te
ctx->prot even if the lookup failed, but it already does that in
some cases so... no issue.
If this was more widely used API we'd rather change it to never
update *prot on failure, but okay we can do this.
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> targ
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This function just does two assignments and and unnecessary check that
> is always true so inline it in the only caller left and remove it.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> --
static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr
> eaddr,
> *protp = ctx.prot;
> *psizep = TARGET_PAGE_BITS;
> return true;
> +} else if (!guest_visible) {
> +return false;
> }
Acked-by: Nicholas Piggin
>
> -if
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This function is not used from any other files so make it static and
> fix the maybe used uninitialised warnings this has uncovered.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/internal.h | 5 +
> target/ppc/mmu_common.c
Will review this if we can get -4 case removed...
Don't know if I'm too keen on doing the fetch branch first
and asymmetric (if vs switch) checking of ret in the fetch
vs data cases. I think with -4 case removed things will
look much nicer.
Thanks,
Nick
On Thu May 2, 2024 at 9:43 AM AEST,
What do you think about adding mmu-book3e.c instead?
Thanks,
Nick
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 300
> 1 file changed, 150 insertions(+), 150 deletions(-)
>
>
he_line_size);
> qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size",
>cpu->env.icache_line_size);
> -if (cpu->env.id_tlbs) {
> +if (cpu->env.tlb_type == TLB_6XX) {
Want to just add the standard comment here?
/* 6xx h
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This series does some further clean up mostly around BookE MMU to
> untangle it from other MMU models. It also contains some other changes
> that I've come up with while working on this. The first 3 patches are
> from the last exception
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> The ppc_hash32_pp_prot() function in mmu-hash32.c is the same as
> pp_check() in mmu_common.c. Rename the latter to ppc_pte_prot() and
> merge with ppc_hash32_pp_prot() to remove duplicated code.
>
> Signed-off-by: BALATON Zoltan
> ---
>
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
> reduce ppc_jumbo_xlate() further.
Nice.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 180 ++--
> 1 file
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> This function is no longer called for BookE MMU model so remove parts
> related to it. This has uncovered a few may be used uninitialised
> warnings that are also fixed.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c
_74xx(CPUPPCState *env)
> return 0;
> }
>
> +static void init_tlbs_4xx(CPUPPCState *env)
> +{
> +#ifndef CONFIG_USER_ONLY
> +env->nb_tlb = 64;
> +env->nb_ways = 1;
> +env->tlb_type = TLB_EMB;
> +#endif
> +}
e200 isn't 4xx though is it? Call it init_T
the XSCOM bridge
implementation, and pnv_adu.c implements the ADU registers and other
functions.
So far, just the ADU no-op registers in the pnv_xscom.c default handler
are moved over to the adu model.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_adu.h | 25 +
include/hw/ppc
- Renamed funcions to pnv_lpc_opb_ prefix rather than pnv_opb_lpc_
- Removed the unnecessary ADU class
Thanks,
Nick
Nicholas Piggin (2):
ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
ppc/pnv: Implement ADU access to LPC space
include/hw/ppc/pnv_adu.h | 32 ++
include/hw/ppc
.
This requires a linkage between adu and lpc, which allows adu to
perform memory access in the lpc space.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_adu.h | 7 +++
include/hw/ppc/pnv_lpc.h | 5 +++
hw/ppc/pnv.c | 4 ++
hw/ppc/pnv_adu.c | 95
:lpc_serirq_mux1
Whereas they previously turn up on lpchc.
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_lpc.h | 12 -
hw/ppc/pnv.c | 38 +--
hw/ppc/pnv_lpc.c | 100 +++
3 files changed, 136 insertions(+), 14 deletions(-)
diff
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Return directly, which is simpler than dragging a return value through
> multpile if and else blocks.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc
On Wed May 8, 2024 at 9:40 AM AEST, BALATON Zoltan wrote:
> On Tue, 7 May 2024, Nicholas Piggin wrote:
> > On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> >> This function is no longer called for BookE MMU model so remove parts
> >> related to it. This has
ile.
If you add a /* quiet used uninitialized warning */ or similar comment
on the memset then.
Reviewed-by: Nicholas Piggin
If you respin you could, put the prot fixes as their own patch but
pretty minor thing if you can't be bothered.
>
> Signed-off-by: BALATON Zoltan
> ---
>
ion from mmu-hash32.c would stop the compiler
> inlining it which results in slightly lower performance.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/internal.h | 35
>
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> As BookE never returns -4 we can drop BookE from the direct store case
> in ppc_jumbo_xlate().
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 7 +--
> 1 file
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
> reduce ppc_jumbo_xlate() further.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Move setting error_code that appears in every case out in front and
> hoist the common fall through case for BOOKE206 as well which allows
> removing the nested switches.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by:
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Merge the code fetch and data access cases in a common switch.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c | 50 +
> 1 file changed, 20 insertions(+), 30 deletions(-)
>
>
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan
Okay for now but we should split into a new file soon.
Acked-by: Nicholas Piggin
> ---
> target/ppc/mmu_common.c | 226
> 1 file changed, 113 insert
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> The value is only used once so no need to introduce a local variable
> for it.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu-radix64.c | 5 ++---
> 1 file changed, 2 inser
sed once. We can drop the local variable and calculate
> it when needed, which makes these checks using it similar to other
> places with such checks.
Sure, why not.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu-hash32.c | 7 ++-
&
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> Checking if a page protection bit is set for a given access type is a
> common operation. Add a macro to avoid repeating the same check at
> multiple places and also avoid a function call. As this relies on
> access type and page
On Wed May 8, 2024 at 10:14 AM AEST, BALATON Zoltan wrote:
> Most exceptions are raised with nip pointing to the faulting
> instruction but the sc instruction generating a syscall exception
> leaves nip pointing to next instruction. Fix gen_sc to not use
> gen_exception_err() which sets nip back
date page flags */
> pte_update_flags(ctx, >tlb.tlb6[best].pte1, ret, access_type);
> }
> +#if defined(DUMP_PAGE_TABLES)
> +if (qemu_loglevel_mask(CPU_LOG_MMU)) {
> +CPUState *cs = env_cpu(env);
> +PowerPCCPU *cpu =
On Wed May 8, 2024 at 10:15 AM AEST, BALATON Zoltan wrote:
> This function is no longer called for BookE MMU model so remove parts
> related to it. This has uncovered a few may be used uninitialised
> warnings that are also fixed.
>
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/mmu_common.c
, and it adds a replay test that runs to the end of the
trace, steps back then forward and verifies the pc.
Signed-off-by: Nicholas Piggin
---
tests/avocado/reverse_debugging.py | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/tests/avocado
, and reverse-stepped from there. This should
load the last auto-snapshot taken.
The test hangs on x86-64 and aarch64 with autosnapshots, so it is
disabled for them.
Signed-off-by: Nicholas Piggin
---
tests/avocado/reverse_debugging.py | 24 ++--
1 file changed, 18 insertions(+), 6
POWER10 hardware implements a degenerate transactional memory facility
in POWER8/9 PCR compatibility modes to permit migration from older
CPUs, but POWER10 / ISA v3.1 mode does not support it so the CPU model
should not support it.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 4
checkstop state does not halt the system, interrupts continue to be
serviced, and other CPUs run. Make it stop the machine with
qemu_system_guest_panicked.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff
Prevent guest state modifying the MSR[ME] bit. Per ISA:
An attempt to modify MSRME in privileged but non-hypervisor state is
ignored (i.e., the bit is not changed).
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target
"MMR" and "SPR SO" are not implemented in POWER9, so clear those bits.
HTM is not set by default, and only later if the cap is set, so remove
the comment that suggests otherwise.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 10 +-
1 file changed, 5 insert
Benjamin Gray (1):
ppc/spapr: Add pa-features for POWER10 machines
Nicholas Piggin (12):
ppc: Drop support for POWER9 and POWER10 DD1 chips
target/ppc: POWER10 does not have transactional memory
ppc/spapr|pnv: Remove SAO from pa-features
ppc/spapr: Remove copy-paste from pa-features
ppc
Change the logging not to print to stderr as well, because a
checkstop is a guest error (or perhaps a simulated machine error)
rather than a QEMU error, so send it to the log.
Update the checkstop message, and log CPU registers too.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c
, which should be good
enough for QEMU debugging.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 16 +++-
target/ppc/helper.h | 4 ++
target/ppc/cpu_init.c| 82 +---
target/ppc/excp_helper.c | 59
This allows different pa-features for powernv8/9/10.
Cc: "Cédric Le Goater"
Cc: "Frédéric Barrat"
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/pnv.c
Copy the pa-features arrays from spapr, adjusting slightly as
described in comments.
Cc: "Cédric Le Goater"
Cc: "Frédéric Barrat"
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 67 --
hw/ppc/spapr.c | 1 +
2 files ch
SAO is a page table attribute that strengthens the memory ordering of
accesses. QEMU with MTTCG does not implement this, so clear it in
ibm,pa-features. This is an obscure feature that has been removed from
POWER10 ISA v3.1, there isn't much concern with removing it.
Signed-off-by: Nicholas
TCG does not support copy/paste instructions. Remove it from
ibm,pa-features. This has never been implemented under TCG or
practically usable under KVM, so it won't be missed.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of
any use in QEMU. Remove them.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 2 --
target/ppc/cpu-models.c | 4
target/ppc/cpu_init.c | 7 ++-
target/ppc/kvm.c| 11 ---
4 files
is separately declared in byte 72,
bit 0 (BE).
Signed-off-by: Benjamin Gray
[npiggin: reword title and changelog, adjust a few bits]
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
The initial MSR state for PAPR specifies MSR[ME] and MSR[FP] are set.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 50523ead25..f3b01b0801 100644
--- a/hw/ppc
Fix an off by one bug.
Cc: Akihiko Odaki
Cc: Alex Bennée
Fixes: 1b53948ff8f70 ("target/ppc: Use GDBFeature for dynamic XML")
Signed-off-by: Nicholas Piggin
---
target/ppc/gdbstub.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/ppc/gdbstub.c b/
Add a ppc64 pseries test. IO in SLOF is very slow when running in
record-replay modes, so this this uses guestfish to extract the
kernel and initrd and boot them directly.
Cc: qemu-...@nongnu.org
Signed-off-by: Nicholas Piggin
---
The test takes about double the length of time of aarch64 and
x86
On Tue Mar 12, 2024 at 7:07 AM AEST, BALATON Zoltan wrote:
> On Mon, 11 Mar 2024, Philippe Mathieu-Daudé wrote:
> > On 11/3/24 19:51, Nicholas Piggin wrote:
> >> From: Benjamin Gray
> >>
> >> Add POWER10 pa-features entry.
> >>
> >> Notably
On Tue Mar 12, 2024 at 4:56 AM AEST, Daniel P. Berrangé wrote:
> On Mon, Mar 11, 2024 at 06:46:53PM +0100, Philippe Mathieu-Daudé wrote:
> > Hi,
> >
> > On 14/12/23 19:17, Cédric Le Goater wrote:
> > > pseries machines before version 2.11 have undergone many changes to
> > > correct issues,
On Tue Mar 12, 2024 at 6:05 AM AEST, Philippe Mathieu-Daudé wrote:
> On 11/3/24 19:51, Nicholas Piggin wrote:
> > From: Benjamin Gray
> >
> > Add POWER10 pa-features entry.
> >
> > Notably DEXCR and and [P]HASHST/[P]HASHCHK instruction support is
> > adv
bool pre_3_0_migration; /* older
> machine don't know about SpaprCpuState */
Acked-by: Nicholas Piggin
I can merge this via the PPC tree.
Thanks,
Nick
> ---
> docs/about/deprecated.rst | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/docs/abo
On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora wrote:
> There is an existing Nested-HV API to enable nested guests on powernv
> machines. However, that is not supported on pseries/PowerVM LPARs.
> This patch series implements required hcall interfaces to enable nested
> guests with KVM on
On Tue Mar 12, 2024 at 4:38 PM AEST, Harsh Prateek Bora wrote:
> Hi Nick,
>
> One minor comment below:
>
> On 2/24/24 13:03, Nicholas Piggin wrote:
> > PPC_VIRTUAL_HYPERVISOR_GET_CLASS is used in critical operations like
> > interrupts and TLB misses and is quite costl
On Tue Mar 12, 2024 at 6:10 PM AEST, Harsh Prateek Bora wrote:
> Hi Nick,
>
> One query/comment below:
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > POWER10 hardware implements a degenerate transactional memory facility
> > in POWER8/9 PCR compatibility modes to
On Tue Mar 12, 2024 at 7:34 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > From: Benjamin Gray
> >
> > Add POWER10 pa-features entry.
> >
> > Notably DEXCR and and [P]HASHST/[P]HASHCHK instruction support is
>
&g
helpful.
Thanks,
Nick
>
> >
> >> Regards,
> >> BALATON Zoltan
> >>
> >>> Co-authored-by: Bernhard Beschow
> >>> Signed-off-by: BALATON Zoltan
> >>> Reviewed-by: Nicholas Piggin
> >>> Tested-by: Bernhard Besc
On Tue Mar 12, 2024 at 6:06 PM AEST, Cédric Le Goater wrote:
> On 3/11/24 19:51, Nicholas Piggin wrote:
> > Copy the pa-features arrays from spapr, adjusting slightly as
> > described in comments.
> >
> > Cc: "Cédric Le Goater"
> > Cc: "Fréd
On Tue Mar 12, 2024 at 7:00 PM AEST, Pavel Dovgalyuk wrote:
> On 11.03.2024 20:40, Nicholas Piggin wrote:
> > record makes an initial snapshot when the machine is created, to enable
> > reverse-debugging. Often the issue being debugged appears near the end of
> > the trac
On Tue Mar 12, 2024 at 2:55 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 10:20, Harsh Prateek Bora wrote:
> >
> >
> > On 3/12/24 00:21, Nicholas Piggin wrote:
> >> The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of
> >> a
On Thu Mar 7, 2024 at 9:03 PM AEST, Chinmay Rath wrote:
> This patch moves the below instructions to decodetree specification :
>
> f{add, sub, mul, div, re, rsqrte, madd, msub, nmadd, nmsub}[s][.] : A-form
> ft{div, sqrt} : X-form
>
>
;frc);
> +get_fpr(t2, a->frb);
> +helper(t3, tcg_env, t0, t1, t2);
> +set_fpr(a->frt, t3);
> +gen_compute_fprf_float64(t3);
> +if (unlikely(a->rc != false)) {
This reads better without the double negative. I.e., just
if (unlikely(a->rc
On Tue Mar 12, 2024 at 7:59 PM AEST, BALATON Zoltan wrote:
> On Tue, 12 Mar 2024, Nicholas Piggin wrote:
> > On Tue Mar 12, 2024 at 7:07 AM AEST, BALATON Zoltan wrote:
> >> On Mon, 11 Mar 2024, Philippe Mathieu-Daudé wrote:
> >>> On 11/3/24 19:51, Nicholas Piggin wro
On Tue Mar 12, 2024 at 8:27 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > Prevent guest state modifying the MSR[ME] bit. Per ISA:
> >
> >An attempt to modify MSRME in privileged but non-hypervisor state is
>
&g
On Tue Mar 12, 2024 at 8:03 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > The initial MSR state for PAPR specifies MSR[ME] and MSR[FP] are set.
> >
> > Signed-off-by: Nicholas Piggin
>
> It would be good to mention PAPR se
On Tue Mar 12, 2024 at 6:56 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 14:18, Nicholas Piggin wrote:
> > On Tue Mar 12, 2024 at 4:38 PM AEST, Harsh Prateek Bora wrote:
> >> Hi Nick,
> >>
> >> One minor comment below:
> &g
as being incompatible with rr?
Thanks,
Nick
>
> On 11.03.2024 20:40, Nicholas Piggin wrote:
> > Using virtual time for announce ensures that guest visible effects
> > are deterministic and don't break replay.
> >
> > Signed-off-by: Nicholas Piggin
> > ---
> &
PAPR API.
>
> Signed-off-by: Harsh Prateek Bora
> Suggested-by: Nicholas Piggin
I still have concerns with exactly how registers are saved and restored,
but it's not necessarily a new problem with v2, and not so much
fundamental design flow more of verifying details so I'm inclined to
> Signed-off-by: Shivaprasad G Bhat
> Signed-off-by: Amit Machhiwal
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> include/hw/ppc/spapr_nested.h | 312 ++
> hw/ppc/spapr_nested.c | 486 +-
&g
POWER10 hardware implements a degenerate transactional memory facility
in POWER8/9 PCR compatibility modes to permit migration from older
CPUs, but POWER10 / ISA v3.1 mode does not support it so the CPU model
should not support it.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
Prevent guest state modifying the MSR[ME] bit. Per ISA:
An attempt to modify MSR[ME] in privileged but non-hypervisor state
is ignored (i.e., the bit is not changed).
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 5 +
1 file changed, 5
Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 2 +-
hw/ppc/spapr.c | 14 ++
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0b47b92baa..aa9786e970 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -150,7 +150,7 @@ static void
On Tue Mar 12, 2024 at 11:24 PM AEST, Alex Bennée wrote:
> Nicholas Piggin writes:
>
> > (H)DEC and PURR get reset before icount does, which causes them to be
> > skewed and not match the init state. This can cause replay to not
> > match the recorded trace e
On Tue Mar 12, 2024 at 11:33 PM AEST, Alex Bennée wrote:
> Nicholas Piggin writes:
>
> > This reverts commit 1f881ea4a444ef36a8b6907b0b82be4b3af253a2.
> >
> > That commit causes reverse_debugging.py test failures, and does
> > not seem to solve the root cause of the
On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora wrote:
> Introduce a SPAPR capability cap-nested-papr which enables nested PAPR
> API for nested guests. This new API is to enable support for KVM on PowerVM
> and the support in Linux kernel has already merged upstream.
>
> Signed-off-by:
t; This is becuase, no read/write call-backs are registered for
> these SPRs. Add support to register generic read/write
> functions to these power10 pmu sprs to fix it.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: Madhavan Srinivasan
> ---
> target/ppc/cpu.h | 6
On Tue Mar 12, 2024 at 10:11 PM AEST, Harsh Prateek Bora wrote:
> Hi Nick,
>
> On 3/12/24 17:21, Nicholas Piggin wrote:
> > On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora wrote:
> >> Introduce a SPAPR capability cap-nested-papr which enables nested PAPR
> >>
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of
any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 2 --
target/ppc/cpu-models.c | 4
target/ppc/cpu_init.c | 7 ++-
target/ppc/kvm.c
Copy the pa-features arrays from spapr, adjusting slightly as
described in comments.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 67 --
hw/ppc/spapr.c | 1 +
2 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv.c b
On Tue Feb 20, 2024 at 6:09 PM AEST, Cédric Le Goater wrote:
> PPC maintainership has been a side activity for the last 2 years and
> it is time to let go some of it now that Nick has taken over.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: Cédric Le Goater
> ---
> MAINTA
capabilities that the Host Partition supports and may use.
>
> [amachhiw: support for p9 compat mode and return register bug fixes]
>
> Signed-off-by: Michael Neuling
> Signed-off-by: Amit Machhiwal
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
for a guest gets deallocated on guest delete.
>
> Signed-off-by: Michael Neuling
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> include/hw/ppc/spapr.h| 2 ++
> include/hw/ppc/spapr_nested.h | 8 +
> h
hineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState
> *spapr,
> + target_ulong lpid);
Why is this made non-static? Doesn't seem to be needed in later patches
either? Other than that,
Reviewed-by: Nicholas Piggin
> #end
> to use it.
>
> The gen_exception() and gen_exception_nip() functions are similar so
> remove code duplication from those too while at it.
>
> Suggested-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
Thanks for doing this one
Reviewed-by: Nicholas Piggin
> -
ets nip back but correctly set nip to
> pc_next so we don't have to patch this in the exception handlers.
>
> Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/excp_helper.c | 43 ++--
> target/ppc/translate.c |
"MMR" and "SPR SO" are not implemented in POWER9, so clear those bits.
HTM is not set by default, and only later if the cap is set, so remove
the comment that suggests otherwise.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 10 +-
This accounts for comments from v1, and drops the attn and
checkstop patches. Will try again next release for those since
they probably fell off peoples' radar this time.
Thanks,
Nick
Benjamin Gray (1):
ppc/spapr: Add pa-features for POWER10 machines
Nicholas Piggin (9):
ppc: Drop support
sh Prateek Bora
> Suggested-by: Nicholas Piggin
Reviewed-by: Nicholas Piggin
> ---
> include/hw/ppc/spapr_nested.h | 3 +++
> hw/ppc/spapr.c| 6 +-
> hw/ppc/spapr_nested.c | 25 ++---
> 3 files changed, 30 insertions(+), 4 deletio
> Signed-off-by: Michael Neuling
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> docs/devel/nested-papr.txt | 119 +
> 1 file changed, 119 insertions(+)
> create mode 100644 docs/devel/nested-papr.txt
>
> diff
he nested guest being deleted. It also supports deleting all nested
> guests at once using a deleteAll flag.
>
> Signed-off-by: Michael Neuling
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> include/hw/ppc/spapr.h| 4 +-
> include/hw/pp
; Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> include/hw/ppc/spapr.h| 3 +
> include/hw/ppc/spapr_nested.h | 23 +++
> hw/ppc/spapr_nested.c | 268 ++
> 3 files changed, 294 insertions(+)
>
> d
declared in byte 72,
bit 0 (BE).
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Benjamin Gray
[npiggin: reword title and changelog, adjust a few bits]
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw
TCG does not support copy/paste instructions. Remove it from
ibm,pa-features. This has never been implemented under TCG or
practically usable under KVM, so it won't be missed.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 8 ++--
1 file changed, 6
The initial MSR state for the OpenFirmware binding specifies
MSR[ME] and MSR[FP] are set.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc
This allows different pa-features for powernv8/9/10.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index aa9786e970..52d964f77a 100644
--- a/hw/ppc/pnv.c
>
> Signed-off-by: Michael Neuling
> Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
> ---
> target/ppc/cpu.h | 2 +
> hw/ppc/ppc.c | 10 ++
> hw/ppc/spapr_nested.c | 334 ++
> 3 files changed
return;
> +} else {
> +spapr->nested.api = NESTED_API_PAPR;
> +}
> +
> +} else if (kvm_enabled()) {
> + /*
> + * this gets executed in L1 qemu when L2 is launched,
> + * needs kvm-hv support in L1 kernel.
> + */
>
On Tue Mar 12, 2024 at 8:36 PM AEST, Nicholas Piggin wrote:
> On Tue Mar 12, 2024 at 7:28 PM AEST, Bernhard Beschow wrote:
> >
> >
> > Am 9. März 2024 11:34:56 UTC schrieb BALATON Zoltan :
> > >On Thu, 29 Feb 2024, BALATON Zoltan wrote:
> > >>
On Wed Mar 13, 2024 at 12:01 AM AEST, Richard Henderson wrote:
> On 3/11/24 23:36, Nicholas Piggin wrote:
[snip]
> >
> > #define FPU_HELPER(name, op, flags_handler) \
> > float64 helper_##name(CPUPPCState *env, float
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