The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 31 +++
1 file changed, 23 insertions
PPR32 provides access to the upper half of PPR.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h| 1 +
target/ppc/spr_common.h | 2 ++
target/ppc/cpu_init.c | 12
target/ppc/translate.c | 16
4 files changed, 31 insertions(+)
diff --git a/target
and reset functions
Signed-off-by: Glenn Miles
[npiggin: rebase and minor compile fixes]
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 17 +
target/ppc/power8-pmu.h| 7 ++
target/ppc/cpu_init.c | 37 +-
tar
This implements SPRC/SPRD SPRs, and SCRATCH0-7 registers.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 7 +++--
target/ppc/helper.h | 3 ++
target/ppc/spr_common.h | 3 ++
target/ppc/cpu_init.c| 10 ++
target/ppc/misc_helper.c | 66
AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR
registers with simple (generic) implementations.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc
LDBAR, TTR are a Power-specific SPRs. These simple implementations
are enough for IBM proprietary firmware for now.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c | 10 ++
2 files changed, 12 insertions(+)
diff --git a/target/ppc/cpu.h b/target
to TBL, TBU, WR_TBL, WR_TBU, respectively.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 8
target/ppc/helper_regs.c | 10 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index
From: Saif Abrar
SPR's CFAR, DEC, HDEC, TB-L/U are not implemented as part of CPUPPCState.
Hence, gdbstub is not able to access them using (CPUPPCState *)env->spr[] array.
Update gdb_get_spr_reg() method to handle these SPR's specifically.
Signed-off-by: Saif Abrar
Signed-off
ead TBL on 32-bit.
Change SPR 268 to be called TB on 64-bit implementations.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 4
target/ppc/ppc-qmp-cmds.c | 4
2 files changed, 8 insertions(+)
diff --git a/target/ppc/helper_regs.c b/target/
Wire the ChipTOD model to powernv9 and powernv10 machines.
Suggested-by-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_chip.h | 3 +++
hw/ppc/pnv.c | 30 ++
2 files changed, 33 insertions(+)
diff --git a/include/hw/ppc
PTCR is a per-core register.
Signed-off-by: Nicholas Piggin
---
target/ppc/misc_helper.c | 16 ++--
target/ppc/translate.c | 4
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index e3b20a8935..5317713fc3
An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means
per-thread or per-core, depending on 1LPAR mode.
Signed-off-by: Nicholas Piggin
---
target/ppc/spr_common.h | 2 ++
target/ppc/translate.c | 26 ++
2 files changed, 28 insertions(+)
diff --git a
: Nicholas Piggin
---
target/ppc/cpu.h | 36 ++
target/ppc/timebase_helper.c | 210 ++-
2 files changed, 243 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 9d115e539e..54150d5a08 100644
--- a/target/ppc/cpu.h
normal with the exception that the mfbhrbe instruction will
always return a zero value.
Signed-off-by: Glenn Miles
[npiggin: rebase and minor compile fixes]
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 2 ++
target/ppc/helper.h | 7
target/ppc
msgsnd has a broadcast mode that sends hypervisor doorbells to all
threads belonging to the same core as the target. A "subcore" mode
sends to all or one thread depending on 1LPAR mode.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 6 +-
target/pp
ted).
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 8287494c39..b732a1b06e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -920,6 +920,18 @@ static v
The DECAR SPR is 32-bits width.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 421900cd11..8287494c39 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
, which should be good
enough for QEMU debugging.
Signed-off-by: Nicholas Piggin
---
Since v1:
- New patch that also uses checkstop function
Since v2:
- Include support for 970.
- Add class attn enable check, similar to check_pow.
---
target/ppc/cpu.h | 16 +++-
target/ppc/helper.h
error. CPU registers are dumped.
Signed-off-by: Nicholas Piggin
---
Since v1:
- Fix loop exit so it stops on the checkstop-causing instruction, rather than
after it.
Since v2:
- Use qemu_system_guest_panicked rather than vm_stop (Richard)
- Move away from printing to stderr (Zoltan)
- Reduce
Try these again. checkstop fix is mostly unchanged since last
posted, but several fixes to attn. Seems to work well enough.
Thanks,
Nick
Nicholas Piggin (2):
target/ppc: Make checkstop actually stop the system
target/ppc: Implement attn instruction on BookS 64-bit processors
target/ppc
On Fri Jan 19, 2024 at 6:58 PM AEST, Cédric Le Goater wrote:
> Hello Nick,
>
> On 1/18/24 16:06, Nicholas Piggin wrote:
> > This is mostly TCG core emulation improvements and fixes. I
> > got the chiptod model in there because it's intertwined with
> > TFMR SPR.
&g
On Fri Jan 19, 2024 at 10:23 AM AEST, David Gibson wrote:
> On Fri, Jan 19, 2024 at 12:09:36AM +1000, Nicholas Piggin wrote:
> > SAO is a page table attribute that strengthens the memory ordering of
> > accesses. QEMU with MTTCG does not implement this, so clear it in
> > ibm,
On Fri Jan 19, 2024 at 8:09 AM AEST, Richard Henderson wrote:
> On 1/19/24 02:25, Nicholas Piggin wrote:
> > +/* attn enable check
> > */
> > +static inline int check_attn_none(CPUPPCState *env)
>
> Don't
On Mon Jan 22, 2024 at 6:54 PM AEST, Thomas Huth wrote:
> On 22/01/2024 05.11, Junho wrote:
> > Hello,
> >
> > I'm a QEMU user with PowerPc target architecture.
> > I have some personal modifications related to tb jmp cache and chaining
> > logic to improve the performance of a specific guest cod
On Wed Nov 22, 2023 at 5:32 PM AEST, Shivaprasad G Bhat wrote:
> Extend the existing watchpoint facility from TCG DAWR0 emulation
> to DAWR1 on POWER10.
>
> As per the PAPR, bit 0 of byte 64 in pa-features property
> indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
> DAWR
djust the tets harness to avoid it.
Thanks,
Nick
On Thu Jan 18, 2024 at 12:12 AM AEST, Nicholas Piggin wrote:
> Add test for POWER10.
>
> Reviewed-by: Cédric Le Goater
> Signed-off-by: Nicholas Piggin
> ---
> tests/avocado/boot_linux_console.py | 8
> 1 file changed
: Nicholas Piggin
---
tests/avocado/boot_linux_console.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.py
index 3f0180e1f8..922a9e7b79 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado
On Thu Jan 25, 2024 at 1:11 PM AEST, David Gibson wrote:
> On Tue, Jan 23, 2024 at 11:57:56AM +1000, Nicholas Piggin wrote:
> > On Fri Jan 19, 2024 at 10:23 AM AEST, David Gibson wrote:
> > > On Fri, Jan 19, 2024 at 12:09:36AM +1000, Nicholas Piggin wrote:
> > > >
When replaying a trace, it is possible to go from shutdown to
running with a reverse-debugging step. This can be useful if the
problem being debugged triggers a reset or shutdown.
Signed-off-by: Nicholas Piggin
---
include/sysemu/runstate.h | 1 +
replay/replay.c | 2 ++
system
oders.
Nicholas Piggin (4):
replay: allow runstate shutdown->running when replaying trace
scripts/replay-dump.py: Update to current rr record format
scripts/replay-dump.py: rejig decoders in event number order
tests/avocado: excercise scripts/replay-dump.py in replay tests
includ
Sort decoder functions to be ascending in order of event number,
same as the decoder tables.
Signed-off-by: Nicholas Piggin
---
scripts/replay-dump.py | 56 +-
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/scripts/replay-dump.py b
The v12 format support for replay-dump has a few issues still. This
fixes async decoding; adds event, shutdown, and end decoding; fixes
audio in / out events, fixes checkpoint checking of following async
events.
Signed-off-by: Nicholas Piggin
---
scripts/replay-dump.py | 132
This runs replay-dump.py after recording a trace, and fails the test if
the script fails.
replay-dump.py is modified to exit with non-zero if an error is
encountered while parsing, to support this.
Signed-off-by: Nicholas Piggin
---
scripts/replay-dump.py | 6 --
tests/avocado
On Tue Apr 23, 2024 at 4:30 PM AEST, Harsh Prateek Bora wrote:
> + qemu-devel
>
> On 4/23/24 11:40, Harsh Prateek Bora wrote:
> > On ppc64, the PowerVM hypervisor runs with limited memory and a VCPU
> > creation during hotplug may fail during kvm_ioctl for KVM_CREATE_VCPU,
> > leading to terminatio
On Mon May 13, 2024 at 9:49 PM AEST, Cédric Le Goater wrote:
> Hello,
>
> On 5/10/24 16:30, Nicholas Piggin wrote:
> > The POWER8 LPC ISA device irqs all get combined and reported to the line
> > connected the PSI LPCHC irq. POWER9 changed this so only internal LPC
> &g
On Thu May 16, 2024 at 11:35 PM AEST, Salil Mehta wrote:
>
> > From: Harsh Prateek Bora
> > Sent: Thursday, May 16, 2024 2:07 PM
> >
> > Hi Salil,
> >
> > On 5/16/24 17:42, Salil Mehta wrote:
> > > Hi Harsh,
> > >
> > >> From: Harsh Prateek Bora
> > >> Sent: Thursday, May 16, 2024
On Thu May 16, 2024 at 2:31 PM AEST, Harsh Prateek Bora wrote:
> Hi Nick,
>
> On 5/14/24 08:39, Nicholas Piggin wrote:
> > On Tue Apr 23, 2024 at 4:30 PM AEST, Harsh Prateek Bora wrote:
> >> + qemu-devel
> >>
> >> On 4/23/24 11:40, Harsh Prateek Bora wro
On Mon May 13, 2024 at 9:27 AM AEST, BALATON Zoltan wrote:
> Add ppc_real_mode_xlate() to handle real mode translation and allow
> removing this case from ppc_jumbo_xlate().
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc
On Mon May 13, 2024 at 9:28 AM AEST, BALATON Zoltan wrote:
> This function is used only once, its return value is ignored and one
> of its parameter is a return value from a previous call. It is better
> to inline it in the caller and remove it.
Debatable. It's definitely clunky code that could us
On Mon May 13, 2024 at 9:27 AM AEST, BALATON Zoltan wrote:
> Introduce ppc_40x_xlate() to split off 40x handlning leaving only 6xx
> in ppc_jumbo_xlate() now.
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc/
On Mon May 13, 2024 at 9:27 AM AEST, BALATON Zoltan wrote:
> Now that only 6xx cases left in ppc_jumbo_xlate() we can change it
> to ppc_6xx_xlate() also removing get_physical_address_wtlb().
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: BALATON Zoltan
> ---
> target/ppc
pe access_type)
> {
> -switch (access_type) {
> -case MMU_INST_FETCH:
> -return PAGE_EXEC;
> -case MMU_DATA_LOAD:
> -return PAGE_READ;
> -case MMU_DATA_STORE:
> -return PAGE_WRITE;
> -}
> -g_assert_not_reached();
>
mmu-hash32.c would stop the compiler inlining it which
> results in slightly lower performance.
>
It's already hard to review patches that move code around, it's better
to keep the changes before/after the move unless really necessary.
For mmu_common.c hunks,
Reviewed-by: Nicholas Pig
On Mon May 13, 2024 at 9:28 AM AEST, BALATON Zoltan wrote:
> The mmask local variable is a less descriptive local name for a
> constant. Drop it and use the constant directly in the two places it
> is needed.
Wow, lots more. I might take up to patch 34ish for first PR.
Thanks,
Nick
>
> Signed-of
On Mon May 13, 2024 at 9:28 AM AEST, BALATON Zoltan wrote:
> This is used only once and can be inlined.
This reminds me, ppc_hash32_pp_prot() calculates prot from
pp and nx (which is not from pp but from segment) and from
key of course. It could be renamed to say ppc_hash32_prot().
Maybe do that w
On Tue Apr 23, 2024 at 4:32 PM AEST, Chinmay Rath wrote:
> Moving the below instructions to decodetree specification :
>
> divd[u, e, eu][o][.]: XO-form
> mod{sd, ud} : X-form
>
> With this patch, all the fixed-point arithmetic instructions have been
> moved to decodetre
On Mon Apr 29, 2024 at 3:13 PM AEST, Chinmay Rath wrote:
> Moving VMX instructions of the following types to decodetree
> specification : storage access, integer logical & integer max/min.
FYI I've added these to
https://gitlab.com/npiggin/qemu/-/commits/ppc-next-test
With the 32-bit fixes. I'll
On Mon May 13, 2024 at 9:27 AM AEST, BALATON Zoltan wrote:
> This series does some further clean up mostly around BookE MMU to
> untangle it from other MMU models. It also contains some other changes
> that I've come up with while working on this. The Simplify
> ppc_booke_xlate() part 1 and part 2
checkstop state does not halt the system, interrupts continue to be
serviced, and other CPUs run. Make it stop the machine with
qemu_system_guest_panicked.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff
This is a bunch of instruction and register additions, improved SMT
support, etc. for TCG.
Thanks,
Nick
Nicholas Piggin (14):
target/ppc: larx/stcx generation need only apply DEF_MEMOP() once
target/ppc: Remove redundant MEMOP_GET_SIZE macro
target/ppc: Make checkstop actually stop the
PPR32 provides access to the upper half of PPR.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h| 1 +
target/ppc/spr_common.h | 2 ++
target/ppc/cpu_init.c | 12
target/ppc/translate.c | 16
4 files changed, 31 insertions(+)
diff --git a/target
Use DEF_MEMOP() consistently in larx and stcx. generation, and apply it
once when it's used rather than where the macros are expanded, to reduce
typing.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff
The DECAR SPR is 32-bits width.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 71da8d4856..462246cb7d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
7;t been tested.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 462246cb7d..e186da5ef1 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -920,6
msgsnd has a broadcast mode that sends hypervisor doorbells to all
threads belonging to the same core as the target. A "subcore" mode
sends to all or one thread depending on 1LPAR mode.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 6 +-
target/pp
Change the logging not to print to stderr as well, because a
checkstop is a guest error (or perhaps a simulated machine error)
rather than a QEMU error, so send it to the log.
Update the checkstop message, and log CPU registers too.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c
AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR
registers with simple (generic) implementations.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc
.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 7 +++--
target/ppc/helper.h | 3 ++
target/ppc/spr_common.h | 3 ++
target/ppc/cpu_init.c| 10 ++
target/ppc/misc_helper.c | 66
target/ppc/translate.c | 18 +++
6
, which should be good
enough for QEMU debugging.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 16 +++-
target/ppc/helper.h | 1 +
target/ppc/cpu_init.c| 82 +---
target/ppc/excp_helper.c | 39 +++
target/ppc
An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means
per-thread or per-core, depending on 1LPAR mode.
Signed-off-by: Nicholas Piggin
---
target/ppc/spr_common.h | 2 ++
target/ppc/translate.c | 26 ++
2 files changed, 28 insertions(+)
diff --git a
LDBAR, TTR are a Power-specific SPRs. These simple implementations
are enough for IBM proprietary firmware for now.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c | 10 ++
2 files changed, 12 insertions(+)
diff --git a/target/ppc/cpu.h b/target
PTCR is a per-core register.
Signed-off-by: Nicholas Piggin
---
target/ppc/misc_helper.c | 16 ++--
target/ppc/translate.c | 4
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 6f419c9346..a67930d031
There is a memop_size() function for this.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 0882fe2fd2..cf2404330b 100644
--- a/target/ppc/translate.c
+++ b
The ibm,pi-features property has a bit to say whether or not
msgsndp should be used. Linux checks if it is being run under
KVM and avoids msgsndp anyway, but it would be preferable to
rely on this bit.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 27 +++
1 file
On Sat May 18, 2024 at 8:48 PM AEST, Richard Henderson wrote:
> On 5/17/24 14:48, Nicholas Piggin wrote:
> > On Tue Apr 23, 2024 at 4:32 PM AEST, Chinmay Rath wrote:
> >> Moving the below instructions to decodetree specification :
> >>
> >>divd[u, e, eu][o
On Sat May 18, 2024 at 9:05 PM AEST, Richard Henderson wrote:
> On 5/18/24 11:31, Nicholas Piggin wrote:
> > @@ -425,17 +426,17 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu,
> > target_ulong vector,
> > env->reserve_addr = -1;
> &g
On Sat May 18, 2024 at 9:07 PM AEST, Richard Henderson wrote:
> On 5/18/24 11:31, Nicholas Piggin wrote:
> > +static void gen_attn(DisasContext *ctx)
> > +{
> > +#if defined(CONFIG_USER_ONLY)
> > +GEN_PRIV(ctx);
> > +#else
> > +gen_helper_attn(tcg_env
On Sat May 18, 2024 at 9:26 PM AEST, Richard Henderson wrote:
> On 5/18/24 11:31, Nicholas Piggin wrote:
> > +void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn)
> > +{
> > +TCGv t0 = tcg_temp_new();
> > +if (!(ct
On Mon May 20, 2024 at 7:06 AM AEST, Salil Mehta wrote:
> KVM vCPU creation is done once during the vCPU realization when Qemu vCPU
> thread
> is spawned. This is common to all the architectures as of now.
>
> Hot-unplug of vCPU results in destruction of the vCPU object in QOM but the
> correspond
On Mon May 20, 2024 at 7:06 AM AEST, Salil Mehta wrote:
> Virtual CPU Hot-unplug leads to unrealization of a CPU object. This also
> involves destruction of the CPU AddressSpace. Add common function to help
> destroy the CPU AddressSpace.
Patches 6,7 seem okay to me. I would like to see a series w
checkstop state does not halt the system, interrupts continue to be
serviced, and other CPUs run. Make it stop the machine with
qemu_system_guest_panicked.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff
T and serialization checks
in spr_core_write_generic32() (Richard)
- Move attn to decodetree.
Thanks
Nick
Nicholas Piggin (12):
target/ppc: Make checkstop actually stop the system
target/ppc: improve checkstop logging
target/ppc: Implement attn instruction on BookS 64-bit processors
target/ppc:
PTCR is a per-core register.
Signed-off-by: Nicholas Piggin
---
target/ppc/misc_helper.c | 16 ++--
target/ppc/translate.c | 4
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 6f419c9346..a67930d031
.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 7 +++--
target/ppc/helper.h | 3 ++
target/ppc/spr_common.h | 3 ++
target/ppc/cpu_init.c| 10 ++
target/ppc/misc_helper.c | 66
target/ppc/translate.c | 18 +++
6
7;t been tested.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 927721d49a..892fb6ce02 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -920,6
, which should be good
enough for QEMU debugging.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 12 +
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 ++
target/ppc/cpu_init.c| 69
The DECAR SPR is 32-bits width.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ee01415c32..927721d49a 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
msgsnd has a broadcast mode that sends hypervisor doorbells to all
threads belonging to the same core as the target. A "subcore" mode
sends to all or one thread depending on 1LPAR mode.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 6 +-
target/pp
An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means
per-thread or per-core, depending on 1LPAR mode.
Signed-off-by: Nicholas Piggin
---
target/ppc/spr_common.h | 2 ++
target/ppc/translate.c | 28
2 files changed, 30 insertions(+)
diff --git a
LDBAR, TTR are a Power-specific SPRs. These simple implementations
are enough for IBM proprietary firmware for now.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c | 10 ++
2 files changed, 12 insertions(+)
diff --git a/target/ppc/cpu.h b/target
AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR
registers with simple (generic) implementations.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc
Change the logging not to print to stderr as well, because a
checkstop is a guest error (or perhaps a simulated machine error)
rather than a QEMU error, so send it to the log.
Update the checkstop message, and log CPU registers too.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c
PPR32 provides access to the upper half of PPR.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h| 1 +
target/ppc/spr_common.h | 2 ++
target/ppc/cpu_init.c | 12
target/ppc/translate.c | 16
4 files changed, 31 insertions(+)
diff --git a/target
not the counterpart of
kvm_destroy_vcpu, etc.. It is not your fault the existing naming
makes this a bit confusing. Fortunately it's pretty well contained
to small amount of code.
I hate to nitpick it but since the functions are being exported,
would it be a better name somthing like kvm_attach_vcp
On Mon May 20, 2024 at 8:55 PM AEST, Salil Mehta wrote:
> > From: Nicholas Piggin
> > Sent: Monday, May 20, 2024 9:19 AM
> >
> > On Mon May 20, 2024 at 7:06 AM AEST, Salil Mehta wrote:
> > > Virtual CPU Hot-unplug leads to unrealization of a CPU object. This
;
> On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> > attn is an implementation-specific instruction that on POWER (and G5/
> > 970) can be enabled with a HID bit (disabled = illegal), and
> > executing
> > it causes the host processor to stop and the s
On Wed May 22, 2024 at 3:34 AM AEST, Richard Henderson wrote:
> On 5/20/24 18:30, Nicholas Piggin wrote:
> > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> > index c358927211..2532408be0 100644
> > --- a/target/ppc/cpu.h
> > +++ b/target/ppc/cpu.h
> > @@ -302
On Wed May 22, 2024 at 3:40 AM AEST, Richard Henderson wrote:
> On 5/20/24 18:30, Nicholas Piggin wrote:
> > +void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn)
> > +{
> > +TCGv t0 = tcg_temp_new();
> > +
> > +tcg_gen_shli_tl(t0, cpu_gpr[gprn], 32
PPR32 provides access to the upper half of PPR.
Signed-off-by: Nicholas Piggin
---
v3:
- Don't clobber lower half of PPR.
- Add spr_load_dump_spr (spr_store_dump_spr was already there).
target/ppc/cpu.h| 1 +
target/ppc/spr_common.h | 2 ++
target/ppc/cpu_init.c
Merge the user-only and full implementations together, and only
call translator_io_start() and only create and set the label
when necessary.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 55 +-
1 file changed, 28 insertions(+), 27 deletions
#x27;s not urgent but
you're the guru with this stuff and I'm hesitant to change it
without a better opinion ... Simple band aid for the meanwhile
could be leave it as is but just disable counting if
record/replay is in use.
Thanks,
Nick
Nicholas Piggin (2):
target/ppc: Fix PMC5 instructi
a bit clearer but objections welcome.
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 162 +
1 file changed, 82 insertions(+), 80 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 49dee6cab0..344e78843c 100644
pe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 2 +-
target/ppc/mmu_helper.c | 2 +-
target/ppc/translate.c | 7 +++
target/ppc/translate/storage-ctrl-impl.c.inc | 7 +++
4 files changed, 16
The ibm,pi-features property has a bit to say whether or not
msgsndp should be used. Linux checks if it is being run under
KVM and avoids msgsndp anyway, but it would be preferable to
rely on this bit.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 28
% [.] address_space_translate_internal
3.17% [.] object_class_dynamic_cast_assert
2.84% [.] ppc_radix64_xlate
Keep a pointer to the class and avoid this lookup. This reduces the
execution time to 40 seconds.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/pegasos2.c
eviewed-by: Richard Henderson
Signed-off-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc/helper.h| 4 +--
target/ppc/insn32.decode | 5
target/ppc/int_helper.c| 4 +--
target/ppc/translate.c
From: Chinmay Rath
This patch merges the definitions of the following set of fpu helper methods,
which are similar, using macros :
1. f{add, sub, mul, div}(s)
2. fre(s)
3. frsqrte(s)
Reviewed-by: Nicholas Piggin
Signed-off-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc
Memory barriers are supposed to do something on BookE systems, these
were probably just missed during MTTCG enablement, maybe no targets
support SMP. Either way, add proper BookE implementations.
Reviewed-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc/translate/misc-impl.c.inc
ing it decodetree compatible, so that the
mentioned insns can be safely move to decodetree specs.
Reviewed-by: Richard Henderson
Signed-off-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/targ
ister fields in the HFLAGS_BHRB_ENABLE hflag:
MMCR0[FCP] - Determines if BHRB recording is frozen in the
problem state
MMCR0[FCPC] - A modifier for MMCR0[FCP]
MMCRA[BHRBRD] - Disables all BHRB recording for a thread
Reviewed-by: Nicholas Piggin
Signed-o
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