This patch adds a platform device driver that supports the OpenCores SPI
controller.
The driver expects two resources: an IORESOURCE_MEM resource defining the
core's memory-mapped registers and an IORESOURCE_IRQ for the associated
interrupt. It also requires a clock, spi-master-clk, used to
* Thierry Reding wrote:
This patch adds a platform device driver that supports the OpenCores SPI
controller.
The driver expects two resources: an IORESOURCE_MEM resource defining the
core's memory-mapped registers and an IORESOURCE_IRQ for the associated
interrupt. It also requires a clock,
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* David Brownell wrote:
On Tuesday 28 April 2009, Thierry Reding wrote:
This second version is pretty much a rewrite.
That happens sometimes...
Some notes about the most
important changes:
* uses per-chip states to allow more slaves to use the controller
concurrently
On Tuesday 28 April 2009, Thierry Reding wrote:
This second version is pretty much a rewrite.
That happens sometimes...
Some notes about the most
important changes:
* uses per-chip states to allow more slaves to use the controller
concurrently
* rejects invalid device
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Le Tuesday 28 April 2009 14:20:11 Thierry Reding, vous avez écrit :
* David Brownell wrote:
On Tuesday 28 April 2009, Thierry Reding wrote:
This second version is pretty much a rewrite.
That happens sometimes...
Some notes about the most
important changes:
* uses per-chip
On Tuesday 28 April 2009, Florian Fainelli wrote:
Is this the http://www.opencores.org/?do=projectwho=spi core?
Yes, it is.
Its summary says Variable length of transfer word up to 32 bits;
does that mean configurable when core is synthesized instead of
truly variable?
This is
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