Hi Javier,
As far as I understand in WR both references are synchronous. Why don't you
try to track both references (or N references) simultanously? If you take
care of the design, your performance should increase while locked and the
transition from one reference to the other if you ever miss one
> ...The problem is that this decoded data clock is locked to the incoming
> data by means of a PFD in the Spartan6/Virtex6 GTP. The PFD normaly only
> looks at rising edges, so any change in the clock duty cycle will translate
> in a phase change in the falling edge and not in the rising edge. I
Hi Warren,
I arrive a bit late to this discussion, but I hope I can help. I guess the
reason for using only one edge is based on the fact that WR is originally
designed to measure the phase between a decoded data clock and a system
clock. The problem is that this decoded data clock is locked to th
> The current implementation used in WR was developed by Tomasz
> Wlostowski in the frame of his MSc thesis, following the ideas of
> Pablo Alvarez which Bruce pointed to earlier. As you can see in
> Tomasz's dissertation [1], there was not a lot of investigation on
> optimal
I would not fully trust NTP, and as already explained taking your GPS
outside as a reference for just a while is not really going to help.
But..why not using GPS inside the building? Some receivers are quite
sensitive, so probably you will not need an external antenna to pick up a
signal. Probably
Hi guys,
I have uploaded a new version of the CTRI-Scope measurement. There was a
typo on a number and several descriptions that has probably excited more
than one person and that has triggered my stress to levels I did not know
until now.
Having said that, have a look at it again if you are inte
We are adding more info to the wiki project. Please go directly to
http://www.ohwr.org/projects/cngs-time-transfer/wiki/Wiki
Cheers,
pablo
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Well it seems there are some time-nuts looking.
Here you have it, for the moment.
*BCT, Beam Current Transformer
*CCR, Cern's Control Room.
*cfc-ccr-ctpps, The front end (a PC running SC5 linux) where we have
installed the CTRI that logs the PPS comming from the PolarRx2e
*cfc-hca4-saos12. The
Hi guys,
Here you have the reports on the CERN's timing chain.
http://www.ohwr.org/documents/111
Questions are welcome!
pablo
On Mon, Sep 26, 2011 at 2:46 PM, Joe Gwinn wrote:
> At 6:56 AM + 9/26/11, time-nuts-requ...@febo.com wrote: (really Javier
> S)
>
>> Date: Mon, 26 Sep 2011 08:56:
rds
pablo
On Fri, Jan 28, 2011 at 2:47 PM, pablo alvarez <
pabloalvarezsanc...@gmail.com> wrote:
> Hi,
>
> The AD9850 has a 10bit DAC. If the AD9850 does not dither the 10bit ADC
> output the zero crossings for a 1MHz signal will have an aprox resolution of
> 2^-10*1us~1ns o
Hi,
The AD9850 has a 10bit DAC. If the AD9850 does not dither the 10bit ADC
output the zero crossings for a 1MHz signal will have an aprox resolution of
2^-10*1us~1ns on average. If the lookup table feeding values to the dac has
10 address lines (just guessing, I do not see any anything on it on t
(probably the simplest is to go for the good old
rs232).
In principle I will do all the code in VHDL so you will not have any
problem in porting it to any device.
Cheers
pablo
On Thu, Dec 4, 2008 at 2:18 AM, Bruce Griffiths
<[EMAIL PROTECTED]> wrote:
> pablo alvarez wrote:
>>
thanks for the positive feedback,
In xilinx fpgas, for example, the recovery time after a metastability
issue is quite fast as reported in this paper
http://www.xilinx.com/support/documentation/application_notes/xapp094.pdf
The capture window of metastable state is 0.01fm (page 2). Probably
this
Hi,
I have been looking at several Dual Mixer Time Difference designs. As
far as I know the basic architecture is based on generating a tone
with an small frequency offset respect to the nominal clocks
frequency, analogue mixing of the clocks, low pass filtering, then a
slow zero crossing detector
Thanks Tim and Bruce for your info! It is precious.
By the way you will have all the schematics and sources will be on the
web. I will keep you informed.
> 1) The HP5359A (and the 5370A/B) used a phase locked startable oscillator.
> The classic gated oscillator uses a delay line to determine the
Dear nuts,
I am designing a card that should be able to delay a trigger from 25ns
up to several seconds in 10ps steps. The card will use an external
10MHz as frequency reference.
I have thought of two architectures. One is a counter clocked by a
keyed oscillator followed by a fine delay and the o
); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED] RETRY
> -Original Message-
> From: Magnus Danielson [mailto:[EMAIL PROTECTED]
> Sent: Monday, August 06, 2007 8:49 PM
> To: Pablo Alvarez Sanchez
> Cc: time-nuts@febo.com
> Subject: Re: [time-nuts] PLL
0ps between two modules
for several minutes.
The hold over I have obtained with the cft-125 is better than 5us for
30min (normally much better)
Pablo ALVAREZ SANCHEZ
CERN - AB Department
CH-1211 Geneva 23
GSM : +41 (0)76 48 72191
Phone : +41 (0)22 76 78431
Fax : +41 (0)22 76 69318
Build
); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED] RETRY
First of all thanks a lot for your answers.
> For a facility like CERN, I think that normal cabel
> assymetries will be sufficiently low such that they would not
> require explicit handling, unless you have higher
> synchro
ndard PHY?
Thanks for you attention
Pablo
-----
Pablo ALVAREZ SANCHEZ
CERN - AB Department
CH-1211 Geneva 23
GSM : +41 (0)76 48 72191
Phone : +41 (0)22 76 78431
Fax : +41 (0)22 76 69318
Building : 864-1-A30
___
time-nuts ma
Hi,
I am curious about the total stability of Cs clocks. Normally producers give
you an initial accuracy after 30 minutes of power on and a table with the Allan
deviation for different measurement intervals.
After that they give you the environmental and physical specifications. For the
hp50
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