Bob Camp wrote:
Hi
Good point, pretty much everything I worry about is timing to or from an external pin.
Once it's inside it's all clocked to the global clock(s).
If you look at the modern families, you no longer have only clocking
on both edges... but even higher rates.
The I/O-block
Tom Van Baak wrote:
Hi David,
Thanks for the detailed comments. I understand better
how the two boards differ now. You did a fine job. And
thanks for making it available to the group, with good
documentation and all.
One comment in the use of microcontrollers -- a reason
I (and many others)
Hi
Can we all come live at your house and play with your toys?
Bob
On Mar 20, 2010, at 10:06 AM, Magnus Danielson wrote:
Tom Van Baak wrote:
Hi David,
Thanks for the detailed comments. I understand better
how the two boards differ now. You did a fine job. And
thanks for making it
Bob Camp wrote:
Hi
Can we all come live at your house and play with your toys?
That would cause some troubles with logistics, like places to sleep. ;)
Tom has far more toys than me. I might have a few things he doesn't
have, but other than that he outperforms me in most fields.
So far,
Hi
I have a tent
Somehow I suspect that commuting to work on a daily basis just might be a
little difficult.
Bob
On Mar 20, 2010, at 12:07 PM, Magnus Danielson wrote:
Bob Camp wrote:
Hi
Can we all come live at your house and play with your toys?
That would cause some troubles
When you run a design on a CPLD (or a FPGA) the design tool optimizes cute
things like fanout and timing. You can also have it optimize delay to
circuit nodes. That allows you to come up with outputs that have a specific
delay relationship.
From my experience, specific delay relationship
Hi
I've had pretty good luck with Quartus setting up delay relationships and
optimizing for them. You are correct that you do get speed variations from the
slow model to the fast model. Getting it all to work out is usually a two step
process. Find the delay clusters and then shove the
Bob Camp wrote:
Hi
I've had pretty good luck with Quartus setting up delay relationships and optimizing for them. You are correct that you do get speed variations from the slow model to the fast model. Getting it all to work out is usually a two step process. Find the delay clusters and then
Hi
Good point, pretty much everything I worry about is timing to or from an
external pin. Once it's inside it's all clocked to the global clock(s).
Bob
On Mar 20, 2010, at 6:41 PM, Magnus Danielson wrote:
Bob Camp wrote:
Hi
I've had pretty good luck with Quartus setting up delay
David,
Did you see the TAPR TADD board(s) before you started
your divider project? I'm curious what features (or missing
features) led you to your board design.
Thanks,
/tvb
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-Original Message-
From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf
Of Tom Van Baak
Sent: 19 March 2010 21:33
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Schematic and BOM
time and frequency
measurement' time-nuts@febo.com
Sent: Friday, March 19, 2010 4:11 PM
Subject: RE: [time-nuts] Schematic and BOM
Tom,
I designed the original version of the board in 2008. I think the TADD2 came along a few months after I did the
first
batch of boards.
If I remember
, March 19, 2010 4:11 PM
Subject: RE: [time-nuts] Schematic and BOM
Tom,
I designed the original version of the board in 2008. I think the TADD2
came along a few months after I did the first
batch of boards.
If I remember correctly, John Ackermann expressed some interest at the time
Bill,
just re-join the end of the names that have been split to the next line of the
post.
Again sent to the list 'cos your ISP still refuses email from me.
Apologies to the list
Regards,
David Partridge
Email:david.partri...@perdrix.co.uk
-Original Message-
From: mason...@wcc.net
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