On Mon, 19 Sep 2011 03:52:15 +0200
Peter Krengel krengelda...@gmx.de wrote:
I like to synchronisize a fine 100MHz TCXO with the
10MHz output of the Tbold. The TCXO has a EFC input.
I know this can be done
using a PLL but I do not want to add noise
to the very good noise parameters of the
Replace the 10 mHz oscillator with a divide by ten counter
driven by the 100 mHz signal. Connect the control voltage
from the Tbolt to the 100 mHz oscillator through a low pass
filter and voltage divider that provides the minimum signal
required for discipline. Tboltmon can set gain etc., even
Peter
I would use a PLL like the ADF 4001 because of its low noise floor and
depending of which Tbolt, its phase noise is very good. The advantage is that
you can pick the filter response in such a way that you take advantage of
the individual Osc. parameters.
Bert Kehren
In a message
Hi Tom,
Would it be possible for your application to let the 100 MHz
TCXO free-run? Then you could use one or two of the ADC
channels to sample the TBolt 10 MHz and 1PPS leaving all
the rest of the channels to do real work.
This would then give you all the information you need to apply
phase
but of course: Whatever algorithms you put into your after-the-fact
software correction will have an influence similar to a hardware PLL.
Chris,
I'm curious about this. What are the inherent limits of each
approach? One difference comes to mind -- with a software
post-processing solution you
the TCXO will have to follow the TBolt...
Bob
-Original Message-
From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On
Behalf Of Peter Krengel
Sent: Sunday, September 18, 2011 9:52 PM
To: time-nuts@febo.com
Subject: [time-nuts] Synchronisizing a 100MHz TCXO with Tbold, pse
If the 100 MHz VCTCXO is fundamentally better than the 10 MHz VC?XO
in the Tbolt, then I would go with Chuck's idea to just use it with a
divide by 10 in front, as the main oscillator. You will still have a
good 10 MHz signal available from the divider - just buffer it up
and maybe harmonic
Thank you all for your suggestions.
@ Attila:
I think your suggestion would be a little bit
too complicated. I dont want to write a dissertation :))
My idea was to simply get a low jitter out of the 100MHz
TCXO clocking the FPGA etc..
The fine TCXO I like to use is a AXLE20-12 from AXTAL.
I
@Tom
Unfortunately there are no free ADC channels in the concept
and there is a fixed adjustment (calibration) software routine
which I cannot change. Complete FPGA software is calculated
for a 100MHz clock. There is no possibility to change that.
So I dont have to fix a frequency- but a
If your 100 MHz is already at HCMOS levels, then just use a 74AC
family decade divider or D-FF for the downconversion to 10 MHz - very
straightforward. A small series damping resistor may be needed if the
100 MHz signal has to be carried very far from its source.
Ed
Hi
I suspect you can find a part with significantly better noise floor. Very
good is around -170 dbc / Hz at a 10 KHz offset. There's a lot of room between
that and -135.
Best guess is that you start rolling up at 1 KHz on a part like that. More or
less you would get:
100 Hz -125 dbc / Hz
...@febo.com] On Behalf Of ewkeh...@aol.com
Sent: Monday, September 19, 2011 4:04 AM
To: time-nuts@febo.com
Subject: Re: [time-nuts] Synchronisizing a 100MHz TCXO with Tbold, pse
help
Peter
I would use a PLL like the ADF 4001 because of its low noise floor and
depending of which Tbolt, its phase noise
Peter, it will be difficult to degrade -138dBc/10kHz using a ADF 4001. I
have PLL's using selected $ 1.00 Xtals getting better than -153dBc/10kHz.
.Axtal has units with -174dBC but out of most price ranges but I thought
you were looking at below -150,very doable with ADF 4001.
Bert
In
Bert,
one would typically limit the loop bandwidth to something much lower than
10KHz. Say 100Hz.
This way at 10KHz the ADF4001 would have no effect on phase noise, it would
be almost entirely determined by the TCXO itself.
This is because a 10MHz reference would have to have to be
I know I do it all the time. That's what I spend most my time on.
Bert
In a message dated 9/19/2011 9:08:25 P.M. Eastern Daylight Time,
saidj...@aol.com writes:
Bert,
one would typically limit the loop bandwidth to something much lower than
10KHz. Say 100Hz.
This way at 10KHz the
Hello group,
I like to synchronisize a fine 100MHz TCXO with the
10MHz output of the Tbold. The TCXO has a EFC input.
I know this can be done
using a PLL but I do not want to add noise
to the very good noise parameters of the TCXO
cause the 100MHz signal is to be used to clock
a FPGA which
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