> Hi John,
>
> Congratulations on a good design.
Thanks!
> Why the 78 MHz sample frequency ?
Long story: it's mostly arbitrary, but at least with some ADCs, it's
beneficial to spur performance if the first few dozen harmonics of the ADC
clock rate and the most commonly-used test frequencies don
In message <00bf01cd4d12$f83a41d0$e8aec570$@pop.net>, "John Miles" writes:
Hi John,
Congratulations on a good design.
Why the 78 MHz sample frequency ?
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
p...@freebsd.org | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.
> I was recently reading the manual for the TimePod. It looks quite
> nice. I'm curious as to the price.
I haven't really done a formal "product announcement" on the list or
anywhere else beyond the PTTI show last November, for two reasons. One is
that the PTTI introduction led to a larger-than-