On 22/12/10 15:55, Richard (Rick) Karlquist wrote:
On 12/21/2010 10:11 PM, Bernd Neubig wrote:
Hi Rick,
I have a problem to imagine how you connect the LO and RF port of a
mixer in
series and drive it (the IF port?) with a ... sine wave.
Can you send me a sketch of this arrangement please?
On 12/21/2010 10:11 PM, Bernd Neubig wrote:
Hi Rick,
I have a problem to imagine how you connect the LO and RF port of a mixer in
series and drive it (the IF port?) with a ... sine wave.
Can you send me a sketch of this arrangement please?
Tnx a lot!
Best regards
Bernd Neubig DK1AG
Good
Clarification of my previous posting:
The IF output of the ASK-1 should be pins 2 and 5,
not pins 4 and 5.
The LO input of the ASK-1 is pins 1 and 3.
The RF input of the ASK-1 is pins 4 and 6.
This is not obvious from the data sheet.
You can wire these two ports in series any
way you like,
Hi everyone,
I want to multiply the output from my Efratom 101 (10Mhz) to clock a DDS at
70 Mhz. Has anyone tried this?
Regards,
Steve G0XAR
--
It is vain to do with more that which can be done with less.
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Von: Stephen Farthing squir...@gmail.com
Betreff: [time-nuts] what is the best way to multiply a 10 Mhz signal?
I want to multiply the output from my Efratom 101 (10Mhz) to clock a DDS at
70 Mhz. Has anyone tried this?
I did 5 MHz * 7 = 35 which is about the same, with CMOS gates and
I'm certainly not the expert but can't you place a divide by 7 counter
in the feedback loop of a phase lock loop. There is a fast version
of the 4046 PPL chip that does 100Mhz and a divide by 7 is easy to
rig with TTL.
On Tue, Dec 21, 2010 at 8:35 AM, Stephen Farthing squir...@gmail.com
On 21/12/10 16:35, Stephen Farthing wrote:
Hi everyone,
I want to multiply the output from my Efratom 101 (10Mhz) to clock a DDS at
70 Mhz. Has anyone tried this?
Regards,
Steve G0XAR
What is the application? What will the DDS output frequency be?
Maybe you could use a 70MHz (or whatever
I used to be in the synthesizer business (Zeta Labs)
in a previous life. I learned to ask the customers:
what you are trying to accomplish as the end goal,
before tackling a messy problem like multiplying by
7. Maybe you don't need to multiply by 7, but we
can't tell from your question.
Rick
Interesting. When I used to use and build DDSs back in the early 70's, we
typically used 2.56 times the maximum required frequency for a clock, to get
above Nyquist and allow adequate filtering stop-band rejection. At the time
we could not go much higher due to limitations in device speeds,
This might explain a way to do it
http://physics.eou.edu/courses/phys345/lab14_pll.pdf
What this is doing is simple. It is a 70Mhz voltage controlled oscillator
who's frequency is controlled such that every 7th cycle the phase matches
your 10MHz reference. The example above does divide by 10 or
You may want to check out the 10MHz locked 1GHz clock I did
(using ADF4107 and a 1GHz Crystek CVCO)
http://www.qslnet.de/member/on4iy/1gclock/xlock-1g.html
and associated DDS to generate oddbal frequencies.
http://www.qslnet.de/member/on4iy/9912.html
Includes some PN measurements.
Xtof.
On
Christophe Huygens wrote:
I'll bet your DDS will run at 80 MHz at room temp.
Since this a one-off project, test it to see if it
works to 80 MHz with some design margin. Now you
can cascade 3 doublers. The reconstruction filter
is now stop 50, pass 30 instead of stop 40 pass 30.
That is WAY
It would seem the most jitter free way to do it would be to simply
multiply it up like we used to do. Some reasonably Hi-Q LC circuits
could make a nice flywheel and filter out other signals at the same
time. Once you have it to the desired signal frequency you could
condition it to clock
So, two doublers for 40 MHz and a tripler for 30 and then
mix to get 70? What happens to phase noise when you do that?
Is it as bad as a PLL?
Seems like you ought to get adequate harmonic rejection.
What about six mixers to get 20, 30, 40, 50, 60, and 70 MHz?
Chips and tank coils are cheap, no?
Burt I. Weiner wrote:
It would seem the most jitter free way to do it would be to simply
multiply it up like we used to do. Some reasonably Hi-Q LC circuits
could make a nice flywheel and filter out other signals at the same
time. Once you have it to the desired signal frequency you could
The 6 mixer scheme was my first thought for lowest PN. That way you do not
get 20logN, but you just get the RMS sum of the noise power each time. That
would be 3 dB to get to 20 MHz, and, each time the sum becomes less than 3
dB, as the highest frequency dominates. It would only degrade
Mike Feher wrote:
The 6 mixer scheme was my first thought for lowest PN. That way you do not
get 20logN, but you just get the RMS sum of the noise power each time.
That
No, this is a fallacy because phase noise adds coherently, so that each
doubler adds 6 dB and each tripler adds 9.54 dB.
Am 21.12.2010 21:41, schrieb Rick Karlquist:
No, this is a fallacy because phase noise adds coherently, so that each
doubler adds 6 dB and each tripler adds 9.54 dB. There is no way to get
around 20 LOG N, no matter how you implement the multiplier even if
you add a tripler output to a
It is easier to see in the time domain: 1ps of jitter on a 10 MHz carrier,
when multiplied to 100 MHz is still 1 ps of jitter, just look at the
zero crossings. But at 100 MHz, the jitter percentage of 1 ps to the 360°
is 10 times as bad, because the 360 degrees/s have shrunk.
So, a phase
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