Dear Ajay Bhargav,
In message 1207509190.33599.1311140198703.javamail.r...@ahm.einfochips.com
you wrote:
e.g.
struct armdgpio_gplr_register {
u32 gplr0;
u32 gplr1;
u32 gplr2;
u8 pad[some_value]; //this padding is going to be big
u32 gplr3;
}
Is there any specific
Hi Kim,
I just checked that this error comes when you don't have any of the following
defined in the board file:
CONFIG_USB_UHCI
CONFIG_USB_OHCI
CONFIG_USB_EHCI
CONFIG_USB_OHCI_NEW
...
MPC837xRDB has EHCI host controller. Hence, CONFIG_USB_EHCI and its relevant
support macros should be defined
On Tue, 19 Jul 2011 14:10:48 +0200
David Jander david.jan...@protonic.nl wrote:
On Tue, 19 Jul 2011 13:20:26 +0200
Wolfgang Denk w...@denx.de wrote:
Dear David Jander,
In message 20110719131744.403a81e6@archvile you wrote:
Now I finally know what's wrong and am working on a
Dear Wolfgang,
Is there any specific reason for not using u32 for the padding as
well?
nothing specific. It makes easy to find number of bytes than words.
Why would you need this BASE + OFFSET notation when using a C struct
for the registers? Thi smakes little sense to me.
Well I
I know it's only typos, but could someone ack please.
Helmut
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On 07/06/2011 07:04 PM, helmut.rai...@hale.at wrote:
From: Helmut Raigerhelmut.rai...@hale.at
When writing 0x4000 to the unlockend_blkaddr register, large writes to
a 2k page NAND sometimes fail. The current kernel driver writes 0x
to this register for V2 of the nand controller.
However
Hi Ajay,
On Tue, Jul 19, 2011 at 12:23 PM, Ajay Bhargav
ajay.bhar...@einfochips.com wrote:
- Prafulla Wadaskar prafu...@marvell.com wrote:
You should define all GPIO register in a single struct
And point them with base address offsets
I suggest you to add mvgpio.c instead of
Hi Ajay,
On Tue, Jul 19, 2011 at 6:29 PM, Ajay Bhargav
ajay.bhar...@einfochips.com wrote:
Hi Prafulla,
I checked datasheet and for most GPIOs, AF1 is given as GPIO but for few
its not, so adding a glue logic to check for specific GPIOs wont be a good
idea.
That's the reason i thought its
Hi Lei,
Actually, as uboot target at small size, I tend to don't add too much
logic to it. So there is no need to
check the MAX, if one need to set the gpio, he should notice by
himself, the gpio number he specified
is a valid gpio address in the system.
Yeah so i made this assumption
On Wed, Jul 20, 2011 at 3:14 PM, Ajay Bhargav
ajay.bhar...@einfochips.com wrote:
Hi Lei,
Actually, as uboot target at small size, I tend to don't add too much
logic to it. So there is no need to
check the MAX, if one need to set the gpio, he should notice by
himself, the gpio number he
Hi Lei,
I am not mixing those two concept together, and in our pratice, we
also do as you said,
use mfp to set that pin to GPIO state, and use gpio function to
manupulate the gpio.
So there is no need checking MFP setting for gpio requreset. Directly
set would be ok.
exactly... so here is
On Wed, Jul 20, 2011 at 3:29 PM, Ajay Bhargav
ajay.bhar...@einfochips.com wrote:
Hi Lei,
I am not mixing those two concept together, and in our pratice, we
also do as you said,
use mfp to set that pin to GPIO state, and use gpio function to
manupulate the gpio.
So there is no need checking
On Tue, Jul 19, 2011 at 10:04 PM, Wolfgang Denk w...@denx.de wrote:
[Me]
include/configs/integratorap.h | 3 +
include/configs/integratorap_cm720t.h | 1 +
include/configs/integratorap_cm920t.h | 1 +
include/configs/integratorap_cm926ejs.h | 1 +
Dear Wolfgang,
On Tuesday 19 July 2011 09:21 PM, Daniel Schwierzeck wrote:
From: Aneesh Vane...@ti.com
Signed-off-by: Aneesh Vane...@ti.com
Cc: Albert ARIBAUDalbert.u.b...@aribaud.net
---
Changes since RFC v1:
- none
Changes since RFC v2:
- none
Changes since v3:
- improved comment
- Lei Wen adrian.w...@gmail.com wrote:
I mean why there has to be one request() function call is need?
Is this mandatory for the gpio general framwork as you said?
Best regards,
Lei
If you're enabling GPIO command support (CONFIG_CMD_GPIO), Its necessary. and
yes its a
part of
This defines the requires CONFIG_SYS_* variables to make the
Integrator CP board compile.
Signed-off-by: Linus Walleij linus.wall...@linaro.org
---
This complements the other Integrator patches so that the CP
variants also build cleanly with the new build system.
---
- Take maintainership of the unlisted integratorap, and the
integratorcp boards
- Orphan the versatile maintained by Peter Pearse, as he has retired
from ARM
Cc: Philippe Robin philippe.ro...@arm.com
Signed-off-by: Linus Walleij linus.wall...@linaro.org
---
Changes v1-v2: take care also of
This patch adds support for software I2C for GONI reference target.
It adds support for access to GPIOs by number, not as it is present,
by bank and offset.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Minkyu Kang
Hi Anton,
On Tuesday 19 July 2011 11:44 PM, Anton Staaf wrote:
[snip ..]
There are a number of possible solutions:
1) Modify the invalidate code to first read the partial cache line
and then invalidate and then write back just the valid part of the
line. This suffers
(to : ARM custodians, for action)
(cc: Wolfgang and Scott, for info)
Hi Sandeep,
Le 19/07/2011 17:22, Paulraj, Sandeep a écrit :
Note that u-boot-ti still has a tag, 2009.01-rc2, which should be
removed from the repository, see
Hi Jaehoon Chung,
On 07/19/2011 04:06 AM, Jaehoon Chung wrote:
Hi Michael.
I have some question. there are some mmc_init().
But you are only checked there..
Did you have any special reason?
Regards,
Jaehoon Chung
The purpose of my patch was to enable an if/else to detect whether
Hi David,
Le 20/07/2011 08:29, David Jander a écrit :
On Tue, 19 Jul 2011 14:10:48 +0200
David Janderdavid.jan...@protonic.nl wrote:
On Tue, 19 Jul 2011 13:20:26 +0200
Wolfgang Denkw...@denx.de wrote:
Dear David Jander,
In message20110719131744.403a81e6@archvile you wrote:
Now I
On Wed, 20 Jul 2011 10:56:07 +0200
Albert ARIBAUD albert.u.b...@aribaud.net wrote:
Hi David,
Le 20/07/2011 08:29, David Jander a écrit :
On Tue, 19 Jul 2011 14:10:48 +0200
David Janderdavid.jan...@protonic.nl wrote:
On Tue, 19 Jul 2011 13:20:26 +0200
Wolfgang Denkw...@denx.de
Hi Michael
Thanks for your explanation. :)
Regards,
Jaehoon Chung
Michael Jones wrote:
Hi Jaehoon Chung,
On 07/19/2011 04:06 AM, Jaehoon Chung wrote:
Hi Michael.
I have some question. there are some mmc_init().
But you are only checked there..
Did you have any special reason?
Hi Ajay,
On Wed, Jul 20, 2011 at 2:36 PM, Ajay Bhargav
ajay.bhar...@einfochips.com wrote:
Dear Wolfgang,
Is there any specific reason for not using u32 for the padding as
well?
nothing specific. It makes easy to find number of bytes than words.
Why would you need this BASE + OFFSET
Hi David,
On Wednesday 20 July 2011 02:51 PM, David Jander wrote:
On Wed, 20 Jul 2011 10:56:07 +0200
[snip ..]
Any ideas?
Yes, one: I had issues with the Marvell Ethernet adapter, which has DMA
as well, not because of cache (it was not active at the time) but
because of instruction
Hi Lei,
I think we make thing complicated here. For GPIO driver, the only
structure we need to
define is the GPIO register itself, like GPIO_PLR, GPIO_PDR, etc...
I got your point, but lemme show you where the problem is..
GPIO_PLR00x
GPIO_PLR10x0004
GPIO_PLR20x0008
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap4/board.c|3 +++
arch/arm/include/asm/arch-omap4/omap4.h |1 +
arch/arm/include/asm/armv7.h|1 +
3 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/board.c
OMAP4460 is the latest addition to the OMAP4 family.
OMAP4460 has dual core Cortex-A9 CPUs that can be clocked upto
1.5 GHz
The memory architecture has been improved to provide better
performance and there several other minor improvements in various
modules.
This series depends on the OMAP4 spl
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap4/emif.c| 39 ++--
arch/arm/include/asm/arch-omap4/emif.h | 10 ++-
2 files changed, 30 insertions(+), 19 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/emif.c
Signed-off-by: Aneesh V ane...@ti.com
---
V2:
* Added a new file that was accidentally missing in v1
---
arch/arm/cpu/armv7/omap-common/Makefile|1 +
arch/arm/cpu/armv7/{omap3 = omap-common}/gpio.c | 41
arch/arm/cpu/armv7/omap3/Makefile |
TPS62361 is the new power supply used in OMAP4460 that
supplies vdd_mpu.
VCORE1 from Phoenix supplies vdd_core and VCORE2 supplies
vdd_iva. VCORE3 is not used in OMAP4460.
Signed-off-by: Aneesh V ane...@ti.com
---
arch/arm/cpu/armv7/omap4/board.c|4 ++
---
arch/arm/cpu/armv7/omap4/clocks.c| 61 ++---
arch/arm/include/asm/arch-omap4/clocks.h | 12 +-
2 files changed, 65 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c
b/arch/arm/cpu/armv7/omap4/clocks.c
index 0db9d18..eda960c
On 07/19/2011 08:45 PM, Wolfgang Denk wrote:
Dear Valentin Longchamp,
In message 4e25a2d0.1090...@keymile.com you wrote:
With the memory test, that takes place before the relocation, it is extremly
slow (even if I reduce the size of the memory tested to a very small
portion).
Is it
Hi Aneesh,
On Wed, 20 Jul 2011 15:59:42 +0530
Aneesh V ane...@ti.com wrote:
On Wednesday 20 July 2011 02:51 PM, David Jander wrote:
On Wed, 20 Jul 2011 10:56:07 +0200
[snip ..]
Any ideas?
Yes, one: I had issues with the Marvell Ethernet adapter, which has DMA
as well, not because
Dear Mehresh Ramneek-B31383,
In message
16867771548d2f469f1a8f817f38278820a...@039-sn1mpn1-003.039d.mgd.msft.net you
wrote:
I just checked that this error comes when you don't have any of the following
defined in the board file:
CONFIG_USB_UHCI
CONFIG_USB_OHCI
CONFIG_USB_EHCI
Hi David,
On Wednesday 20 July 2011 05:01 PM, David Jander wrote:
Hi Aneesh,
On Wed, 20 Jul 2011 15:59:42 +0530
Aneesh Vane...@ti.com wrote:
On Wednesday 20 July 2011 02:51 PM, David Jander wrote:
On Wed, 20 Jul 2011 10:56:07 +0200
[snip ..]
Any ideas?
Yes, one: I had issues with
Dear Ajay Bhargav,
In message 794341286.33968.1311143785027.javamail.r...@ahm.einfochips.com you
wrote:
Is there any specific reason for not using u32 for the padding as
well?
nothing specific. It makes easy to find number of bytes than words.
If there is no specific reason (which I
Dear Linus Walleij,
In message CACRpkdYR5+bMBpdF0F5NmQZZGnRS3=nuyq1r_fcezoj2fp2...@mail.gmail.com
you wrote:
Would it not make
sense to omit these file alltogether then, and let the entries in
boards.cfg point to the generic files integratorap.h resp.
integratorcp.h instead?
This row
Hi Ajay,
On Wed, Jul 20, 2011 at 6:43 PM, Ajay Bhargav
ajay.bhar...@einfochips.com wrote:
Hi Lei,
I think we make thing complicated here. For GPIO driver, the only
structure we need to
define is the GPIO register itself, like GPIO_PLR, GPIO_PDR, etc...
I got your point, but lemme show you
Dear Ajay Bhargav,
In message 1499501074.35394.1311158638174.javamail.r...@ahm.einfochips.com
you wrote:
Hi Lei,
I think we make thing complicated here. For GPIO driver, the only
structure we need to
define is the GPIO register itself, like GPIO_PLR, GPIO_PDR, etc...
I got your
Dear Valentin Longchamp,
In message 4e26b523.3070...@keymile.com you wrote:
I have done a little bit of profiling this morning, and the main culprit is
the
call to getenv_f in post_get_flags for the four environment variables:
post_poweron, post_normal, post_slowtest post_critical
This
- Lei Wen adrian.w...@gmail.com wrote:
Hi Ajay,
On Wed, Jul 20, 2011 at 6:43 PM, Ajay Bhargav
ajay.bhar...@einfochips.com wrote:
Hi Lei,
I think we make thing complicated here. For GPIO driver, the only
structure we need to
define is the GPIO register itself, like GPIO_PLR,
On 07/20/2011 02:20 PM, Wolfgang Denk wrote:
Dear Valentin Longchamp,
In message 4e26b523.3070...@keymile.com you wrote:
I have done a little bit of profiling this morning, and the main culprit is
the
call to getenv_f in post_get_flags for the four environment variables:
post_poweron,
Le 19/07/2011 22:11, J. William Campbell a écrit :
If this is true, then it means that the cache is of type write-back (as
opposed to write-thru). From a (very brief) look at the arm7 manuals, it
appears that both types of cache may be present in the cpu. Do you know
how this operates?
Dear Valentin Longchamp,
In message 4e26cad9.3090...@keymile.com you wrote:
We are currently planning to move away from I2C EEPROM for environment (for
future hardware), but what would you advise me to do for our current hardware
where the environment is in this EEPROM ?
This depends on the
Hi Wolfgang,
I agree with you that there may be some boards that have USB (on soc) but do
not use it.
But in that case, they should not define CONFIG_HAS_FSL_DR_USB in their board
file.
usb.h file has a logic that if this file is included, and the USB protocol is
not defined then it throws
The vector is not correctly setup in armv7 except for OMAP3.
Correcting this.
Signed-off-by: Aneesh V ane...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
arch/arm/cpu/armv7/start.S | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git
Configuring DCSRCR to define the DCSR space to be 1G instead
of the default 4M. DCSRCR only allows selection of either 4M
or 1G.
Most DCSR registers are within 4M but the Nexus trace buffer
is located at offset 16M within the DCSR.
Configuring the LAW to be 32M to allow access to the Nexus
trace
Dear Jeroen.
The patch file that i uploaded before is for u-boot tools for snow leopard
10.6.8.
I think http://patchwork.ozlabs.org/patch/105538/ will resolve for snow leopard
environment.
Regards
sungyeon.
On Jul 19, 2011, at 11:38 PM, Jeroen wrote:
Hello Sungyeon / Mike,
I am not sure
On Jul 20, 2011, at 9:47 AM, Stephen George wrote:
Configuring DCSRCR to define the DCSR space to be 1G instead
of the default 4M. DCSRCR only allows selection of either 4M
or 1G.
Most DCSR registers are within 4M but the Nexus trace buffer
is located at offset 16M within the DCSR.
Hi,
The determination to explore new ways of doing things, especially by reading
important life changing books, easily brings about a sustainable progressive
and successful life --G.P.I.
Among these great highly motivational and inspirational books are;-
WAYS OF ATTAINING BUSINESS
On 7/20/2011 7:35 AM, Albert ARIBAUD wrote:
Le 20/07/2011 16:01, J. William Campbell a écrit :
On 7/20/2011 6:02 AM, Albert ARIBAUD wrote:
Le 19/07/2011 22:11, J. William Campbell a écrit :
If this is true, then it means that the cache is of type write-back
(as
opposed to write-thru). From
OMAP4460 is the latest addition to the OMAP4 family.
OMAP4460 has dual core Cortex-A9 CPUs that can be clocked upto
1.5 GHz
The memory architecture has been improved to provide better
performance and there several other minor improvements in various
modules.
This series depends on
Nokia has Approved you of GBP £750,000.00. For claim contact: Mr. David Bassett
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Am Montag, den 18.07.2011, 13:49 -0400 schrieb Mike Frysinger:
On Sat, Jul 16, 2011 at 13:32, Andreas Pretzsch wrote:
The sspi command writes the given data out on SPI and prints the data it
reads to the console. For write-only slaves (i.e. a SPI-connected latch
used as output expander),
On Wed, 20 Jul 2011 08:55:00 +0200
Helmut Raiger helmut.rai...@hale.at wrote:
On 07/06/2011 07:04 PM, helmut.rai...@hale.at wrote:
From: Helmut Raigerhelmut.rai...@hale.at
When writing 0x4000 to the unlockend_blkaddr register, large writes to
a 2k page NAND sometimes fail. The current
On Wed, 20 Jul 2011 08:53:48 +0200
Helmut Raiger helmut.rai...@hale.at wrote:
I know it's only typos, but could someone ack please.
Helmut
I'll apply it soon, sorry for the delay.
-Scott
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Am Donnerstag, den 07.07.2011, 12:15 +0200 schrieb Detlev Zundel:
Hi Wolfgang,
Dear Detlev Zundel,
In message m2aacrlsen@ohwell.denx.de you wrote:
I'd say clear/set/toggle are changeable, don't see any legit
return-value-usage here. For 100% backward compatibility, one could
Changes for v2:
- updated mkconfig patch to make minimal changes and changed commit
message, since it now relies on GNU and BSD extensions.
Jeroen Hofstee (3):
include/compiler.h: typedef ulong for FreeBSD
rules.mk: replace GNU specific \w with POSIX equivalant
mkconfig: also create
Changes for v2:
- updated mkconfig patch to make minimal changes and changed commit
message, since it now relies on GNU and BSD extensions.
Jeroen Hofstee (3):
include/compiler.h: typedef ulong for FreeBSD
rules.mk: replace GNU specific \w with POSIX equivalant
mkconfig: also create
Parsing of boards.cfg fails on FreeBSD with the error:
sed: 1: /=/ {s/=/\t/;q } ; { s/ ...: extra characters at the end
of q command
BSD sed expects commands to be on seperate 'lines', hence it expects
an additional ; before the closing brackets.
BSD sed does not support \t, replaced by literal
Hi,
I would like to know if there's any methodology or requirement documentation
available for the POST Hardware Diagnose Commands from U-Boot, for
microprocessor MPC8378?
Thanks,
Ferdinand Vega
Systems Engineer II (ESEA MESA)
Honeywell Aerospace
San Antonio Industrial Park
Road
Dear Paulraj, Sandeep,
In message be04c0a3bec7354a8bce3db869f4d493023...@dfle35.ent.ti.com you wrote:
This series depends on the OMAP4 spl series [1] and the SPL framework
series [2]
[1] http://marc.info/?l=u-bootm=131082102506002w=2
[2] http://marc.info/?l=u-bootm=131056990001719w=2
Dear Wolfgang,
On 18.07.2011 21:41, Andreas Bießmann wrote:
The series ARM: remove broken boards deletes the last few boards which used
the obsolete arm920t/at91rm9200 arch code.
This series completes it and removes the now obsolete at91rm9200 arch code
completely. Additionally ther are some
Dear Vega, Ferdinand (ESEA MESA),
In message
7c815335a6382547a0240c3fa5f33bc9ac5...@de08ev804.global.ds.honeywell.com you
wrote:
I would like to know if there's any methodology or requirement documentation
available for the POST Hardware Diagnose Commands from U-Boot, for
microprocessor
Dear Reinhard Meyer,
In message 4e273239.10...@emk-elektronik.de you wrote:
The series ARM: remove broken boards deletes the last few boards which
used
the obsolete arm920t/at91rm9200 arch code.
This series completes it and removes the now obsolete at91rm9200 arch code
completely.
On Wed, Jul 20, 2011 at 14:38, Jeroen Hofstee wrote:
Parsing of boards.cfg fails on FreeBSD with the error:
sed: 1: /=/ {s/=/\t/;q } ; { s/ ...: extra characters at the end
of q command
BSD sed expects commands to be on seperate 'lines', hence it expects
an additional ; before the closing
Dear Paulraj, Sandeep,
In message be04c0a3bec7354a8bce3db869f4d493023...@dfle35.ent.ti.com you
wrote:
This series depends on the OMAP4 spl series [1] and the SPL framework
series [2]
[1] http://marc.info/?l=u-bootm=131082102506002w=2
[2]
OMAP4460 is the latest addition to the OMAP4 family.
OMAP4460 has dual core Cortex-A9 CPUs that can be clocked upto
1.5 GHz
The memory architecture has been improved to provide better
performance and there several other minor improvements in various
modules.
This series depends on
This is the finalized version for the SPL framework:
http://marc.info/?l=u-bootm=131056990001719w=2
Changes since RFC v1:
- added documentation for SPL framework
- enable garbage collect of unused sections for SPL unconditionally
Changes since RFC v2:
- renamed
Aneesh V (11):
omap4: utility function to identify the context of hw init
omap4: cleanup pin mux data
omap4: add OMAP4430 revision check
omap4: add clock support
omap4: add sdram init support
omap4: calculate EMIF register values
omap4: automatic sdram detection
armv7:
This code has been changed to read the CPU speed information from the
CPR registers rather than the bootstrap registers. This is useful when
changing the clock speed to something other than the default on boot.
Signed-off-by: Mike Williams m...@mikebwilliams.com
---
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Saya anak tunggal dari orang tua saya.
Apa yang terjadi sekarang? Orang tua saya telah meninggal karena
kecelakaan mobil. Ayah saya ternyata telah menikah dua istri. Ibu dari
Indonesia. Kami bahagia hidup bersama di Pulau Sumatra sebelum gempa
bumi. Setelah gempa, kami memutuskan untuk
Dear Mike Williams,
In message 1311197713-13010-1-git-send-email-m...@mikebwilliams.com you wrote:
This code has been changed to read the CPU speed information from the
CPR registers rather than the bootstrap registers. This is useful when
changing the clock speed to something other than the
On Wednesday, July 20, 2011 13:04:47 Andreas Pretzsch wrote:
I also thought about passing NULL for the read buffer, but a quick
browse through the code showed that most, but not all SPI drivers are
prepared for that. And as there is already a static rx buffer in the spi
command code, I
Hello Dear Andy:
I found in env_mmc.c, mmc_get_env_addr(...)only do *env_addr =
CONFIG_ENV_OFFSET.If CONFIG_ENV_OFFSET is defined in partition space,the raw
data may cover the env.IF CONFIG_ENV_OFFSET = 0,will it damage MBR?Should it do
some protection methods?
Thank you very much
We have a few minor differences between P2041 P2040 that we need to
handle or we run into issues. We also rename a few things to make the
P2041 the superset device.
P2040 is a reduced P2041 (missing 10g/XAUI and L2-cache).
- k
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P2041 is the superset part that covers both P2040 P2041. The only
difference between the two devices is that P2041 supports 10g/XAUI and
has an L2 cache.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/cpu/mpc85xx/Makefile |6 +-
We add XAUI_FM1 into the SERDES tables for P2041[e] devices. However
for the P2040[e] devices that dont support XAUI we handle this at
runtime via SVR checks. If we are on a P2040[e] device the SERDES
functions will behave as follows:
is_serdes_prtcl_valid() will always report invalid if prtcl
This patch adds generic GPIO driver framework support for Marvell SoCs.
To enable GPIO driver define CONFIG_MV_GPIO and for GPIO commands
define CONFIG_CMD_GPIO in your board configuration file.
Signed-off-by: Ajay Bhargav ajay.bhar...@einfochips.com
---
drivers/gpio/Makefile |1 +
This patch adds support for generic GPIO driver framework for Marvell
SoC Armada100.
Signed-off-by: Ajay Bhargav ajay.bhar...@einfochips.com
---
arch/arm/include/asm/arch-armada100/gpio.h | 71
1 files changed, 71 insertions(+), 0 deletions(-)
create mode 100644
Hi Sandeep,
On Thu, Jul 21, 2011 at 3:01 AM, Paulraj, Sandeep s-paul...@ti.com wrote:
Aneesh V (11):
omap4: utility function to identify the context of hw init
omap4: cleanup pin mux data
omap4: add OMAP4430 revision check
omap4: add clock support
omap4: add sdram init support
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