hi Albert,
On Mon Jul 08, 2013 at 09:55:51PM +0200, Albert ARIBAUD wrote:
snip
Invalidating the cache in addition to flushing it would not prevent
further writes from dirtying the cache lines if they happen before
the cache is disabled.
I have a doubt on this. The arm926ejs uses a
I have tried to implement an AUART driver for i.MX28.
However for it to work I must print 1 character to the
debug UART via the serial_pl01x driver. If I do this
the AUART will start working. If I don't nothing will
be printed to the AUART. Anybody can see any obvious errors?
Signed-off-by:
There are differnce with clock calcuation by cpu variations.
This patch will fix it according to user manual.
Signed-off-by: Minkyu Kang mk7.k...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes for v2:
- remove hard-coded constants.
In chapter 'Advisory 2.1 USB Host Clock Drift Causes USB Spec Non-compliance in
Certain Configurations' of the TI Errata it is recommended to use certain
div/mult values for the DPLL5 clock setup.
So far u-boot used the old 34xx values, so I added the errata recommended
values specificly for
On Tue, Jul 9, 2013 at 1:23 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 07/08/2013 01:50 PM, Marek Vasut wrote:
Dear Stephen Warren,
[...]
I had already tested the commit in your tree right before the reverts
(a36466c50b1b3614c3cfdae194227f7dd8e2c592); that's how I noticed that
the
Looks fine to me.
Acked-by: Rajeshwari Shinderajeshwar...@samsung.com
On Tue, Jul 9, 2013 at 1:07 PM, Minkyu Kang mk7.k...@samsung.com wrote:
There are differnce with clock calcuation by cpu variations.
This patch will fix it according to user manual.
Signed-off-by: Minkyu Kang
Hi,
It seems that all three ARM errata workarounds done in omap3 board-init
(#454179 #430973 #621766) are solved/not longer needed e.g. in the
AM/DM37xx chips. Other people have noticed this:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx
When still applying them (especcially
Dear Amar,
On 07/07/13 14:43, Minkyu Kang wrote:
Dear Amar,
On 6 July 2013 04:12, Albert ARIBAUD albert.u.b...@aribaud.net
mailto:albert.u.b...@aribaud.net wrote:
Hi Minkyu,
This breaks build of VCMA9:
s3c24x0_i2c.c: In function 'board_i2c_init':
Hi Sughosh,
On Tue, 9 Jul 2013 11:41:34 +0530, Sughosh Ganu
urwithsugh...@gmail.com wrote:
hi Albert,
On Mon Jul 08, 2013 at 09:55:51PM +0200, Albert ARIBAUD wrote:
snip
Invalidating the cache in addition to flushing it would not prevent
further writes from dirtying the cache
On Mon, 08 Jul 2013 12:15:18 -0400, Tom Rini wrote:
Add a README for the family of boards the am335x_evm covers, and
include instructions on preparing and using falcon mode, for various
media.
Signed-off-by: Tom Rini tr...@ti.com
---
board/ti/am335x/README | 113
Hi Pavel,
On Tue, 9 Jul 2013 01:22:01 +0200, Pavel Machek pa...@denx.de wrote:
Hi!
From: Dinh Nguyen dingu...@altera.com
Because the SOCFPGA platform will include support for Cyclone V and
Arria V FPGA parts, renaming socfpga_cyclone5 folder to socfpga to
be more
Hi Andreas,
On Tue, 09 Jul 2013 10:08:10 +0200, Andreas Naumann d...@andin.de
wrote:
Hi,
It seems that all three ARM errata workarounds done in omap3 board-init
(#454179 #430973 #621766) are solved/not longer needed e.g. in the
AM/DM37xx chips. Other people have noticed this:
Excuse me, this patch has not been merged? Thanks.
-Original Message-
From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Tom Rini
Sent: Friday, June 28, 2013 5:57 AM
To: Wood Scott-B07421
Cc: u-boot@lists.denx.de; Wood Scott-B07421; aflem...@gmail.com; Zhang
Ying-B40530
Subject: Re:
Hi Dan,
On 07/08/2013 11:59 PM, Dan Murphy wrote:
Add code to configure the USB EHCI host controller.
This enumerates an ethernet controller through USB3 using
the HSIC lines.
Signed-off-by: Dan Murphy dmur...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c | 15 +++
On 07/08/2013 11:59 PM, Dan Murphy wrote:
Need to check why gpio toggling in ehci-omap is not
working and works only from ehci-hcd.
do you mean HSIC detection is not working?
GPIO toggling has to work from anywhere.
Signed-off-by: Dan Murphy dmur...@ti.com
---
Hi Andreas,
On 07/09/2013 11:10 AM, Albert ARIBAUD wrote:
Hi Andreas,
On Tue, 09 Jul 2013 10:08:10 +0200, Andreas Naumann d...@andin.de
wrote:
Hi,
It seems that all three ARM errata workarounds done in omap3 board-init
(#454179 #430973 #621766) are solved/not longer needed e.g. in the
Hi Andreas,
On Tue, 09 Jul 2013 12:42:27 +0200, Andreas Bießmann
andreas.de...@googlemail.com wrote:
Another solution could be to read the
silicon revision and enable erratum workarounds on that information. It
would be a step towards single binary.
Seconded.
Best regards
Andreas
Hi
I am working on one board with an arm11 based cpu, NOR flash and DDR2 SDRAM.
When I compile u-boot source code, I get u-boot.bin image generated.
This image has primary(second stage) and secondary(third stage) bootloader
combined.
I have following queries:
1) The question that still eats me
From: Ying Zhang b40...@freescale.com
1. The symbol CONFIG_SPL_NAND_MINIMAL is unused, so deleted it.
2. Some functions were unused in the minimal SPL, but it is useful
in the common SPL. So, enabled some functionality for common SPL.
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change
From: Ying Zhang b40...@freescale.com
This patch introduces SPL to enable a loader stub that being loaded by
the code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.
The SPL's size is sizeable, the maximum size must not exceed the size
From: Ying Zhang b40...@freescale.com
Due to the nand SPL on some board(e.g. P1022DS)has a size limit, it can
not be more than 4K. So, the SPL cannot initialize the DDR with the SPD
code. This patch introduces TPL to enable a loader stub that is loaded
by the code from the SPL. It initializes the
From: Ying Zhang b40...@freescale.com
This patch introduces SPL to enable a loader stub that being loaded by
the code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.
The SPL's size is sizeable, the maximum size must not exceed the size
From: Ying Zhang b40...@freescale.com
Enable p1022ds to start from eSPI with SPL.
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change from v6:
- No longer changes the header file included by the file
- board/freescale/p1022ds/spl.c
Change from v5:
- Split from powerpc/p1022ds: boot from
From: Ying Zhang b40...@freescale.com
Enable p1022ds to start from eSDHC with SPL.
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change from v6:
- Split from the patch powerpc/p1022ds: boot from SD Card with SPL,
- this patch only enables p1022ds to boot from SD Card with SPL.
Change from
From: Ying Zhang b40...@freescale.com
TPL is introduced in the patch NAND: TPL : introduce the TPL
based on the SPL, here enable TPL for p1022ds nand boot.
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change from v6:
- Delete the file board/freescale/p1022ds/tpl.c.
- Reuse the file
Hi Rajdeep,
On Tue, 9 Jul 2013 16:12:14 +0530, Rajdeep Vaghasia
rajdeep.vagha...@gmail.com wrote:
Hi
I am working on one board with an arm11 based cpu, NOR flash and DDR2 SDRAM.
When I compile u-boot source code, I get u-boot.bin image generated.
This image has primary(second stage) and
This patch resolves the below mentiond compilation error of i2c driver
for non-FDT case.
Compilation error:
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error: 'CONFIG_MAX_I2C_NUM' undeclared (first use
in this function) s3c24x0_i2c.c:544:18: note: each undeclared
Hi,
This reverts commit 0bf796f7ae22086f0504f3297e9fb4e96aa04161.
This commit causes breakage of the EHCI, where on Tegra it is not
possible to run usb reset twice as it results in the board hang.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Vivek Gautam gautamvivek1...@gmail.com
Cc:
Dear amar_g
On 09/07/13 21:44, amar_g wrote:
Please add prefix at title.
This patch resolves the below mentiond compilation error of i2c driver
typo. - mentiond
for non-FDT case.
Compilation error:
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error:
Dear Minkyu,
Please find my responses below.
Thanks Regards
Amarendra Reddy
On 9 July 2013 18:50, Minkyu Kang mk7.k...@samsung.com wrote:
Dear amar_g
On 09/07/13 21:44, amar_g wrote:
Please add prefix at title.
OK shall add aprefix 'EXYNOS' at title in the next patch.
This patch
This patch resolves the below mentiond compilation error of i2c driver
for non-FDT case
Compilation error:
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error: 'CONFIG_MAX_I2C_NUM' undeclared (first use
in this function) s3c24x0_i2c.c:544:18: note: each undeclared
identifier
Hi, I am trying to boot with a multi image file that was generated with
mkimage. The uboot decompress the file and find the kernel, but is not find
the filesystem. How can I fix the ramdisk address in ram to call bootm in
right way?
- command line used to mkimage: mkimage -A arm -T multi -C
Hi amar_g,
On Tue, 09 Jul 2013 19:35:40 +0530, amar_g amarendra...@samsung.com
wrote:
This patch resolves the below mentiond compilation error of i2c driver
for non-FDT case
Compilation error:
---8---
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error:
Hi,
It seems that all three ARM errata workarounds done in omap3 board-init
(#454179 #430973 #621766) are solved/not longer needed e.g. in the
AM/DM37xx chips. Other people have noticed this:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx
When still applying them (especcially
Hi, I am trying to boot with a multi image file that was generated with
mkimage. The uboot decompress the file and find the kernel, but is not find
the filesystem. How can I fix the ramdisk address in ram to call bootm in
right way?
- command line used to mkimage: mkimage -A arm -T multi -C
Hi Andreas,
On 07/09/2013 05:01 PM, Andreas Naumann wrote:
It seems that all three ARM errata workarounds done in omap3 board-init
(#454179 #430973 #621766) are solved/not longer needed e.g. in the
AM/DM37xx chips. Other people have noticed this:
Hello,
It seems that all three ARM errata workarounds done in omap3 board-init
(#454179 #430973 #621766) are solved/not longer needed e.g. in the
AM/DM37xx chips. Other people have noticed this:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx
When still applying them
Nishanth
Thanks for the feedback
On 07/08/2013 04:27 PM, Nishanth Menon wrote:
On 07/08/2013 03:53 PM, Dan Murphy wrote:
Add the tca642x gpio expander driver
http://www.ti.com/sitesearch/docs/universalsearch.tsp?searchTerm=tca642linkId=1
I think there are just TCA6424 ?
giving a link to the
On 07/08/2013 04:19 PM, Nishanth Menon wrote:
$subject
Don't know where it went it was in my patch set I submitted.
omap5: uevm
On 07/08/2013 03:54 PM, Dan Murphy wrote:
Configure the tca6424 gpio expander
This allows use of the debug and tri color LEDs.
As well as HDMI PEO signal.
we use
On 07/09/2013 11:17 AM, Dan Murphy wrote:
On 07/08/2013 04:27 PM, Nishanth Menon wrote:
On 07/08/2013 03:53 PM, Dan Murphy wrote:
[...]
+/* tca642x register address definitions */
+struct tca642x_bank_info tca642x_banks[] = {
+{0x00, 0x04, 0x08, 0x0c},
+{0x01, 0x05, 0x09, 0x0d},
+
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at 9:13 AM, Tom Rini tr...@ti.com wrote:
On Thu, Jul 04, 2013 at 01:26:11PM -0700, Simon Glass wrote:
In the recent bootm refactor, the PREP stage
Configure the tca6424 gpio expander
This allows use of the debug and tri color LEDs.
Signed-off-by: Dan Murphy dmur...@ti.com
---
v2 - Updated per comments- http://patchwork.ozlabs.org/patch/257603
board/ti/omap5_uevm/evm.c | 21 +
board/ti/omap5_uevm/mux_data.h |
Add the tca642x gpio expander driver
Datasheet:
http://www.ti.com/product/tca6424a
Signed-off-by: Dan Murphy dmur...@ti.com
---
v2 - Updated per comments- http://patchwork.ozlabs.org/patch/257602/
drivers/gpio/Makefile |1 +
drivers/gpio/tca642x.c | 321
On Tue, Jul 09, 2013 at 12:00:00PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at 9:13
On Tue, Jul 9, 2013 at 2:00 PM, Simon Glass s...@chromium.org wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at 9:13 AM, Tom Rini tr...@ti.com wrote:
On Thu, Jul 04, 2013 at
The BeagleBone Black differs from the other AM335x boards in a few
significant ways, so it makes sense to create a custom configuration
for it. In particular, it uses eMMC instead of NAND flash.
We can use the eMMC boot partition to store the environment, since it
isn't used for anything else.
Give the user the ability to disable NAND support by defining
CONFIG_NO_NAND. This will allow custom hardware to easily support
this configuration.
Signed-off-by: Justin Waters justin.wat...@timesys.com
---
include/configs/am335x_evm.h | 55 --
1 file
The BeagleBone Black can boot from either the MMC card
or eMMC chip on board. We should try both interfaces.
This modification also allows a graceful fallback if
a device exists but boot images are not present on it.
Signed-off-by: Justin Waters justin.wat...@timesys.com
---
There are a number of differences between the BeagleBone Black
and other AM335x boards that require some modification of the
default AM335x EVM configuration. In particular, it lacks NAND
flash, has multiple MMC interfaces, and can store its environment
in an unused eMMC partition.
The following
Many modern U-Boot ports enable command line editing and
a history buffer. The am335x_evm configuration is fairly
comprehensive as it is, so a few extra kb should not be
noticable, and it adds a very convenient feature.
Signed-off-by: Justin Waters justin.wat...@timesys.com
---
This rule catches images such as MLO.byteswap
Signed-off-by: Justin Waters justin.wat...@timesys.com
---
.gitignore |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.gitignore b/.gitignore
index 771b860..d1282e7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -24,7 +24,7 @@
#
Like 'bootm', 'bootz' needs to consume 'bootz' so that the rest of the
state functions will work.
Signed-off-by: Tom Rini tr...@ti.com
---
common/cmd_bootm.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index
As a zImage does not have a U-Boot header, we cannot really do what
BOOTM_STATE_FINDOTHER does, exactly. Break the ramdisk/fdt portions of
bootm_find_other into bootm_find_ramdisk/fdt which can be called in both
cases.
Signed-off-by: Tom Rini tr...@ti.com
---
common/cmd_bootm.c | 56
On Tue, Jul 09, 2013 at 03:00:06PM -0400, Justin Waters wrote:
Give the user the ability to disable NAND support by defining
CONFIG_NO_NAND. This will allow custom hardware to easily support
this configuration.
Signed-off-by: Justin Waters justin.wat...@timesys.com
Just make boards.cfg set
Hello Stefano,
The twister always had a fragile usb support in u-boot
in the past. Since some floating patches mentioned
alternating success after usb hub resets, I had a look
if these patches fixed the twister as well, they don't.
Some fiddling around [1] makes the usb work however,
by not
On Tue, Jul 09, 2013 at 03:00:05PM -0400, Justin Waters wrote:
There are a number of differences between the BeagleBone Black
and other AM335x boards that require some modification of the
default AM335x EVM configuration. In particular, it lacks NAND
flash, has multiple MMC interfaces, and
Tom,
On Tue, 2013-07-09 at 15:44 -0400, Tom Rini wrote:
On Tue, Jul 09, 2013 at 03:00:06PM -0400, Justin Waters wrote:
Give the user the ability to disable NAND support by defining
CONFIG_NO_NAND. This will allow custom hardware to easily support
this configuration.
Signed-off-by:
Hi Tom,
On Tue, Jul 9, 2013 at 12:05 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 12:00:00PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013
Tom,
On Tue, 2013-07-09 at 15:47 -0400, Tom Rini wrote:
On Tue, Jul 09, 2013 at 03:00:05PM -0400, Justin Waters wrote:
There are a number of differences between the BeagleBone Black
and other AM335x boards that require some modification of the
default AM335x EVM configuration. In
On Tue, Jul 09, 2013 at 01:04:58PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 12:05 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 12:00:00PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul
On Tue, Jul 9, 2013 at 4:19 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 01:04:58PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 12:05 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 12:00:00PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013
Important, but I really want to see real-world booting in a case or two.
Unfortunately I don't have any ARM boards that work out of the box with
NetBSD.
There 'seems' to be a pre-built freebsd arm port...
https://wiki.freebsd.org/FreeBSD/arm/BeagleBone
NM.. they are using the 'bootelf'
Hi Tom,
On Tue, Jul 9, 2013 at 2:19 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 01:04:58PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 12:05 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 12:00:00PM -0700, Simon Glass wrote:
Hi Tom,
On
Hi Andreas,
I have tried to implement an AUART driver for i.MX28.
However for it to work I must print 1 character to the
debug UART via the serial_pl01x driver. If I do this
the AUART will start working. If I don't nothing will
be printed to the AUART. Anybody can see any obvious errors?
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.
While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.
So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.
The core specific part of the work is done in the assembly routine
in
armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/include/asm/armv7.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
(for GIT URL and Changelog see below)
ARM CPUs with the virtualization extension have a new mode called
HYP mode, which allows hypervisors to safely control and monitor
guests. The current hypervisor implementations (KVM and Xen)
require the kernel to be entered in that HYP mode.
This patch
To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
respective configuration variable.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
include/configs/vexpress_ca15_tc2.h | 2 ++
1 file changed, 2
The flush_dcache_range() on arm926 did not work as expected on i.MX28.
This can be observed during the operation of the FEC ethernet driver
where the driver did occasionally fail with timeout trying to transmit
a frame. The FEC ethernet driver uses DMA for transmitting the frame in
the following
Allocate the framebuffer aligned so it can be flushed
and the flush_dcache_range() function won't complain.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Anatolij Gustschin ag...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic
The usb_lowlevel_init() call already fills and passes back struct
ehci_ctrl , which readily contains correctly determined address of
the port register block address computed from values from controller
configuration registers. Leverage this and make use of this value
as this makes the code mode
Clean up the code that checks the validity of a USB gadget driver
in usb_gadget_register_driver(). Moreover, limit the speed of the
driver to either FULL or HIGH, this is more precise and once we
have xHCI support, also more correct.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam
This series cleans up the mv_udc / chipidea UDC driver and adds support
for handling caches.
Marek Vasut (17):
usb: mv_udc: Unbreak the mv_udc driver
usb: mv_udc: Clean up mv_udc.h
usb: mv_udc: Move endpoint array into driver data
usb: mv_udc: Clean up the EP initialization
usb: ehci:
The mv_udc driver is broken for a while and doesn't even compile.
This patch fixes the issues and gets the driver into working state
again. This driver was tested on Freescale i.MX233/i.MX28 .
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen
The QH_MAXNUM is used in absolutelly incorrect manner and is not
even needed. Remove it and correctly replace it's occurance with
2 * NUM_ENDPOINTS .
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador
The endpoint QH list has to be aligned to 10-bit boundary. We also have
to make sure the list is aligned on a cacheline boundary. Make sure it
is. Furthermore, check if the memory allocation for the QH list didn't
fail. Moveover, improve the comment about the QH list structure.
Finally, the qTD
Do a coding-style cleanup of this file and throw away useless
defined values. These values were likely a result of a copy-paste
job.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Move the constant values that are programmed into mv_ep.ep into
separate static const structure so they can be memcpy()'d when
the initialization happens.
Moveover, we only every init NUM_ENDPOINTS, not 2 * NUM_ENDPOINTS,
so fix this bug as well.
Signed-off-by: Marek Vasut ma...@denx.de
Cc:
The endpoints are operated on a per-controller basis, move the
endpoint array into controller's private data. Also shuffle the
struct mv_ep structure definition just above the definition of
the struct mv_drv so they're well grouped together.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio
Implement functions to flush/invalidate dcache over QH and qTDs
and make use of them where appropriate. Also use them to replace
the old incorrect cache management attempt. This is the first step
towards making this driver work with data cache enabled.
Signed-off-by: Marek Vasut ma...@denx.de
Cc:
Move the struct ehci_ctrl defition from ehci-hcd.c into ehci.h
so it can be re-used by drivers. In particular, the mv_udc driver
can benefit from this move.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador
Check the length of system cacheline at compile-time and fail
if the system uses too long cachelines.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
The code for retrieving qTD item for particular endpoint is hard
to understand, moreover it's duplicated all over the driver. Move
the code into single nice and documented function.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen
The code for retrieving QH for particular endpoint is hard to understand,
moreover it's duplicated all over the driver. Move the code into single
nice and documented function.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc:
There is no need to init this field at runtime, so init it statically.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
Both the endpoint queue head and the endpoint item list is a controller
specific thing. Move them both into controller private data.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Allocate the qTD items all at once instead of allocating them
separately. Moreover, make sure each qTD is properly aligned
to 32-bytes boundary and that cache can be safely flushed over
each qTD touple.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei
The requests sent to the controller are not properly cache aligned
most of the time, thus implement a simple bounce buffer to avoid
problem with cache.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador
From: Kuo-Jung Su dant...@faraday-tech.com
1. Update license statement
2. struct ftmac110_regs __iomem *regs - struct ftmac110_regs *regs.
3. Reformat hardware tx/rx descriptor as an uniform one,
and replace uint32_t[2] with uint64_t for descriptor control.
Changes for v2:
- Re-send these
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/ftmac110.c | 17 ++---
drivers/net/ftmac110.h | 17 ++---
2 files changed, 28 insertions(+), 6 deletions(-)
From: Kuo-Jung Su dant...@faraday-tech.com
1. Reformat tx/rx descriptor as an uniform struct.
2. Replace uint32_t[2] with uint64_t for descriptor control.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/ftmac110.c | 86
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/ftmac110.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c
On 09/07/13 23:05, amar_g wrote:
This patch resolves the below mentiond compilation error of i2c driver
typo.. maybe mentiond will be mentioned?
for non-FDT case
Compilation error:
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error: 'CONFIG_MAX_I2C_NUM' undeclared
On Tue, 2013-07-09 at 06:17 +0800, Joe Hershberger wrote:
Hi Jim and Stephen,
On Wed, Jul 3, 2013 at 11:01 PM, Jim Lin ji...@nvidia.com wrote:
TFTP booting is slow when a USB keyboard is installed and
CONFIG_USB_KEYBOARD is defined.
This fix is to change Ctrl-C polling to every second
Signed-off-by: Pardeep Kumar Singla b45...@freescale.com
---
board/freescale/mx6qsabresd/mx6qsabresd.c | 92 -
include/configs/mx6qsabre_common.h|3 +-
include/configs/mx6qsabresd.h | 13
3 files changed, 106 insertions(+), 2
1 - 100 of 108 matches
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