Hi Albert,
On Tue, Aug 5, 2014 at 10:30 AM, Chris Packham judge.pack...@gmail.com wrote:
On 14/07/14 17:01, Chris Packham wrote:
In order to use configuration flags it is necessary to include config.h.
Without this arm targets that use CONFIG_USE_IRQ or CONFIG_SPL_BUILD
won't get the correct
On Tue, Aug 19, 2014 at 03:28:09PM -0600, Simon Glass wrote:
Hi Thierry,
On 19 August 2014 07:12, Thierry Reding thierry.red...@gmail.com wrote:
On Tue, Aug 19, 2014 at 06:55:18AM -0600, Simon Glass wrote:
On 19 August 2014 05:35, Thierry Reding thierry.red...@gmail.com wrote:
[...]
On Tue, Aug 19, 2014 at 01:48:55PM +, Marcel Ziswiler wrote:
+ /* TPS659110: LDO2_REG = 1.05V, ACTIVE */
+ data[0] = 0x15;
+ addr = 0x31;
+
+ err = i2c_read(PMU_I2C_ADDRESS, addr, 1, data, 1);
You sure about that read?
Me wondering why it did not work on my shiny Apalis
Hi Kishon,
On Tuesday 19 August 2014 08:58 PM, Felipe Balbi wrote:
On Tue, Aug 19, 2014 at 08:48:36PM +0530, Kishon Vijay Abraham I
wrote:
Hi Lukasz,
On Tuesday 19 August 2014 02:22 PM, Lukasz Majewski wrote:
Hi Kishon,
In order to support multiple USB device controllers in
Benoît,
On Tue, Aug 19, 2014 at 8:35 PM, Benoît Thébaudeau
benoit.thebaudeau@gmail.com wrote:
Commit 41623c9 'arm: move exception handling out of start.S files' missed some
linker scripts. Hence, some boards no longer had exception handling linked
since
this commit. Restore the original
Hi Kishon,
On Monday 18 August 2014 08:26 PM, Lukasz Majewski wrote:
Hi Kishon,
Explicity set the max packet size in the device descriptor to 0x40
as specified in the device class specification for device firmware
upgrade. Also changed debug to printf to explicitly notify the
This patch adds support for Olimex A20-OLinuXino-LIME board.
Signed-off-by: FUKAUMI Naoki nao...@gmail.com
---
board/sunxi/Makefile | 1 +
board/sunxi/dram_a20_olinuxino_l.c | 31 +++
configs/A20-OLinuXino-Lime_defconfig | 5 +
3 files changed,
Hi Felipe,
On Tue, Aug 19, 2014 at 09:08:00PM +0530, Kishon Vijay Abraham I
wrote:
On Monday 18 August 2014 08:26 PM, Lukasz Majewski wrote:
Hi Kishon,
Explicity set the max packet size in the device descriptor to
0x40 as specified in the device class specification for
On Tue, 2014-08-19 at 15:42 -0600, Stephen Warren wrote:
At a quick glance this looks OK,
Acked-by: Stephen Warren swar...@nvidia.com
Thanks mate. Glad to get ready for more PCIe action now.
One very minor nit:
diff --git a/arch/arm/dts/tegra30-apalis.dts
Hi Kishon,
Hi,
On Tuesday 19 August 2014 02:23 PM, Lukasz Majewski wrote:
Hi Kishon,
Since there can be multiple USB controllers in the system,
usb_gadget_handle_interrupts should take controller index as
arguments.
The controller index is passed in the ums/dfu/thor command.
On Wed, 2014-08-20 at 08:38 +0200, Thierry Reding wrote:
Hehe... this should probably be i2c_write() instead. Perhaps this is on
by default on Beaver and Cardhu but not on the particular revision that
Apalis T30 uses?
Well, we anyway use a completely different rail configuration but me
just
Hi Chris,
On Tue, 05 Aug 2014 20:30:36 +1200, Chris Packham
judge.pack...@gmail.com wrote:
On 14/07/14 17:01, Chris Packham wrote:
In order to use configuration flags it is necessary to include config.h.
Without this arm targets that use CONFIG_USE_IRQ or CONFIG_SPL_BUILD
won't get the
On Wed, Aug 20, 2014 at 03:39:37AM +0100, AlisonWang wrote:
Hi, Mark,
On Tue, Aug 19, 2014 at 03:54:50AM +0100, Alison Wang wrote:
+int timer_init(void)
+{
+ struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+ unsigned long ctrl, val, freq;
+
+
Hi,
What is the recommended tool-chain to verify compilation of MIPS boards?
I tried the one from
https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
But it does not work, throws plenty of errors about hard/soft float.
Regards,
Vasili
Hi Ye,
On 20/08/2014 10:55, Ye.Li wrote:
From: Ye.Li ye...@freescale.com
The load region size of EIM-NOR are defined to 0. For this case,
the parameter imximage_init_loadsize must be calculated.
The imximage tool implements the calculation in the imximage_generate
function, but the
On Wed, Aug 20, 2014 at 10:56:58AM +0200, Marcel Ziswiler wrote:
On Wed, 2014-08-20 at 08:38 +0200, Thierry Reding wrote:
Hehe... this should probably be i2c_write() instead. Perhaps this is on
by default on Beaver and Cardhu but not on the particular revision that
Apalis T30 uses?
Well,
Hi Ye,
On 20/08/2014 11:18, Ye.Li wrote:
From: Ye.Li ye...@freescale.com
The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.
But when using Plugin mode
Hi Prafulla,
On Wed, 6 Aug 2014 03:09:25 -0700, Prafulla Wadaskar
prafu...@marvell.com wrote:
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-
boun...@lists.denx.de] On Behalf Of Prafulla Wadaskar
Sent: 06 August 2014 15:35
To: Masahiro Yamada;
Hi Fabio, hi Magnus,
On 12/08/2014 22:29, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Currently I don't have access to a mx31pdk board.
Magnus was the original maintainer of the board and accepted to take back
this role.
Signed-off-by: Fabio Estevam
Hi Marek,
On 04/08/2014 01:47, Marek Vasut wrote:
Fix the name of the CCM CHSCCDR register.
Signed-off-by: Marek Vasut ma...@denx.de
---
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
--
=
DENX Software
On 04/08/2014 01:47, Marek Vasut wrote:
The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but
only 3840 MiB of that can be really used. In case the controller is
configured to operate a 4GiB module, the imx_ddr_size() function will
correctly compute that there is 4GiB of DRAM
On 20.08.2014 11:35, Vasili Galka wrote:
Hi,
What is the recommended tool-chain to verify compilation of MIPS boards?
you could try
Denx ELDK 5.5 for MIPS
http://www.denx.de/wiki/ELDK-5/WebHome
or
Mentor Sourcery CodeBench Lite Edition for MIPS ELF
Hi Marek,
On 04/08/2014 01:47, Marek Vasut wrote:
The COL field value cannot be easily calculated from the desired
column number. Instead, there are special cases for that, see the
datasheet, MMDCx_MDCTL field description, field COL . Cater for
those special cases.
Signed-off-by: Marek
Hi Marek,
On 04/08/2014 01:47, Marek Vasut wrote:
Building the SPL in Thumb mode saves roughly 30% in size of the
resulting SPL binary. As the size of SPL it limited on the MX6,
this helps a lot.
Signed-off-by: Marek Vasut ma...@denx.de
---
Applied to u-boot-imx, thanks !
Best regards,
Hi Peter, hi Marek,
On 19/06/2014 09:12, Marek Vasut wrote:
On Wednesday, June 18, 2014 at 08:17:05 PM, Peter Schumann wrote:
Am 17.06.2014 18:00, schrieb Stefano Babic:
Hi peter,
...
On 17/06/2014 00:19, Marek Vasut wrote:
Agree. Reason is that this change is for all boards, and without a
Hi Tim,
On 08/08/2014 07:57, Tim Harvey wrote:
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.
Without this patch we find a high link failure rate (5%) on
Hi Fabio,
On 15/08/2014 06:00, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Use the latest DDR initialization values suggested by the FSL hardware team.
While at it, add some comments for clarification.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Christian,
On Wed, Aug 20, 2014 at 9:21 AM, Christian Riesch
christian.rie...@omicron.at wrote:
Benoît,
On Tue, Aug 19, 2014 at 8:35 PM, Benoît Thébaudeau
benoit.thebaudeau@gmail.com wrote:
Commit 41623c9 'arm: move exception handling out of start.S files' missed
some
linker scripts.
Hi Tim,
On 18/08/2014 15:52, Tim Harvey wrote:
On Thu, Aug 14, 2014 at 8:23 AM, Stefano Babic sba...@denx.de wrote:
On 08/08/2014 07:35, Tim Harvey wrote:
There are many similarities between the IMX6QUAD/IMX6DUAL and there are
many similarities between the IMX6SOLO/IMX6DUALITE. Add a
Hi Tim,
On 08/08/2014 07:35, Tim Harvey wrote:
NAND devices have differing layouts with respect to page size and pages per
block. These parameters affect the parameters that need to be passed to
mkfs.ubifs and ubinize used to create UBI images. The various NAND chips
supported by Gateworks
Hi Tim,
On 08/08/2014 07:35, Tim Harvey wrote:
During manufacturing this bit is not getting enabled when it should be, so
we will ignore it.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
On 08/08/2014 07:35, Tim Harvey wrote:
The Gateworks System Controller EEPROM config is flash based. Add a delay
following writes to avoid errors on back-to-back writes.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gsc.c | 2 +-
1 file changed, 1
On 08/08/2014 07:35, Tim Harvey wrote:
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index
On 08/08/2014 07:35, Tim Harvey wrote:
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
b/board/gateworks/gw_ventana/gw_ventana.c
index
Hi Tim,
On 08/08/2014 07:35, Tim Harvey wrote:
The i2c_dis# pinmux/padconf was missing for the GW53xx (this feature was
added to the GW53xx on revB PCB's). Additionally, remove the duplicate
config for GW54xx.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
Hi Tim,
On 08/08/2014 07:35, Tim Harvey wrote:
Enable the SION bit on gpio outputs that we wish to be able to read the
value of.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 133
+---
1 file changed, 70
Hi Tim,
On 08/08/2014 07:35, Tim Harvey wrote:
The PCISKT_WDIS# gpio allows for asserting WDIS# going to the various PCIe
sockets on the Ventana board.
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 17 +
1 file changed, 17
Hi Tim,
On 08/08/2014 07:35, Tim Harvey wrote:
Signed-off-by: Tim Harvey thar...@gateworks.com
---
board/gateworks/gw_ventana/gw_ventana.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c
Hi Tim,
On 08/08/2014 07:35, Tim Harvey wrote:
The Gateworks Ventana EEPROM contains a set of configuration bits that
affect the removal of device-tree nodes that support peripherals that do not
exist on sub-loaded boards. This patch adds:
- a structure to define a config bit name, dt node
Hi Fabio,
On 15/08/2014 02:00, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
mx6sxsabresd was not in the master branch when the conversion to the new
Kconfig
style happened, so convert it now so that it can build again.
Signed-off-by: Fabio Estevam
On Tuesday, August 19, 2014 at 12:17:38 PM, Lukasz Majewski wrote:
Hi Marek,
The following changes since commit
401abbf150e55e974829a7cc64584d9e463fc5ea:
usb: ehci: rmobile: Remove xHCI address (2014-07-28 12:47:31 +0200)
are available in the git repository at:
The following changes since commit e49f14af1349eef94e41b636320bbfcace7403b5:
patman: Only use git's --no-decorate when available (2014-08-13 08:34:16
-0600)
are available in the git repository at:
git://git.denx.de/u-boot-usb.git HEAD
for you to fetch changes up to
Hi Fabio,
On 15/08/2014 05:24, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Configure and enable the ethernet clock for mx6solox.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
arch/arm/cpu/armv7/mx6/clock.c | 21 +
1 file
Hi Fabio,
On 15/08/2014 05:24, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.
Add support for one FEC port initially.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
FEC is not
Forgot to answer this part:
On 13/08/14 15:55, Igor Grinberg wrote:
Hi Nikita,
[...]
+}
+#else
+static void cm_fx6_setup_ecspi(void) { }
+#endif
+
+void board_init_f(ulong dummy)
+{
+ gd = gdata;
+ enable_usdhc_clk(1, 2);
can this be done inside board_mmc_init() or even in a
The tools/genboardscfg.py expects all the Kconfig and defconfig are
written correctly. Imagine someone accidentally has broken a board.
Error-out just for one broken board is annoying for the other
developers. Let the tool skip insane boards and continue processing.
Signed-off-by: Masahiro
tools/genboardscfg.py expects all the boards have MAINTAINERS.
If someone adds a new board but misses to add its MAINTAINERS file,
tools/genboardscfg.py fails to generate the boards.cfg file.
It is annoying for the other developers.
This commit allows tools/genboardscfg.py to display warning
This series depends on the following prerequisites
http://patchwork.ozlabs.org/patch/380316/
http://patchwork.ozlabs.org/patch/376222/
Masahiro Yamada (7):
tools/genboardscfg.py: ignore defconfigs starting with a dot
tools/genboardscfg.py: be tolerant of missing MAINTAINERS
I guess some developers are already getting sick of this tool
because it takes a few minites to generate the boards.cfg
on reasonable computers.
This commit makes it about 4 times faster.
You might not be satisfied at all, but better than now.
Signed-off-by: Masahiro Yamada
This tool deletes the incomplete boards.cfg
if it encounters an error or is is terminated by the user.
I notice some problems even though they rarely happen.
[1] The boards.cfg is removed if the program is terminated
during __gen_boards_cfg() function but before boards.cfg
is actually touched.
It looks silly to regenerate the boards.cfg even when it is
already up to date.
The tool should exit with doing nothing if the boards.cfg is newer
than any of defconfig, Kconfig and MAINTAINERS files.
Specify -f (--force) option to get the boards.cfg regenerated
regardless its time stamp.
Kconfig in U-Boot creates a temporary file configs/.tmp_defconfig
during processing make board_defconfig. The temporary file
might be left over for some reasons.
Just in case, tools/genboardscfg.py should make sure to
not read such garbage files.
Signed-off-by: Masahiro Yamada
When an error occurs or the program is terminated by the user
on the way, the destructer __del__ of class Slot is invoked and
the work directories are removed.
We have to make sure there are no subprocesses (in this case,
make O=work_dir ...) using the work directories before
removing them.
Hi Daniel,
On Wed, Aug 20, 2014 at 1:23 PM, Daniel Schwierzeck
daniel.schwierz...@gmail.com wrote:
On 20.08.2014 11:35, Vasili Galka wrote:
Hi,
What is the recommended tool-chain to verify compilation of MIPS boards?
you could try
Denx ELDK 5.5 for MIPS
On Wed, Aug 20, 2014 at 01:12:21PM +0200, Marek Vasut wrote:
The following changes since commit e49f14af1349eef94e41b636320bbfcace7403b5:
patman: Only use git's --no-decorate when available (2014-08-13 08:34:16
-0600)
are available in the git repository at:
Current way of calculation CS0_END field for MMDCx_MDASP register
is problematic because in most cases the user is forced to define
cs_density in an unnatural way: as value - 2, instead of value.
This breaks the abstraction provided by struct mx6_ddr_sysinfo
because the user is forced to be aware
This patch series introduces the mx6 based cm-fx6 board.
cm-fx6 comes with either single, dual, or quad core mx6 soc, and various dram
configurations.
First 12 patches are preparatory steps which include:
- Cleanups and bug fixes for the mx6 dram config code
- New functions and
Define the new common function sata_port_status() which can be
used to query the sata driver for the state of ports, and implement it
for dwc_ahsata.
Cc: Stefano Babic sba...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Marek Vasut ma...@denx.de
Reviewed-by: Marek Vasut ma...@denx.de
Signed-off-by:
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:
cs = (cs | gpio 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is
Add functions to enable/disable clocks for UART, SPI, ENET, and MMC.
Cc: Stefano Babic sba...@denx.de
Cc: Igor Grinberg grinb...@compulab.co.il
Acked-by: Igor Grinberg grinb...@compulab.co.il
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V4:
- No changes.
Changes in
Add NAND support for Compulab CM-FX6 CoM.
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Cc: Tom Rini tr...@ti.com
Acked-by: Igor Grinberg grinb...@compulab.co.il
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V4:
- Introduce nand
Add USB and USB OTG host support for Compulab CM-FX6 CoM.
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Cc: Tom Rini tr...@ti.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V4:
- cm_fx6_init_usb_otg() returns an int
- Use
Add macro which defines i2c_pads_info structs for multiple SoC types,
and a macro which selects the appropriate struct based on CPU type,
thus eliminating the need to manage multiple i2c pad configurations
manually when supporting multiple SoC types.
Cc: Stefano Babic sba...@denx.de
Cc: Tim
Add support for M25PE16 and M25PX16
Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Marek Vasut ma...@denx.de
Acked-by: Marek Vasut ma...@denx.de
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V4:
- No changes.
Changes in V3:
- No changes.
Bit 16 in mapsr register is in a reserved field. Don't write to it.
Cc: Stefano Babic sba...@denx.de
Cc: Tim Harvey thar...@gateworks.com
Acked-by: Tim Harvey thar...@gateworks.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V4:
- No changes.
Changes in V3:
Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
SPL. These #defines do not allow the user to select SPI mode for the SPI flash
(there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
spi_spl_load.c), and duplicate information already provided by
According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).
Configure MMDC for slow pd.
Cc: Stefano Babic sba...@denx.de
Cc: Tim Harvey
Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM
module what I2C bus the EEPROM is located at. Make cl_eeprom_read()
switch to that bus when reading EEPROM.
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Dmitry Lifshitz lifsh...@compulab.co.il
Cc: Tom Rini tr...@ti.com
Cc: Marek Vasut
Add initial support for Compulab CM-FX6 CoM.
Support includes MMC, SPI flash, and SPL with dynamic DRAM detection.
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Marek Vasut ma...@denx.de
Cc: Simon Glass s...@chromium.org
Acked-by: Marek
Add support for SATA.
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Cc: Tom Rini tr...@ti.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V4:
- Use load instead of fatload.
- Removed default declaration of cm_fx6_setup_issd()
Use Compulab eeprom module to obtain revision number, serial number, and
mac address from the EEPROM.
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Cc: Tom Rini tr...@ti.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V4:
- Introduce
No functional changes.
Cc: Stefano Babic sba...@denx.de
Cc: Tim Harvey thar...@gateworks.com
Acked-by: Tim Harvey thar...@gateworks.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V4:
- No changes.
Changes in V3:
- No changes.
Changes in V2:
- No
Add support for all 3 I2C busses on Compulab CM-FX6 CoM.
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Cc: Tom Rini tr...@ti.com
Acked-by: Igor Grinberg grinb...@compulab.co.il
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V4:
- No
Define get_cpu_type(). Reuse it in is_cpu_type().
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
New patch for V4 of series.
arch/arm/include/asm/arch-mx6/sys_proto.h | 5 +++--
1 file changed, 3 insertions(+),
Add ethernet support for Compulab CM-FX6 CoM
Cc: Igor Grinberg grinb...@compulab.co.il
Cc: Stefano Babic sba...@denx.de
Cc: Tom Rini tr...@ti.com
Acked-by: Igor Grinberg grinb...@compulab.co.il
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V4:
- No changes
Changes
To better enable debug of u-boot itself (in particular SPL). To debug
u-boot you want to put your board in JTAG boot mode for quick recompile
and elf downloads via the JTAG debugger. Yet you may still want to boot
from a persistent storage media (SD or QSPI). Allow override of the
boot mode pins
On 20.08.2014 13:50, Vasili Galka wrote:
Hi Daniel,
On Wed, Aug 20, 2014 at 1:23 PM, Daniel Schwierzeck
daniel.schwierz...@gmail.com wrote:
On 20.08.2014 11:35, Vasili Galka wrote:
Hi,
What is the recommended tool-chain to verify compilation of MIPS boards?
you could try
Denx
Hi Daniel,
On Wed, Aug 20, 2014 at 3:20 PM, Daniel Schwierzeck
daniel.schwierz...@gmail.com wrote:
On 20.08.2014 13:50, Vasili Galka wrote:
Hi Daniel,
On Wed, Aug 20, 2014 at 1:23 PM, Daniel Schwierzeck
daniel.schwierz...@gmail.com wrote:
On 20.08.2014 11:35, Vasili Galka wrote:
Hi,
From: Ye.Li ye...@freescale.com
The load region size of EIM-NOR are defined to 0. For this case,
the parameter imximage_init_loadsize must be calculated.
The imximage tool implements the calculation in the imximage_generate
function, but the following function imximage_set_header resets the value
From: Ye.Li ye...@freescale.com
The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.
But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch
On Wed, 2014-08-20 at 11:46 +0200, Thierry Reding wrote:
Wow, 3.9 MiB/s on average. I only get around 2.0 MiB/s on all my
devices. TrimSlice is the exception with around 5.0 MiB/s. I wonder
where exactly that comes from. It's the oldest device so I'd expect
it to be the slowest too.
That's
2014-08-19 20:01 GMT+09:00 Stefan Roese s...@denx.de:
Please use SPDX license identifiers instead. Please fix this globally.
Thanks!
I have sent a follow up patch.
http://patchwork.ozlabs.org/patch/381530/
--
Best Regards
Masahiro Yamada
___
Hi Thierry,
On 20 August 2014 00:36, Thierry Reding thierry.red...@gmail.com wrote:
On Tue, Aug 19, 2014 at 03:28:09PM -0600, Simon Glass wrote:
Hi Thierry,
On 19 August 2014 07:12, Thierry Reding thierry.red...@gmail.com wrote:
On Tue, Aug 19, 2014 at 06:55:18AM -0600, Simon Glass wrote:
Hi Albert,
please pull from u-boot-imx, thanks !
The following changes since commit 1899fac925eda817e12234aef3d01d354788662e:
Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'
(2014-08-09 16:48:34 +0200)
are available in the git repository at:
On Wed, Aug 20, 2014 at 09:34:13AM +0200, Lukasz Majewski wrote:
Hi Felipe,
On Tue, Aug 19, 2014 at 09:08:00PM +0530, Kishon Vijay Abraham I
wrote:
On Monday 18 August 2014 08:26 PM, Lukasz Majewski wrote:
Hi Kishon,
Explicity set the max packet size in the device
Hi Andreas,
I'm trying to verify the correct build of all AVR32 boards. What is
the recommended toolchain to use?
I tried the one that comes with Ubuntu:
sudo apt-get install gcc-avr binutils-avr gdb-avr avr-libc avrdude
But it does not work, I get the following build errors:
Building
Albert,
Please pull u-boot-tegra/master into ARM/master. Thanks!
./MAKEALL -s tegra AOK, checkpatch.pl is OK, and ./MAKEALL -a arm only
shows failures that were already present in ARM/master.
The following changes since commit 1899fac925eda817e12234aef3d01d354788662e:
Merge branch
On 19 August 2014 02:22, Thierry Reding thierry.red...@gmail.com wrote:
From: Thierry Reding tred...@nvidia.com
When creating build directories also create parents as necessary. This
fixes a failure when building a hierarchical branch (i.e. foo/bar).
Signed-off-by: Thierry Reding
On 08/18/2014 07:55 PM, Alison Wang wrote:
From: Jingchang Lu jingchang...@freescale.com
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu jingchang...@freescale.com
Hi Simon, Tom and Stephen,
Could you guys review this patch which solved the issue York reported?
Thanks,
-Bryan
On Fri, Aug 15, 2014 at 4:51 PM, Bryan Wu coolo...@gmail.com wrote:
Commit b3dd64f5d537 bootm: use genimg_get_kernel_addr() introduced
a bug for booting FIT image. It's because
On 08/18/2014 07:55 PM, Alison Wang wrote:
From: Wang Huan b18...@freescale.com
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v5: Change the patch order.
On 08/14/2014 08:59 PM, Simon Glass wrote:
Buildman has been around for a little over a year and is used by a fair
number of U-Boot developers. However quite a few people still use MAKEALL.
Buildman was intended to replace MAKEALL, so perhaps now is a good time to
start that process.
The
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.
I see no issue with the
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
This reset is required for PCIe and the corresponding ID therefore needs
to be defined.
It might be worth mentioning in the commit description why this patch
does different things for each SoC; namely that
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Implement the powergate API that allows various power partitions to be
power up and down.
diff --git a/arch/arm/cpu/tegra-common/powergate.c
b/arch/arm/cpu/tegra-common/powergate.c
+static int
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.
Aside from the differing #address-cells at the top-level of the DT, this
matches what's been proposed for the Linux kernel,
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.
Aside from the differing #address-cells at the top-level of the DT,
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
Add the device tree node for the PCIe controller found on Tegra20 SoCs.
This matches the kernel, so
Acked-by: Stephen Warren swar...@nvidia.com
___
U-Boot mailing
On 08/18/2014 01:16 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.
diff --git a/arch/arm/dts/tegra20-trimslice.dts
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