Move firewall related code new firewall.c in order to share
code in Stratix 10 and Agilex.
No functional change.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile| 1 +
arch/arm/mach-socfpga/firewall.c | 97 +++
Add reset manager support for Agilex.
Signed-off-by: Ley Foon Tan
---
.../mach-socfpga/include/mach/reset_manager.h | 5 ++-
.../include/mach/reset_manager_agilex.h | 38 +++
arch/arm/mach-socfpga/reset_manager.c | 9 +++--
3 files changed, 48 insertions(+), 4
Add system manager support for Agilex.
Signed-off-by: Ley Foon Tan
---
.../include/mach/system_manager.h | 6 +
.../include/mach/system_manager_agilex.h | 127 ++
2 files changed, 133 insertions(+)
create mode 100644
Add build support for Agilex SoC.
Signed-off-by: Ley Foon Tan
---
arch/arm/Kconfig | 4 +-
arch/arm/mach-socfpga/Kconfig | 13 ++
arch/arm/mach-socfpga/Makefile | 9 +
configs/socfpga_agilex_defconfig | 57 +++
Add base address for Intel Agilex SoC.
Signed-off-by: Ley Foon Tan
---
.../include/mach/base_addr_agilex.h | 38 +++
1 file changed, 38 insertions(+)
create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_agilex.h
diff --git
Move Stratix10 and Agilex reset manager common code to reset.h.
Remove unused RSTMGR_XXX defines.
Signed-off-by: Ley Foon Tan
---
.../mach-socfpga/include/mach/reset_manager.h | 26 ++
.../include/mach/reset_manager_s10.h | 80 ---
2 files changed, 26
This patchset add Intel Agilex SoC[1] support.
Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in Agilex are CCU, clock manager and SDRAM,
other IPs have minor changes compared to Stratix 10.
Intel Agilex HPS TRM:
This commit adds the first of a few more Xilinx ZYNQ based SoM boards.
The SoM is based on Xilinx Zynq 7000 SoC.
Mainly vxWorks 6.9.4.x is running on the board,
doing some PLC stuff on various carrier boards.
Signed-off-by: Hannes Schmelzer
---
Changes in v3:
- drop silicon version 1/2 from
On 5/9/19 11:49 PM, Michal Simek wrote:
On 08. 05. 19 5:37, Hannes Schmelzer wrote:
On 5/3/19 6:29 PM, Michal Simek wrote:
On 03. 05. 19 6:18, Tom Rini wrote:
On Fri, May 03, 2019 at 01:34:24PM +0200, Hannes Schmelzer wrote:
On 5/2/19 9:03 PM, Tom Rini wrote:
On Thu, May 02, 2019 at
On Thu, May 9, 2019 at 4:22 PM Horatiu Vultur
wrote:
>
> Hi Joe,
>
> The 05/09/2019 21:03, Joe Hershberger wrote:
> > External E-Mail
> >
> >
> > On Wed, May 1, 2019 at 6:18 AM Horatiu Vultur
> > wrote:
> > >
> > > Update Luton network driver to have support also for pcb90. The pcb90
> > > has
We always want to enumerate PCIe devices, because withouth this they
won't work in Linux.
Signed-off-by: Marek Behún
---
board/CZ.NIC/turris_omnia/turris_omnia.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c
If SCSI and USB boot options are both available, try to boot from SCSI
first.
Signed-off-by: Marek Behún
---
include/configs/turris_omnia.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h
index
The board code reads MAC addresses from the ATSHA204A cryptochip.
For compatibility reasons the ethernet adapters on this SOC are not
enumerated in register address order. But when Omnia was first
manufactured this was done differently.
Change setting of MAC addresses to conform to the
This is not needed here since Omnia is using DM_PCI now.
Signed-off-by: Marek Behún
---
include/configs/turris_omnia.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h
index 8e3d5cc8cf..26f85466a4 100644
---
The U-Boot partition is 1 MiB and environment is 64 KiB. It does not
make sense to have environment at 0xc when it could be at 0xf
and we can have more space for U-Boot binary.
Signed-off-by: Marek Behún
---
include/configs/turris_omnia.h | 4 ++--
1 file changed, 2 insertions(+), 2
Hi Stefan, I am sending five another fixes for Turris Omnia.
Marek
Marek Behún (6):
arm: mvebu: turris_omnia: set default ethernet adapter
arm: mvebu: turris_omnia: fix adapters MAC addresses
arm: mvebu: turris_omnia: change environment address in SPI flash
arm: mvebu: turris_omnia:
Set default value for the ethact variable to the WAN port.
Signed-off-by: Marek Behún
---
include/configs/turris_omnia.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h
index 018f54428b..290828d73e 100644
---
The local device (host "bridge"?) on pci_mvebu controller reports
PCI_CLASS_MEMORY_OTHER in the class register.
This does not work in U-Boot, because U-Boot then tries to autoconfigure
this device in pci_auto.c. This causes the real connected PCIe device
not to work (in U-Boot nor in Linux).
Hi Bernhard,
On Mon, 1 Apr 2019 at 02:33, Bernhard Messerklinger
wrote:
>
> With the introduction of the new spi-mem model operations changed
> slightly, which broke the ich-spi driver. The new spi-mem operations
> make things a bit easier to handle for ich flash interface. This patch
> makes
On Mon, Apr 22, 2019 at 04:28:01PM -0500, Sam Voss wrote:
> Validation of fit image configuration signatures does not seem to do a
> "fall-back" mechanism as mentioned in doc/uImage.FIT/signature.txt.
>
> The current constraints seem to only allow the following:
>
> - skipping keys not marked
On Thu, May 09, 2019 at 06:44:05PM +0800, Kever Yang wrote:
> Here is the v2 of second batch of changes for the Rockchip repository.
> Drop support for rk3399 neo4, rockpro64, rock-pi boards support since v1.
>
> Clean bill-of-health in Travis-CI at
>
>
On Thu, May 09, 2019 at 12:08:29PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the following Marvell related patches:
>
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
___
U-Boot mailing list
lowing changes since commit 504bf790da08db9b4a443566cf6ef577f9c7996a:
>
> Merge branch 'master' of git://git.denx.de/u-boot-sunxi (2019-05-08
> 16:21:43 -0400)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-amlogic.git tags/u-boot-amlogic-20190509
>
> for you to fetch
On Thu, May 09, 2019 at 05:08:08PM +0800, ub...@andestech.com wrote:
> Hi Tom,
>
> Please pull some riscv updates:
>
> - Correct SYS_TEXT_BASE for qemu.
> - Support booti.
> - Increase SYSBOOTM_LEN for Fedora/RISCV kernel.
> - Support SMP booting from flash.
>
>
On Wed, May 08, 2019 at 05:30:11PM -0500, Joe Hershberger wrote:
> Hi Tom,
>
> This is the series with the AR8xxx phy series removed until we figure it out.
>
> Tested to work fine on your evm.
>
> The following changes since commit 8d7f06bbbef16f172cd5e9c4923cdcebe16b8980:
>
> Merge branch
On 08. 05. 19 5:37, Hannes Schmelzer wrote:
>
>
> On 5/3/19 6:29 PM, Michal Simek wrote:
>> On 03. 05. 19 6:18, Tom Rini wrote:
>>> On Fri, May 03, 2019 at 01:34:24PM +0200, Hannes Schmelzer wrote:
On 5/2/19 9:03 PM, Tom Rini wrote:
> On Thu, May 02, 2019 at 08:34:32PM +0200,
Hi Joe,
The 05/09/2019 21:03, Joe Hershberger wrote:
> External E-Mail
>
>
> On Wed, May 1, 2019 at 6:18 AM Horatiu Vultur
> wrote:
> >
> > Update Luton network driver to have support also for pcb90. The pcb90
> > has 24 ports from which 12 ports are connected to SerDes6G.
>
> Can you
On Fri, Apr 26, 2019 at 6:16 AM Christophe Roullier
wrote:
>
> Synopsys GMAC 4.20 is used. And Phy mode for eval and disco is RMII
> with PHY Realtek RTL8211 (RGMII)
> We also support some other PHY config on stm32mp157c
> PHY_MODE(MII,GMII, RMII, RGMII) and in normal,
> PHY wo crystal
On 5/9/19 10:11 PM, Simon Goldschmidt wrote:
> This series converts (hopefully) all drivers used in socfpga to livetree
> so that none of them references 'gd' any more (with the exception of
> some a10/s10 drivers that should be fixed).
>
>
> Simon Goldschmidt (6):
> timer: dw-apb: remove
On 5/9/19 8:08 PM, Simon Goldschmidt wrote:
> This adds a UCLASS_SYSRESET sysreset driver for socfgpa gen5.
>
> Signed-off-by: Simon Goldschmidt
> ---
>
> Changes in v3:
> - moved socfpga gen5 sysreset driver to extra patch
>
> Changes in v2: None
[...]
> +static int
Hi Thierry,
On Thu, Apr 25, 2019 at 8:32 AM Thierry Reding wrote:
>
> On Tue, Apr 16, 2019 at 04:36:16PM +, Joe Hershberger wrote:
> > On Tue, Apr 16, 2019 at 11:21 AM Thierry Reding
> > wrote:
> > >
> > > From: Thierry Reding
> > >
> > > Implement this callback that allows the MAC address
On 5/9/19 8:55 PM, Simon Goldschmidt wrote:
>
>
> On 09.05.19 20:08, Simon Goldschmidt wrote:
>> This adds a UCLASS_SYSRESET sysreset driver for socfgpa gen5.
>>
>> Signed-off-by: Simon Goldschmidt
>> ---
>>
>> Changes in v3:
>> - moved socfpga gen5 sysreset driver to extra patch
>>
>> Changes
On 5/9/19 8:42 PM, Simon Goldschmidt wrote:
[...]
> diff --git a/include/configs/socfpga_vining_fpga.h
> b/include/configs/socfpga_vining_fpga.h
> index 29a92b9146..737a304217 100644
> --- a/include/configs/socfpga_vining_fpga.h
> +++ b/include/configs/socfpga_vining_fpga.h
> @@ -145,6 +145,7 @@
On Wed, May 1, 2019 at 6:18 AM Horatiu Vultur
wrote:
>
> Update Luton network driver to have support also for pcb90. The pcb90
> has 24 ports from which 12 ports are connected to SerDes6G.
Can you separate this into a restructuring patch and the patch that
adds support for this device? This is a
On Sat, May 4, 2019 at 12:28 PM Marek Vasut wrote:
>
> Add ifdeffery to allow operation without the clock framework
> enabled. This is required on RZ/A1, as it does not have clock
> driver yet.
>
> Signed-off-by: Marek Vasut
> Cc: Chris Brandt
> Cc: Joe Hershberger
> Cc: Nobuhiro Iwamatsu
On Sat, May 4, 2019 at 12:28 PM Marek Vasut wrote:
>
> Add support for RZ/A1 SoC specifics.
>
> Signed-off-by: Marek Vasut
> Cc: Chris Brandt
> Cc: Joe Hershberger
> Cc: Nobuhiro Iwamatsu
Acked-by: Joe Hershberger
___
U-Boot mailing list
On Wed, May 1, 2019 at 5:36 PM Marek Vasut wrote:
>
> According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the
> TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3
> (r8a77995).
>
> Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM
>
On 5/9/19 10:26 PM, Joe Hershberger wrote:
> On Thu, May 9, 2019 at 3:24 PM Marek Vasut wrote:
>>
>> On 5/9/19 10:18 PM, Joe Hershberger wrote:
>>> On Thu, May 9, 2019 at 3:01 PM Marek Vasut wrote:
On 5/9/19 8:56 PM, Joe Hershberger wrote:
> On Wed, May 1, 2019 at 5:36 PM Marek
On Thu, May 9, 2019 at 3:24 PM Marek Vasut wrote:
>
> On 5/9/19 10:18 PM, Joe Hershberger wrote:
> > On Thu, May 9, 2019 at 3:01 PM Marek Vasut wrote:
> >>
> >> On 5/9/19 8:56 PM, Joe Hershberger wrote:
> >>> On Wed, May 1, 2019 at 5:36 PM Marek Vasut wrote:
>
> According to the R-Car
On Thu, May 9, 2019 at 3:01 PM Marek Vasut wrote:
>
> On 5/9/19 8:56 PM, Joe Hershberger wrote:
> > On Wed, May 1, 2019 at 5:36 PM Marek Vasut wrote:
> >>
> >> According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the
> >> TX clock internal delay mode isn't supported on R-Car E3
On 5/9/19 10:18 PM, Joe Hershberger wrote:
> On Thu, May 9, 2019 at 3:01 PM Marek Vasut wrote:
>>
>> On 5/9/19 8:56 PM, Joe Hershberger wrote:
>>> On Wed, May 1, 2019 at 5:36 PM Marek Vasut wrote:
According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the
TX clock
Convert 'dw_spi_ofdata_to_platdata' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR.
Signed-off-by: Simon Goldschmidt
---
drivers/spi/designware_spi.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git
Convert 'cadence_spi_ofdata_to_platdata' to use dev_read_* functions to
read driver parameters and 'dev_read_first_subnode'/'ofnode_read_*' to
read flash (child node) parameters.
Tested on socfpga_socrates (socfpga gen5).
Signed-off-by: Simon Goldschmidt
---
drivers/spi/cadence_qspi.c | 39
Convert 'gpio_dwapb_bind' to iterate over subnodes using livetree
functions (inspired from mt7621_gpio.c).
Signed-off-by: Simon Goldschmidt
---
drivers/gpio/dwapb_gpio.c | 25 +++--
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/gpio/dwapb_gpio.c
Convert 'socfpga_reset_probe' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int'.
Signed-off-by: Simon Goldschmidt
---
drivers/reset/reset-socfpga.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index
The dw-apb timer does not use 'gd', so remove its declaration.
Signed-off-by: Simon Goldschmidt
---
drivers/timer/dw-apb-timer.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c
index cb48801af1..86312b8dc7 100644
---
Convert 'altera_uart_ofdata_to_platdata' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR.
Signed-off-by: Simon Goldschmidt
---
drivers/serial/altera_uart.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
This series converts (hopefully) all drivers used in socfpga to livetree
so that none of them references 'gd' any more (with the exception of
some a10/s10 drivers that should be fixed).
Simon Goldschmidt (6):
timer: dw-apb: remove unused DECLARE_GLOBAL_DATA_PTR
spi: cadence_qspi: convert to
On Wed, Apr 17, 2019 at 4:02 AM Yinbo Zhu wrote:
>
> From: Yinbo Zhu
>
> At present the MMC subsystem maintains its own list
> of MMC devices. This cannot work with driver model
> when CONFIG_BLK is enabled, use blk_dread to
> replace previous mmc read interface,
>
> Signed-off-by: Yinbo Zhu
>
On 5/9/19 8:56 PM, Joe Hershberger wrote:
> On Wed, May 1, 2019 at 5:36 PM Marek Vasut wrote:
>>
>> According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the
>> TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3
>> (r8a77995).
>>
>> Avoid setting the
When not using DM_ETH, these PHY settings are programmed with default
values hardcoded into the driver. When using DM_ETH, they should come
from the device tree. However, if the device tree does not have the
properties, the driver will silent use -1. Which is entirely out of
range, programs
These are standard across gigabit phys. These mostly extend the
auto-negotiation information with gigabit fields.
Signed-off-by: Trent Piepho
---
cmd/mii.c | 34 +-
1 file changed, 29 insertions(+), 5 deletions(-)
diff --git a/cmd/mii.c b/cmd/mii.c
index
Share the code that prints out a register field with the function that
prints out the "special" fields.
There were two arrays the register dump list, one with reg number and
name, another with a pointer to the field table and the table size.
These two arrays had have each entry match what
Am 09.05.2019 um 21:13 schrieb Wolfgang Grandegger:
Hello Simon,
Am 09.05.19 um 20:42 schrieb Simon Goldschmidt:
This fixes 3 boards that don't use CONFIG_EXTRA_ENV_SETTINGS from
socfpga_common.h. They need to enable reset manager compatibility
mode unless all peripheral drivers in Linux
Hello Simon,
Am 09.05.19 um 20:42 schrieb Simon Goldschmidt:
> This fixes 3 boards that don't use CONFIG_EXTRA_ENV_SETTINGS from
> socfpga_common.h. They need to enable reset manager compatibility
> mode unless all peripheral drivers in Linux support reset handling.
>
> Fixes: commit
On Wed, May 1, 2019 at 5:36 PM Marek Vasut wrote:
>
> According to the R-Car Gen3 Hardware Manual Rev 1.50 of Nov 30, 2018, the
> TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) or D3
> (r8a77995).
>
> Avoid setting the APSR:TDM bit on these SoCs. Moreover, only set APSR:TDM
>
On 09.05.19 20:08, Simon Goldschmidt wrote:
This adds a UCLASS_SYSRESET sysreset driver for socfgpa gen5.
Signed-off-by: Simon Goldschmidt
---
Changes in v3:
- moved socfpga gen5 sysreset driver to extra patch
Changes in v2: None
drivers/sysreset/Kconfig| 7
On Tue, Apr 30, 2019 at 11:04 AM Bartosz Golaszewski wrote:
>
> From: Bartosz Golaszewski
>
> Add support for CONFIG_DM_ETH to the davinci_emac driver. Optimally
> we should only support DM-enabled platforms but there are several
> non-DT boards that still use it so either we need to keep
This fixes 3 boards that don't use CONFIG_EXTRA_ENV_SETTINGS from
socfpga_common.h. They need to enable reset manager compatibility
mode unless all peripheral drivers in Linux support reset handling.
Fixes: commit 4b2e32efa4e7 ("arm: socfpga: gen5: deassert peripheral reset by
default")
âFrom: Markus Klotzbuecher
User-Agent: Mutt/1.10.1 (2018-07-13)
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This adds a UCLASS_SYSRESET sysreset driver for socfgpa gen5.
Signed-off-by: Simon Goldschmidt
---
Changes in v3:
- moved socfpga gen5 sysreset driver to extra patch
Changes in v2: None
drivers/sysreset/Kconfig| 7
drivers/sysreset/Makefile | 1 +
This adds a define for the bit in rstmgr's ctrl regiser that issues
a cold reset (we had a define for the warm reset bit only) in preparation
for a proper sysrese driver.
Signed-off-by: Simon Goldschmidt
Series changes: 2
- separate this patch to the register descriptions from the actual
This adds a UCLASS_SYSRESET sysreset driver for socfgpa stratix10.
Signed-off-by: Simon Goldschmidt
---
Changes in v3:
- moved socfpga stratix sysreset driver to extra patch
Changes in v2: None
drivers/sysreset/Kconfig| 7 ++
drivers/sysreset/Makefile | 1
This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga
to a UCLASS_SYSRESET based dm driver.
A side effect is that gen5 and a10 can now select between cold and warm
reset.
Signed-off-by: Simon Goldschmidt
---
Changes in v3:
- this patch enables the new drivers and drops the
On Thu, 2019-05-09 at 08:20 +0200, Anatolij Gustschin wrote:
> On Wed, 8 May 2019 23:30:01 +
> Trent Piepho tpie...@impinj.com wrote:
> ...
> > diff --git a/board/wandboard/wandboard.c
> > b/board/wandboard/wandboard.c
> > index 69fbc8b690..9d7a94ff9d 100644
> > ---
Andrew,
On Thu, May 09, 2019 at 12:03:31PM -0400, Andrew F. Davis wrote:
> On 5/8/19 11:52 PM, Lokesh Vutla wrote:
> >
> >
> > On 09/05/19 3:07 AM, Andreas Dannenberg wrote:
> >> The board detection scheme employed on various TI EVMs makes use of
> >> SRAM scratch space to share data read from
On Thu, May 09, 2019 at 06:05:57PM +0200, Heinrich Schuchardt wrote:
> On 5/9/19 4:16 PM, Tom Rini wrote:
> > On Thu, May 09, 2019 at 12:03:38AM +0200, Heinrich Schuchardt wrote:
> >> On 5/8/19 7:50 PM, Tom Rini wrote:
> >>> On Wed, May 08, 2019 at 07:57:57AM +0200, Heinrich Schuchardt wrote:
>
On 5/9/19 4:16 PM, Tom Rini wrote:
> On Thu, May 09, 2019 at 12:03:38AM +0200, Heinrich Schuchardt wrote:
>> On 5/8/19 7:50 PM, Tom Rini wrote:
>>> On Wed, May 08, 2019 at 07:57:57AM +0200, Heinrich Schuchardt wrote:
>>>
The following changes since commit
On 5/8/19 11:52 PM, Lokesh Vutla wrote:
>
>
> On 09/05/19 3:07 AM, Andreas Dannenberg wrote:
>> The board detection scheme employed on various TI EVMs makes use of
>> SRAM scratch space to share data read from an on-board EEPROM between
>> the different bootloading stages. Map the associated
Hello Heiko
On Thu, May 09, 2019 at 01:17:06PM +0200, Heiko Schocher wrote:
>
>Am 09.05.2019 um 10:59 schrieb Markus Klotzbuecher:
>> Hello Heiko
>>
>> On Tue, Apr 30, 2019 at 06:54:01AM +0200, Heiko Schocher wrote:
>>
>> > Am 15.04.2019 um 17:32 schrieb Markus Klotzbuecher:
>> > > From: Markus
Configuration option CONFIG_CMD_BOOTEFI_SELFTEST is useful for the
development of the UEFI sub-system. For production it is not needed.
Remove CONFIG_CMD_BOOTEFI_SELFTEST from bcm968580xref_ram_defconfig.
Suggested-by: Tom Rini
Signed-off-by: Heinrich Schuchardt
---
On Tue, May 07, 2019 at 09:04:16PM -0600, Simon Glass wrote:
> Hi Bin,
>
> On Tue, 7 May 2019 at 03:28, Bin Meng wrote:
> >
> > Hi Simon, Thierry,
> >
> > On Fri, May 3, 2019 at 12:22 AM Simon Glass wrote:
> > >
> > > Hi Thierry,
> > >
> > > On Thu, 2 May 2019 at 03:25, Thierry Reding wrote:
>
Configuration option CONFIG_CMD_BOOTEFI_SELFTEST is useful for the
development of the UEFI sub-system. For production it is not needed.
Remove CONFIG_CMD_BOOTEFI_SELFTEST from bcm963158_ram_defconfig.
Suggested-by: Tom Rini
Signed-off-by: Heinrich Schuchardt
---
On 08/05/2019 20:33, Pierre-Jean Texier wrote:
Hi Bryan,
Le 08/05/2019 à 20:14, Bryan O'Donoghue a écrit :
Reusing the loadaddr to load the boot script breaks some of the logic we
want to have around the bootscript/FIT load addresses. Making a dedicated
bootscript address allows us to
On 5/1/19 4:51 PM, Stephen Warren wrote:
On 4/30/19 10:27 AM, Marek Vasut wrote:
On 4/30/19 5:29 PM, Stephen Warren wrote:
On 4/16/19 4:04 PM, Stephen Warren wrote:
From: Stephen Warren
Fix test_mmc_dev(), test_mmc_rescan(), test_mmc_info() not to use the
same configuration data that
On Thu, May 09, 2019 at 05:12:25PM +0200, Marek Vasut wrote:
> On 5/9/19 5:03 PM, Vasily Khoruzhick wrote:
> > On Thu, May 9, 2019 at 7:56 AM Marek Vasut wrote:
> >>
> >> On 5/9/19 4:02 PM, Tom Rini wrote:
> >>> On Mon, May 06, 2019 at 09:26:04AM -0400, Tom Rini wrote:
> >>>
> Hey folks,
>
On 5/9/19 5:03 PM, Vasily Khoruzhick wrote:
> On Thu, May 9, 2019 at 7:56 AM Marek Vasut wrote:
>>
>> On 5/9/19 4:02 PM, Tom Rini wrote:
>>> On Mon, May 06, 2019 at 09:26:04AM -0400, Tom Rini wrote:
>>>
Hey folks,
I'm attempting, again, to see what we need to do in order to use
On Thu, May 9, 2019 at 7:56 AM Marek Vasut wrote:
>
> On 5/9/19 4:02 PM, Tom Rini wrote:
> > On Mon, May 06, 2019 at 09:26:04AM -0400, Tom Rini wrote:
> >
> >> Hey folks,
> >>
> >> I'm attempting, again, to see what we need to do in order to use gcc-8.x
> >> for U-Boot and ran into, again:
> >>
On 5/9/19 4:02 PM, Tom Rini wrote:
> On Mon, May 06, 2019 at 09:26:04AM -0400, Tom Rini wrote:
>
>> Hey folks,
>>
>> I'm attempting, again, to see what we need to do in order to use gcc-8.x
>> for U-Boot and ran into, again:
>> https://patchwork.ozlabs.org/patch/920329/ which in short is that
On Thu, May 09, 2019 at 12:03:38AM +0200, Heinrich Schuchardt wrote:
> On 5/8/19 7:50 PM, Tom Rini wrote:
> >On Wed, May 08, 2019 at 07:57:57AM +0200, Heinrich Schuchardt wrote:
> >
> >>The following changes since commit
> >>44237e272f1eac3b026709e76333a07b2d3a3523:
> >>
> >>Merge branch 'master'
LS1046AFRWY board supports LS1046A family SoCs. This patch
add base support for this board.
Board support's 4GB ddr memory, i2c, micro-click module,microSD card,
serial console,qspi nor flash,ifc nand flash,qsgmii network interface,
usb 3.0 and serdes interface to support two x1gen3 pcie
Acked-by: Sylvain Lemieux
On Tue, Apr 30, 2019 at 4:48 PM Vladimir Zapolskiy wrote:
>
> Hi Jagan,
>
> On 04/28/2019 11:48 PM, Jagan Teki wrote:
> > Mark LPC32XX_SSP has BROKEN, this so the resulting build shows
> > warning for broken configuration enabled and associated code
> > will remove in
On Mon, May 06, 2019 at 09:26:04AM -0400, Tom Rini wrote:
> Hey folks,
>
> I'm attempting, again, to see what we need to do in order to use gcc-8.x
> for U-Boot and ran into, again:
> https://patchwork.ozlabs.org/patch/920329/ which in short is that when
> using -mcpu=xscale gcc-8.x throws an
Hi Philipp,
On Thu, May 9, 2019 at 6:10 PM Philipp Tomsich
wrote:
>
> Jagan,
>
> On 09.05.2019, at 14:36, Jagan Teki wrote:
>
> On Thu, May 9, 2019 at 6:01 PM Paul Kocialkowski
> wrote:
>
>
> Hi,
>
> On Thu, 2019-05-09 at 16:15 +0530, Jagan Teki wrote:
>
> Hi Paul,
>
> On Thu, May 9, 2019 at
Hi,
On Thu, 2019-05-09 at 14:40 +0200, Philipp Tomsich wrote:
> Jagan,
>
> > On 09.05.2019, at 14:36, Jagan Teki wrote:
> >
> > On Thu, May 9, 2019 at 6:01 PM Paul Kocialkowski
> > wrote:
> > > Hi,
> > >
> > > On Thu, 2019-05-09 at 16:15 +0530, Jagan Teki wrote:
> > > > Hi Paul,
> > > >
> >
On 09.05.2019 02:05, Vladimir Oltean wrote:
> On 5/9/19 1:55 AM, Tom Rini wrote:
>> On Wed, May 08, 2019 at 10:52:28PM +, Vladimir Oltean wrote:
>>> On 5/9/19 1:48 AM, Tom Rini wrote:
On Wed, May 08, 2019 at 10:45:50PM +, Vladimir Oltean wrote:
> On 5/9/19 1:42 AM, Tom Rini wrote:
On Thu, May 9, 2019 at 6:09 PM Paul Kocialkowski
wrote:
>
> On Thu, 2019-05-09 at 18:06 +0530, Jagan Teki wrote:
> > On Thu, May 9, 2019 at 6:01 PM Paul Kocialkowski
> > wrote:
> > > Hi,
> > >
> > > On Thu, 2019-05-09 at 16:15 +0530, Jagan Teki wrote:
> > > > Hi Paul,
> > > >
> > > > On Thu, May
Jagan,
> On 09.05.2019, at 14:36, Jagan Teki wrote:
>
> On Thu, May 9, 2019 at 6:01 PM Paul Kocialkowski
> mailto:paul.kocialkow...@bootlin.com>> wrote:
>>
>> Hi,
>>
>> On Thu, 2019-05-09 at 16:15 +0530, Jagan Teki wrote:
>>> Hi Paul,
>>>
>>> On Thu, May 9, 2019 at 12:38 PM Paul Kocialkowski
On Thu, 2019-05-09 at 18:06 +0530, Jagan Teki wrote:
> On Thu, May 9, 2019 at 6:01 PM Paul Kocialkowski
> wrote:
> > Hi,
> >
> > On Thu, 2019-05-09 at 16:15 +0530, Jagan Teki wrote:
> > > Hi Paul,
> > >
> > > On Thu, May 9, 2019 at 12:38 PM Paul Kocialkowski
> > > wrote:
> > > > Hi,
> > > >
>
On Thu, May 9, 2019 at 6:01 PM Paul Kocialkowski
wrote:
>
> Hi,
>
> On Thu, 2019-05-09 at 16:15 +0530, Jagan Teki wrote:
> > Hi Paul,
> >
> > On Thu, May 9, 2019 at 12:38 PM Paul Kocialkowski
> > wrote:
> > > Hi,
> > >
> > > On Wed, 2019-05-08 at 11:11 +0530, Jagan Teki wrote:
> > > > (Sorry for
Hi,
On Thu, 2019-05-09 at 16:15 +0530, Jagan Teki wrote:
> Hi Paul,
>
> On Thu, May 9, 2019 at 12:38 PM Paul Kocialkowski
> wrote:
> > Hi,
> >
> > On Wed, 2019-05-08 at 11:11 +0530, Jagan Teki wrote:
> > > (Sorry for the noice, I have missed to send two patches from v7)
> > >
> > > This is v7
Hi Ajay,
On 09/05/2019 13:26, Ajay Kaher wrote:
>
>
> On 25/04/19, 7:07 PM, "Tom Rini" wrote:
>
>> On Thu, Apr 25, 2019 at 01:13:24PM +, Ajay Kaher wrote:
>> >
>> > Tom, [PATCH v2 1/2] reviewed by 'Matthias Brugger'.
>> > But no update on [Patch v2 2/2] (includes changes in
>>
On 25/04/19, 7:07 PM, "Tom Rini" wrote:
> On Thu, Apr 25, 2019 at 01:13:24PM +, Ajay Kaher wrote:
> >
> > Tom, [PATCH v2 1/2] reviewed by 'Matthias Brugger'.
> > But no update on [Patch v2 2/2] (includes changes in include/configs/rpi.h)
>
> Since Matthias is the Pi custodian,
On Thu, May 09, 2019 at 12:15:34AM +0200, Graf, Alexander wrote:
>
> On 09.05.19 00:03, Heinrich Schuchardt wrote:
> >On 5/8/19 7:50 PM, Tom Rini wrote:
> >>On Wed, May 08, 2019 at 07:57:57AM +0200, Heinrich Schuchardt wrote:
> >>
> >>>The following changes since commit
>
Hello Andreas,
Am 08.05.2019 um 23:37 schrieb Andreas Dannenberg:
From: Vignesh R
There is no need for to include this header here, so drop it.
Signed-off-by: Vignesh R
---
arch/arm/include/asm/omap_i2c.h | 2 --
1 file changed, 2 deletions(-)
Reviewed-by: Heiko Schocher
bye,
Heiko
Hello Andreas,
Am 08.05.2019 um 23:37 schrieb Andreas Dannenberg:
From: Vignesh R
K3 devices have I2C IP that is same as OMAP2+ family. Allow driver to be
compiled for ARCH_K3.
Signed-off-by: Vignesh R
Signed-off-by: Andreas Dannenberg
---
drivers/i2c/Kconfig | 2 +-
1 file changed, 1
Hello Markus,
Am 09.05.2019 um 10:59 schrieb Markus Klotzbuecher:
Hello Heiko
On Tue, Apr 30, 2019 at 06:54:01AM +0200, Heiko Schocher wrote:
Am 15.04.2019 um 17:32 schrieb Markus Klotzbuecher:
From: Markus Klotzbuecher
please add a commit message.
Signed-off-by: Markus Klotzbuecher
On Thu, May 9, 2019 at 5:33 AM Peng Fan wrote:
>
> Without this definition, fsl_esdhc will access reserved registers
> on i.MX chips, so define ARCH_MXC to fix it.
>
> Signed-off-by: Peng Fan
Reviewed-by: Fabio Estevam
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On Thu, May 9, 2019 at 5:33 AM Peng Fan wrote:
>
> imx-regs.h under arch-imx has no user, drop it.
>
> Signed-off-by: Peng Fan
Reviewed-by: Fabio Estevam
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This patch add documentation for TPL build and flashing steps
for rk3399 boards.
Add full boot log for future reference.
Signed-off-by: Jagan Teki
---
doc/README.rockchip | 51 -
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git
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