Hello Michael,
On 02.03.22 16:56, Michael Opdenacker wrote:
> - Grammar fixes
> - Clarify explanations
>
> Signed-off-by: Michael Opdenacker
> ---
> doc/README.bootcount | 34 ++
> drivers/bootcount/Kconfig | 10 +-
> 2 files changed, 23
Hello Marek,
On 16.02.22 15:27, Marek Vasut wrote:
> With DM I2C, the EEPROM bus has been correctly configured in
> eeprom_execute_command() already. Do not reconfigure it here
> with hard-coded bus number again.
>
> Signed-off-by: Marek Vasut
> Cc: Heiko Schocher
> Cc: Tom Rini
> ---
>
Hello Nikita,
On 15.02.22 18:58, Nikita Yushchenko wrote:
> Per dm_i2c_ops.probe_chip documentation, i2c_probe_chip() shall fallback
> to default probe method when .probe_chip() returns -ENOSYS.
>
> Signed-off-by: Nikita Yushchenko
> ---
> drivers/i2c/i2c-uclass.c | 2 +-
> 1 file changed, 1
On 3/22/22 17:17, Marek Behún wrote:
From: Marek Behún
Commit 0934dddc6436 ("arm: a37xx: Update DTS files to version from
upstream Linux kernel") ported Linux's device-tree files for Armada 3720
SOCs. This broke USB port on Turris MOX, because in Linux' DTS the bus
voltage supply is described
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.
Signed-off-by: Stanley Chu
---
v3:
- separate group names and function names in different tables
to allow for adding additional functions
v2:
- drop the WDnRCRB/CORSTCB register access, it is not for
GPIO modules reset control
---
Hi Michael
thanks for your reply.
the wdt design of npcm750 and npcm845 is the same.
so the driver can work on npcm750 and npcm845.
about the npcm845 wdt dtsi , i will followed kernel upstream name and
use nuvoton,npcm750-wdt.
i think the v6 version is better for now.
should i use v6 patch to
Hi Marek,
On Mon, 2022-03-21 at 15:59 +0100, Marek Vasut wrote:
> Caution: EXT Email
>
> On 3/21/22 04:35, Ye Li wrote:
> >
> > Hi Marek,
> Hi,
>
> >
> > >
> > > diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-
> > > imx/spl_imx_romapi.c
> > > index d827de375a6..c47f5a6bdb4
Hi:
I had a custom AM335X board connected my computer by usbnet. It always report
data abort when 'dhcp':
Next it the log:
U-Boot 2022.01-rc1-00183-gfa5b4e2d19-dirty (Feb 25 2022 - 15:45:02 +0800)
CPU : AM335X-GP rev 2.1
Model: WISDOM AM335X CCT
DRAM: 512 MiB
NAND: 256 MiB
MMC: OMAP
Hi Tim,
On Tue, Mar 22, 2022 at 3:42 PM Tim Harvey wrote:
>
> Enable ONFI detection to fix NAND chip configuration. Without this
> the NAND oobsize will be wrong which leads to invalid ECC strength and
> incompatibility with the previous configuration.
>
> Fixes: 777f333c375a ("imx: ventana:
Greetings,
I'm working on adding board support for an imx8mp SoC board which uses
the EQoS MAC interface. I'm finding that eqos_start() fails with
'EQOS_DMA_MODE_SWR stuck'. I believe this is likely a clock issue but
not clear what it could be that isn't properly defined in imx8mp.dtsi.
Any
On 3/22/22 6:11 PM, Heinrich Schuchardt wrote:
> On 3/22/22 21:59, Sean Anderson wrote:
>> This cleans up the semihosting code and adds the following new features:
>>
>> - hostfs support (like sandbox)
>> - support for being used as a SPL boot device
>> - serial device support
>> - falling back
On 3/22/22 6:05 PM, Heinrich Schuchardt wrote:
> On 3/22/22 21:59, Sean Anderson wrote:
>> This converts the semihosting readme to rST. I have tried to make only
>> cosmetic changes, but I did fix up the first link (which was broken).
>>
>> Signed-off-by: Sean Anderson
>> ---
>>
>> (no changes
On Tue, Mar 22, 2022 at 11:33:20PM +0100, Heinrich Schuchardt wrote:
> On 3/22/22 23:16, Tom Saeger wrote:
> > On Tue, Mar 22, 2022 at 10:41:40PM +0100, Heinrich Schuchardt wrote:
> > > On 3/22/22 22:21, Tom Saeger wrote:
> > > > Since be66b89da306 ("efi_loader: configuration of variables store")
On Tue, Mar 22, 2022 at 10:41:40PM +0100, Heinrich Schuchardt wrote:
> On 3/22/22 22:21, Tom Saeger wrote:
> > Since be66b89da306 ("efi_loader: configuration of variables store")
> > the choice of EFI_VARIABLE_FILE_STORE or EFI_MM_COMM_TEE
> > is mutually-exclusive, however efi_var_to_file also
On 3/22/22 23:16, Tom Saeger wrote:
On Tue, Mar 22, 2022 at 10:41:40PM +0100, Heinrich Schuchardt wrote:
On 3/22/22 22:21, Tom Saeger wrote:
Since be66b89da306 ("efi_loader: configuration of variables store")
the choice of EFI_VARIABLE_FILE_STORE or EFI_MM_COMM_TEE
is mutually-exclusive,
On Tue, Mar 22, 2022 at 10:09:38PM +0100, Heinrich Schuchardt wrote:
> On 3/22/22 14:18, Daniel Golle wrote:
> > Hi Heinrich,
> >
> > On Tue, Mar 22, 2022 at 09:29:54AM +0100, Heinrich Schuchardt wrote:
> > > On 3/22/22 00:22, Daniel Golle wrote:
> > > > It can be useful for the OS (Linux) to
On 3/22/22 21:59, Sean Anderson wrote:
This cleans up the semihosting code and adds the following new features:
- hostfs support (like sandbox)
- support for being used as a SPL boot device
- serial device support
- falling back to normal drivers if semihosting is disabled
The main device
Since be66b89da306 ("efi_loader: configuration of variables store")
the choice of EFI_VARIABLE_FILE_STORE or EFI_MM_COMM_TEE
is mutually-exclusive, however efi_var_to_file also allows
for "neither". Set Kconfig choice optional.
Signed-off-by: Tom Saeger
---
lib/efi_loader/Kconfig | 1 +
1 file
On 3/22/22 21:59, Sean Anderson wrote:
This converts the semihosting readme to rST. I have tried to make only
cosmetic changes, but I did fix up the first link (which was broken).
Signed-off-by: Sean Anderson
---
(no changes since v1)
doc/usage/index.rst | 1 +
On 3/22/22 22:21, Tom Saeger wrote:
Since be66b89da306 ("efi_loader: configuration of variables store")
the choice of EFI_VARIABLE_FILE_STORE or EFI_MM_COMM_TEE
is mutually-exclusive, however efi_var_to_file also allows
for "neither". Set Kconfig choice optional.
Signed-off-by: Tom Saeger
---
On 3/16/22 04:03, Simon Glass wrote:
This is an attempt to cover the common cases found when enabling driver
model for serial on a new board.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add an example patch
- Mention removing old code that is not used
Hi Stefan,
I did a review for the Kirkwood boards regarding the
CONFIG_RESET_PHY_R usage. Here is my finding, and also a suggestion
below to go forward with the conflict patches.
There are about 25 out of the total of 33 Kirkwood boards that either
use CONFIG_RESET_PHY_R to invoke reset_phy(),
This adds a test to ensure that puts is equivalent to putc called in a
loop. We don't verify the contents of the message to avoid having to
record console output a second time (though that could be added in the
future). The globals are initialized to non-zero values to avoid a
warning; in
This imports some defines for esr and spsr from Linux v5.16. I have
modified the includes and fixed some indentation nits but otherwise it
is the same. There are a lot more defines than we need, but it doesn't
hurt.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- New
To avoid passing around an extra register everywhere, save esr in
pt_regs like the rest. For proper alignment we need to have a second
(unused) register. All the printfs have to be adjusted, since
it's now an unsigned long and not an int.
Signed-off-by: Sean Anderson
---
(no changes since v2)
This adds support for booting entirely from JTAG while using a
hard-coded RCW. With these steps, it is not necessary to program a
"good" RCW using CodeWarrior. The method here can be performed with any
JTAG adapter supported by OpenOCD, including the on-board CMSIS-DAP
(albeit very slowly).
These
On 3/22/22 14:18, Daniel Golle wrote:
Hi Heinrich,
On Tue, Mar 22, 2022 at 09:29:54AM +0100, Heinrich Schuchardt wrote:
On 3/22/22 00:22, Daniel Golle wrote:
It can be useful for the OS (Linux) to know which configuration has
been chosen by U-Boot when launching a FIT image.
Store the name of
This adds a filesystem which is backed by the host's filesystem. It is
modeled off of sandboxfs, which has very similar aims. Semihosting
doesn't support listing directories (except with SYS_SYSTEM), so neither
do we. it's possible to optimize a bit for the common case of reading a
whole file by
Some serial drivers can be vastly more efficient when printing multiple
characters at once. Non-DM serial has had a puts option for these sorts
of drivers; implement it for DM serial as well.
Because we have to add carriage returns, we can't just pass the whole
string directly to the serial
This documents how to use semihosting, the new semihosting features, and
how to migrate from smhload.
Signed-off-by: Sean Anderson
---
Changes in v3:
- Add additional documentation for QEMU and OpenOCD
- Add dummy device number for hostfs
Changes in v2:
- Add migration instructions for smhload
This implements puts for sandbox. It is fairly straightforward, except
that we break out the shared color printing functionality into its own
function.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- New
drivers/serial/Kconfig | 1 +
drivers/serial/sandbox.c | 21
This register holds "pstate" which includes (among other things) the
instruction mode the CPU was in when the exception was taken. This is
necessary to correctly interpret instructions at elr.
Signed-off-by: Sean Anderson
---
Changes in v3:
- Fix loading the wrong EL's SPSR
Changes in v2:
-
This adds an implementation of puts for DM. The implementation is not as
clean as for the non-DM puts because we have to handle non-nul-terminated
string. We also handle short writes (though these are probably very
unusual).
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
Use the semihosting_enabled function to determine whether or not to
enable semihosting devices. This allows for graceful fallback in the
event a debugger is not attached.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- New
arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3
If semihosting is disabled, then the user has no debugger attached, and
will not see any messages. Don't create a serial device in this
instance, to (hopefully) fall back on another working serial device.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- New
If a debugger is not attached to U-Boot, semihosting calls will raise a
synchronous abort exception. Try to catch this and disable semihosting
so we can e.g. use another uart if one is available. In the immediate
case, we return an error, since it is not always possible to check for
semihosting
These functions are intended to support detecting semihosting and
falling back gracefully to alternative implementations. The test starts
by making semihosting call. SYS_ERRNO is chosen because it should not
mutate any state. If this semihosting call results in an exception
(rather than being
This adds a serial driver which uses semihosting calls to read and write
to the host's console. For convenience, if CONFIG_DM_SERIAL is enabled,
we will instantiate a serial driver. This allows users to enable this
driver (which has no physical device) without modifying their device
trees or board
This adds three wrappers around the semihosting commands for reading and
writing to the host console. We use the more standard getc/putc/puts
names instead of readc/writec/write0 for familiarity.
Signed-off-by: Sean Anderson
---
(no changes since v1)
arch/arm/lib/semihosting.c | 18
This command's functionality is now completely implemented by the
standard fs load command. Convert the vexpress64 boot command (which is
the only user) and remove the implementation.
Signed-off-by: Sean Anderson
---
Changes in v3:
- Add dummy device number for hostfs
Changes in v2:
- Rebase
Most U-Boot command deal with start/size instead of start/end. Convert
the "fdt chosen" command to use these semantics as well. The only user
of this subcommand is vexpress, so convert the smhload command to use
this as well. We don't bother renaming the variable in vexpress64's
bootcommand, since
In order to add filesystem support, we will need to be able to seek and
write files. Add the appropriate helper functions.
Signed-off-by: Sean Anderson
---
(no changes since v1)
arch/arm/lib/semihosting.c | 67 +++---
include/semihosting.h | 20
This adds a boot method for loading the next stage from the host. It is
mostly modeled off of spl_load_image_ext. I am not really sure why/how
spl_load_image_fat uses three different methods to load the image, but
the simple case seems to work OK for now.
To control the presence of this boot
This adds some documentation for semihosting functions in the header.
Signed-off-by: Sean Anderson
---
(no changes since v1)
arch/arm/lib/semihosting.c | 9 -
include/semihosting.h | 32
2 files changed, 32 insertions(+), 9 deletions(-)
diff
There's no point in using string constants for smh_open if we are just
going to have to parse them. Instead, use numeric modes. The user needs
to be a bit careful with these, since they are much closer semantically
to string modes used by fopen(3) than the numeric modes used with
open(2).
Instead of printing in what are now library functions, try to return a
numeric error code. This also adjust some functions (such as read) to
behave more similarly to read(2). For example, we now return the number
of bytes read instead of failing immediately on a short read.
Signed-off-by: Sean
This exports semihosting functions for use in other files. The header is
in include/ and not arm/include/asm because I anticipate that RISC-V may
want to add their own implementation at some point.
smh_len_fd has been renamed to smh_flen to more closely match the
semihosting spec.
Signed-off-by:
These files are spread all over the tree, so just use a regex. Orphaned
for now, since this is more of a "one-off" series. Though I'll be happy
to review patches.
Signed-off-by: Sean Anderson
---
Liviu or Andre, perhaps you should be listed here as well?
(no changes since v2)
Changes in v2:
-
This adds some instructions for enabling the debug uart, including the
correct address and clock rate.
Signed-off-by: Sean Anderson
---
(no changes since v2)
Changes in v2:
- New
doc/board/nxp/ls1046ardb.rst | 9 +
1 file changed, 9 insertions(+)
diff --git
This converts the readme for this board to rST. I have tried not to
change any semantics from the original (though I did convert MB to M).
Signed-off-by: Sean Anderson
---
(no changes since v1)
board/freescale/ls1046ardb/MAINTAINERS | 1 +
board/freescale/ls1046ardb/README | 76
This cleans up the semihosting code and adds the following new features:
- hostfs support (like sandbox)
- support for being used as a SPL boot device
- serial device support
- falling back to normal drivers if semihosting is disabled
The main device affected by these changes is vexpress64, so
This adds some additional info about booting from different sources,
including the correct switch positions.
Signed-off-by: Sean Anderson
---
(no changes since v1)
doc/board/nxp/ls1046ardb.rst | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git
This converts the semihosting readme to rST. I have tried to make only
cosmetic changes, but I did fix up the first link (which was broken).
Signed-off-by: Sean Anderson
---
(no changes since v1)
doc/usage/index.rst | 1 +
.../semihosting.rst}
initrddump.efi uses colored output and clear the screen. This is not
helpful for integration into Python tests. Allow specifying 'nocolor' in
the load option data to suppress color output and clearing the screen.
Signed-off-by: Heinrich Schuchardt
---
v3:
new patch
---
Provide a unit test for
* efidebug boot add
* efidebug bootmgr
* initrd via EFI_LOAD_FILE2_PROTOCOL
Signed-off-by: Heinrich Schuchardt
---
v3:
pass u"nocolor" as optional data to initrddump.efi
v2:
new patch
---
test/py/tests/test_efi_bootmgr/conftest.py| 42
A unit test for the boot manager is provided.
In the test a disk images is prepared and bound as device in the sandbox.
intrddump.efi is run as boot binary. The CRC32 of the initrd image
presented via the EFI_LOAD_FILE2_PROTOCOL is checked.
The initrddump.efi application is adjusted to better
Up to now the initrddump.efi application has drained the input after
showing the prompt. This works for humans but leads to problems when
automating testing. If the input is drained, this should be done before
showing the prompt.
Signed-off-by: Heinrich Schuchardt
---
v3:
new patch
---
On 3/17/22 1:39 PM, Pierre-Clément Tosi wrote:
> On Wed, Mar 16, 2022 at 03:47:57PM -0400, Sean Anderson wrote:
>> On 3/16/22 11:39 AM, Pierre-Clément Tosi wrote:
>> > Import the header from version 5.16 of the kernel:
>> >
>> > commit df0cc57e057f18e44dac8e6c18aba47ab53202f9
>> >
>> >
On 2022-03-22 06:49, Adam Ford wrote:
On Tue, Mar 22, 2022 at 8:02 AM Angus Ainslie wrote:
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
driver.
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to
common place")
I did a clk dump before this series
On Mon, Mar 21, 2022 at 1:37 PM Han Xu wrote:
>
> The code change fixed the kernel gpmi bch setting not aligned with
> u-boot settings issue. It still uses the legacy bch geometry as the
> default option. If users need to choose the minimum ecc strength that
> NAND chips required, it can be
Enable ONFI detection to fix NAND chip configuration. Without this
the NAND oobsize will be wrong which leads to invalid ECC strength and
incompatibility with the previous configuration.
Fixes: 777f333c375a ("imx: ventana: enable dm for MTD and NAND")
Signed-off-by: Tim Harvey
---
On Tue, Mar 22, 2022 at 10:13 AM Tim Harvey wrote:
>
> On Mon, Mar 21, 2022 at 12:42 PM Tim Harvey wrote:
> >
> > On Mon, Mar 21, 2022 at 1:34 AM Frieder Schrempf
> > wrote:
> > >
> > > Hi Ye,
> > >
> > > Am 17.03.22 um 14:54 schrieb Frieder Schrempf:
> > > > Hi Han,
> > > >
> > > > Am 17.03.22
On Mon, Mar 21, 2022 at 12:42 PM Tim Harvey wrote:
>
> On Mon, Mar 21, 2022 at 1:34 AM Frieder Schrempf
> wrote:
> >
> > Hi Ye,
> >
> > Am 17.03.22 um 14:54 schrieb Frieder Schrempf:
> > > Hi Han,
> > >
> > > Am 17.03.22 um 14:33 schrieb Han Xu:
> > >>
> > >>
> > >> On Thu, Mar 17, 2022 at 8:27
As explained in commit 4af2a33ee5b9 ("cmd: gpio: Make `gpio input`
return pin value again") the `gpio input` is used in scripts to obtain
the value of a pin, despite the fact that CMD_RET_FAILURE is
indistinguishable from a valid pin value.
To be able to detect failures and properly use the value
From: Marek Behún
Commit 0934dddc6436 ("arm: a37xx: Update DTS files to version from
upstream Linux kernel") ported Linux's device-tree files for Armada 3720
SOCs. This broke USB port on Turris MOX, because in Linux' DTS the bus
voltage supply is described as a `phy-supply` property of connector
Since the commit bfaa51dd4adf ("cmd: add serial console support
for the cls command") the cls command is not enough to clear the
video display when ANSI console is activated.
This patch clears the video device with the video_clear() API
before to display the bitmap used for the PXE background.
Hi,
On 3/22/22 15:10, Patrick Delaunay wrote:
Since the commit bfaa51dd4adf ("cmd: add serial console support
for the cls command") the cls command is not enough to clear the
video display when ANSI console is activated.
This patch clears the video device with the video_clear() API
before to
From: Luca Ellero
Take as reference Linux kernel code:
drivers/gpio/gpio-pca953x.c
Signed-off-by: Luca Ellero
---
drivers/gpio/pca953x_gpio.c | 50 +
1 file changed, 40 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/pca953x_gpio.c
On 3/22/22 15:06, Patrick Delaunay wrote:
Add driver for OP-TEE based Random Number Generator on ARM SoCs
where hardware entropy sources are not accessible to normal world
and the RNG service is provided by a HWRNG Trusted Application (TA).
This driver is based on the linux driver:
Hi,
On 3/22/22 07:11, Dominic Rath wrote:
> The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect
> the maximum possible SDRAM of 2 GB for AM64x (instead of the register's
> default that says 8 GB, which the AM64x DDR controller wouldn't support).
>
> The offset 0x20 was
Hi,
On 3/22/22 07:11, Dominic Rath wrote:
> The K3 DDRSS used by AM64x and J721e (and probably J7200 in the future)
> used to define only two register ranges: one labeled "cfg" that was
> internally referenced as "DDRSS wrapper", and the LPDDR4 FSP handshake
> registers in the CTRL_MMR register
Since the commit bfaa51dd4adf ("cmd: add serial console support
for the cls command") the cls command is not enough to clear the
video display when ANSI console is activated.
This patch clears the video device with the video_clear() API
before to display the bitmap used for the PXE background.
In U-Boot, the discovery of TA based on its UUID on the TEE bus is
not supported.
This patch only binds the driver associated to the new supported
OP-TEE TA = TA_HWRNG when this driver is enable.
Signed-off-by: Patrick Delaunay
---
drivers/tee/optee/core.c | 13 +
1 file changed,
When the RNG device is secured with OP-TEE, it is only accessible with
the HWRNG TA, the CONFIG_RNG_OPTEE is needed for STM32MP15 targets
with OP-TEE support.
The probe of this RNG driver fails when the TA is not available in OP-TEE
and the previous driver can be used, as CONFIG_RNG_STM32MP1 is
Add driver for OP-TEE based Random Number Generator on ARM SoCs
where hardware entropy sources are not accessible to normal world
and the RNG service is provided by a HWRNG Trusted Application (TA).
This driver is based on the linux driver: char/hw_random/optee-rng.c
Signed-off-by: Patrick
On Tue, Mar 22, 2022 at 8:02 AM Angus Ainslie wrote:
>
> Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
> driver.
>
> 43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common
> place")
>
I did a clk dump before this series and after this series then
Hi Heinrich,
On Tue, Mar 22, 2022 at 09:29:54AM +0100, Heinrich Schuchardt wrote:
> On 3/22/22 00:22, Daniel Golle wrote:
> > It can be useful for the OS (Linux) to know which configuration has
> > been chosen by U-Boot when launching a FIT image.
> > Store the name of the FIT configuration node
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock
driver.
43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common
place")
Signed-off-by: Angus Ainslie
---
drivers/clk/imx/clk-imx8mm.c | 60 +++-
drivers/clk/imx/clk-imx8mn.c
This is a DM clock driver based off the imx8mm u-boot driver and the linux
kernel driver.
All of the PLLs and clocks are initialized so the subsystems below are
functional and tested.
1) USB host and peripheral
2) ECSPI
3) UART
4) I2C all busses
5) USDHC for eMMC support
6) USB storage
7) GPIO
Sync the clock ids with the mainline kernel
077de6e1c9f ("clk: imx8mq: add PLL monitor output")
Signed-off-by: Angus Ainslie
Reviewed-by: Marek Vasut
---
include/dt-bindings/clock/imx8mq-clock.h | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git
This is a DM clock driver for the imx8mq based on the linux kernel
driver and the u-boot imx8mm clock driver.
It also removes some code duplication in the imx8m[nmp] clock drivers.
Changes since V4
Rebased onto [1] so patch 4 of 4 was dropped.
Added CLK_COMPOSITE_CCF
Fixed const* clock
From: Haolin Li
A pointer can not be negative. Use macro IS_ERR_OR_NULL() for checking.
Signed-off-by: Haolin Li
---
drivers/mmc/rockchip_sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index
On 2022-03-21 06:50, Heiko Thiery wrote:
Hi Angus,
[snip]
> So I'm not sure if the ipg clock is the right one for the boards that
> has different clock for ipg and per.
So I only looked at imx6qdl.dtsi where the clocks are different
clocks = < IMX6QDL_CLK_UART_IPG>,
<
Le Tue, 22 Mar 2022 11:18:39 +,
a écrit :
> On 3/11/22 11:35 AM, Clément Léger wrote:
> > Enable CONFIG_ATMEL_TCB_TIMER and disable CONFIG_ATMEL_PIT_TIMER.
> > This will allow using the TCB timer instead of the PIT one when running
> > under OP-TEE.
>
> Hello Clement,
>
> We have to make
Hi Tom,
Am Di., 22. März 2022 um 13:25 Uhr schrieb Tom Rini :
>
> On Tue, Mar 22, 2022 at 10:25:12AM +0100, Heinrich Schuchardt wrote:
> > On 3/21/22 15:26, Heiko Thiery wrote:
> > > It was observed that enabling additional DM modules the configured
> > > malloc value is not sufficient. So lets
The K3 DDRSS used by AM64x and J721e (and probably J7200 in the future)
used to define only two register ranges: one labeled "cfg" that was
internally referenced as "DDRSS wrapper", and the LPDDR4 FSP handshake
registers in the CTRL_MMR register space, labeled "ctrl_mmr_lp4".
The address
The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect
the maximum possible SDRAM of 2 GB for AM64x (instead of the register's
default that says 8 GB, which the AM64x DDR controller wouldn't support).
The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG
was
On Tue, Mar 22, 2022 at 10:25:12AM +0100, Heinrich Schuchardt wrote:
> On 3/21/22 15:26, Heiko Thiery wrote:
> > It was observed that enabling additional DM modules the configured
> > malloc value is not sufficient. So lets increase the value.
> >
> > Signed-off-by: Heiko Thiery
> > ---
> > v2:
Am 2022-03-22 11:54, schrieb Andre Przywara:
On Tue, 22 Mar 2022 17:19:53 +0800
Jim Liu wrote:
Hi,
Add watchdog controller driver for NPCM7xx/npcm8xx
So this is now the same as v4, with both compatible strings listed.
Which *might* be right, but my question still stands:
Is the 845
Corstone1000 is a platform from arm, which includes pre
verified Corstone SSE710 sub-system that combines Cortex-A and
Cortex-M processors [0].
This code adds the support for the Cortex-A35 implementation
at host side, it contains also the necessary bits to support
the Corstone 1000 FVP (Fixed
cp.b is used a lot as a way to load binaries to memory and execute
them, however we may need to integrate this with the efi subsystem to
set it up as a bootdev.
So, introduce a loadm command that will be consistent with the other
loadX commands and will call the efi API's.
ex: loadm $kernel_addr
This series add support for arm's corstone1000 platform (see
specific commit changelog for references to documentation),
but first introduce a command (loadm which will integrate with
efi subsystem) used in one of the boot sequence in this
platform.
Cheers,
Rui
Rui Miguel Silva (2):
cmd:
From: Luca Ellero
NOTE: this chip uses "extened device information"
Signed-off-by: Luca Ellero
---
drivers/mtd/spi/sf_dataflash.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 351c41039a..85867817c7 100644
---
From: Luca Ellero
Take as reference Linux kernel code:
drivers/mtd/devices/mtd_dataflash.c
Signed-off-by: Luca Ellero
---
drivers/mtd/spi/sf_dataflash.c | 98 ++
1 file changed, 64 insertions(+), 34 deletions(-)
diff --git
Since AT45DB641E uses "extended device information" for reading JEDEC ID
we must first introduce support for this feature.
All code is borrowed from Linux kernel source code:
drivers/mtd/devices/mtd_dataflash.c
Luca Ellero (2):
sf: dataflash: add support for "extended ID"
sf:
On Tue, 22 Mar 2022 17:19:53 +0800
Jim Liu wrote:
Hi,
> Add watchdog controller driver for NPCM7xx/npcm8xx
So this is now the same as v4, with both compatible strings listed.
Which *might* be right, but my question still stands:
Is the 845 watchdog compatible to the 740 version? Does the
Hi Frieder,
sorry for late answer.
On 17.03.22 14:24, Frieder Schrempf wrote:
Hi Stefano,
this old patch was delegated to you in patchwork. If you're not the
correct maintainer to address, please let me know. As the NAND layer
seems to be unmaintained at the moment, I'm not sure whom to ask.
On 3/21/22 15:26, Heiko Thiery wrote:
It was observed that enabling additional DM modules the configured
malloc value is not sufficient. So lets increase the value.
Signed-off-by: Heiko Thiery
---
v2:
- add a more proper commit message to explan why the value was increased
Add watchdog controller driver for NPCM7xx/npcm8xx
Signed-off-by: Jim Liu
Reviewed-by: Stefan Roese
Reviewed-by: Simon Glass
Changes for v2:
- coding style cleanup
- change register type from struct
Changes for v3:
- remove common.h
Changes for v4:
- add a bit of detail about the
Hi Han,
On Mon, Mar 21, 2022 at 03:18:34PM -0500, Han Xu wrote:
> The code change fixed the kernel gpmi bch setting not aligned with
> u-boot settings issue. It still uses the legacy bch geometry as the
AFAIK there is no merged changes in the kernel regarding this.
The breaking change was done
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