Re: [PATCH v2 5/8] usb: dwc3: Add dwc3 glue driver for am62

Hi Sjoerd, On 2023/04/07 3:55, Sjoerd Simons wrote: Add glue code for TI AM62 to the dwc3 driver; Most code adopted from TI vendor u-boot code. Signed-off-by: Sjoerd Simons --- Changes in v2: - Switch dwc3 glue to a seperate driver rather then in dwc-generic Thanks for helping separate

Re: commit 787f04bb6a - imx: add USB2_BOOT type

On Thu, Apr 20, 2023 at 03:13:42PM -0700, Tim Harvey wrote: > On Sun, Apr 16, 2023 at 11:55 PM Rasmus Villemoes > wrote: > > > > On 26/10/2022 01.42, Rasmus Villemoes wrote: > > > On 18/10/2022 02.43, Peng Fan wrote: > > >> + Stefano & Fabio > > >> > > > > > > > > > Is there any chance

Re: [PATCH v2 06/17] mmc: rockchip_sdhci: Use set_clock and config_dll sdhci_ops

On Thu, Apr 20, 2023 at 03:45:17PM +, Jonas Karlman wrote: > Hi Kever, > On 2023-04-20 13:10, Jonas Karlman wrote: > > Hi Kever, > > On 2023-04-20 12:19, Kever Yang wrote: > >> Hi Tom, > >> > >> I got error report like below log when apply many of this patchset with > >> "git-pw patch apply

Re: [PATCH 1/1] patman: fix class TestFunctional

On Fri, 21 Apr 2023 at 06:07, Heinrich Schuchardt wrote: > > Variable orig_dir cannot be used in the finally block if it has not be > assigned outside of the try block. > > tools/patman/func_test.py:523:21: > E0601: Using variable 'orig_dir' before assignment > (used-before-assignment) > >

Re: [PATCH v9 8/9] rockchip: Move to standard boot

Hi Tom, On Mon, 24 Apr 2023 at 11:35, Tom Rini wrote: > > On Sun, Apr 23, 2023 at 10:46:27PM +, Jonas Karlman wrote: > > Hi Simon, > > > > On 2023-04-08 22:44, Simon Glass wrote: > > > Drop the distro-boot scripts and use standard boot instead. > > > > With the "Drop patches which enable

Re: [PATCH 1/1] tools: fix TestFdtUtil()

On Fri, 21 Apr 2023 at 06:03, Heinrich Schuchardt wrote: > > Variable old_outdir cannot be used before assignment. > The assignment must occur before the try block. > > tools/dtoc/test_fdt.py:796:26: > E0601: Using variable 'old_outdir' before assignment > (used-before-assignment) > > Add missing

Re: [PATCH 1/1] test: fix launch_efi()

On Fri, 21 Apr 2023 at 05:57, Heinrich Schuchardt wrote: > > We cannot use old_dtb in the finally block if it has not been assigned > before the try block. > > test/py/tests/test_efi_fit.py:458:30: > E0601: Using variable 'old_dtb' before assignment (used-before-assignment) > > Fixes:

Re: [PATCH] doc:fix typo in 'mmc write' example

Hi Shirokov, On Fri, 21 Apr 2023 at 22:48, Shirokov Alexander wrote: > > Hello Simon, > > Thanks for your answer.Using 0x explicitly shows that we are working with HEX. > But without the prefix, it looks like a decimal number. And it's more > confusing > when the number of blocks looks like a

[PATCH v10 8/9] rockchip: Move to standard boot

Drop the distro-boot scripts and use standard boot instead. Signed-off-by: Simon Glass Tested-by: Jonas Karlman --- Changes in v10: - Drop DISTRO_DEFAULTS and add BOOTSTD_DEFAULTS for all rockchip boards as suggested by Jonas Karlman Changes in v4: - Add back BOOT_TARGETS Changes in v3: -

[PATCH v10 9/9] rockchip: Use the same boot_targets for all boards

It doesn't really matter if we mention things which are not present. For example, if 'nvme' is included but the board does not support it, it just continues with the next item in the list. It is simpler to use the same target list for all boards, so drop the different one for rk3399.

[PATCH v10 7/9] bootstd: Use blk uclass device numbers to set efi bootdev

From: Mathew McBride When loading a file from a block device, efiload_read_file was using the seq_num of the device (e.g "35" of virtio_blk#35) instead of the block device id (e.g what you get from running the corresponding device scan command, like "virtio 0") This cause EFI booting from these

[PATCH v10 6/9] bootstd: Adjust code ordering to work around compiler quirk

At present when debugging is off, bootdev_find_in_blk() sometimes fails to find a valid bootflow, e.g. with virtio. Accessing the 'blk' variable later in the function seems to correct it. Move the 'ret' check before the debug statement and set the block device again aftewards, to work around

[PATCH v10 4/9] bootstd: Report missing labels only when asked

Use the -l flag to indicate whether to report missing uclasses. Also try to be more helpful when no devices are found. For example, when we see something 'scsi0' requested and nothing was found, this indicates that there are no SCSI devices, so show a suitable message. Move messages out of the

[PATCH v10 3/9] bootstd: Support booting EFI where multiple options exist

The current EFI implementation has a strange quirk where it watches loaded files and uses the last-loaded file to determine the device that is being booted from. This is confusing with bootstd, where multiple options may exist. Even loading a device tree will cause it to go wrong. There is no API

[PATCH v10 5/9] bootstd: Show a message sometimes if no bootflows are found

Enable some messages that might provide hints, but only for CMD_BOOTFLOW_FULL since otherwise the -l flag is not available. Signed-off-by: Simon Glass Suggested-by: Tom Rini --- (no changes since v6) Changes in v6: - Add new patch to show a message sometimes if no bootflows are found

[PATCH v10 0/9] bootstd: Convert rockchip and add various fixes and tweaks

This series converts rockchip boards over to use standard boot. It also fixes various problems which have come up recently, showing differences between the current implementation and the distroboot scripts. This should get us closer to being able to turn down the scripts. Changes in v10: - Drop

[PATCH v10 2/9] virtio: Ensure PCI is set up first

Sometimes virtio may rely on PCI, or at least that is what the distro_bootcmd script suggests. Add this in. Signed-off-by: Simon Glass --- (no changes since v5) Changes in v5: - Add new patch to ensure PCI is set up first when using virtio drivers/virtio/virtio-uclass.c | 6 ++ 1 file

[PATCH v10 1/9] bootstd: Tweak bootflow logic for device tree

We should only store the FDT filename if we were able to determine one. Adjust the logic for this. This corrects the case where no FDT is needed to boot, such as with EFI using ACPI. Signed-off-by: Simon Glass --- (no changes since v6) Changes in v6: - Fix 'unable' typo Changes in v5: - Add

Re: [PATCH v3 08/25] menu: Make use of CLI character processing

On Tue, Apr 18, 2023 at 07:49:34PM -0600, Simon Glass wrote: > Hi Daniel, > > On Tue, 11 Apr 2023 at 14:19, Daniel Golle wrote: > > > > On Fri, Jan 06, 2023 at 08:52:26AM -0600, Simon Glass wrote: > > > Avoid duplicating some of the escape-sequence processing here and use the > > > CLI function

[PATCH v5 00/10] Renesas RZ/N1 SoC initial support

The RZ/N1 is a family of SoC devices from Renesas [1], featuring ARM Cortex-A7 and/or Cortex-M3 CPU, industrial ethernet protocols, integrated Ethernet switch, and numerous peripherals. This is a first step in upstreaming support for the RZ/N1 family. Currently it contains just enough to boot to

[PATCH v5 08/10] board: schneider: add RZN1 board support

Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which are based on the Reneasas RZ/N1 SoC devices. The intention is to support both boards using a single defconfig, and to handle the differences at runtime. Signed-off-by: Ralph Siemsen --- Changes in v5: - put all local DTS

[PATCH v5 09/10] tools: spkgimage: add Renesas SPKG format

Renesas RZ/N1 devices contain BootROM code that loads a custom SPKG image from QSPI, NAND or USB DFU. Support this format in mkimage tool. SPKGs can optionally be signed, however creation of signed SPKG is not currently supported. Example of how to use it: tools/mkimage -n

[PATCH v5 10/10] doc: renesas: add Renesas board docs

As a starting point, list all currently supported Renesas boards. For the RZ/N1 board, add details about booting and flashing. Signed-off-by: Ralph Siemsen --- Changes in v5: - added renesas dir to doc/board/index.rst - corrections to list of Renesas boards - move RZ/N1 detail into its own

[PATCH v5 06/10] ARM: dts: add devicetree for Renesas RZ/N1 SoC

This is taken directly from Linux kernel 6.3-rc7. Signed-off-by: Ralph Siemsen --- Changes in v5: - r9a06g032.dtsi now identical to linux 6.3-rc7 version Changes in v3: - add syscon phandle to ddrctl - simplify UART compatible strings arch/arm/dts/r9a06g032.dtsi | 477

[PATCH v5 03/10] clk: renesas: add R906G032 driver

Clock driver for the Renesas RZ/N1 SoC family. This is based on Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"), with the following additional patch series applied:

[PATCH v5 07/10] ARM: rmobile: Add support for Renesas RZ/N1 SoC

The RZ/N1 is a family of SoC devices from Renesas, featuring: * ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3 * Integrated SRAM up to 6MB * Integrated gigabit ethernet switch * Optional DDR2/3 controller * I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD Add basic support for this

[PATCH v5 04/10] pinctrl: renesas: add R906G032 driver

Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC. This is quite rudimentary right now, and only supports applying a default pin configuration as specified by the device tree. Signed-off-by: Ralph Siemsen Reviewed-by: Marek Vasut --- Changes in v5: - add R-b tag

[PATCH v5 05/10] ram: cadence: add driver for Cadence EDAC

Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Signed-off-by: Ralph Siemsen --- Changes in v5: - move board-specific init out of the driver. Changes in v3: - assorted small cleanups - support version 1.0 silicon (previously #if 0...) drivers/ram/Kconfig|

[PATCH v5 01/10] ARM: armv7: add non-SPL enable for Cortex SMPEN

Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S") added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For platforms not using SPL boot, add the corresponding non-SPL config, so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected. Signed-off-by: Ralph

[PATCH v5 02/10] clk: renesas: prepare for non R-Car clock drivers

Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3. This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing recursion into the drivers/clk/reneasas directory, without bringing in the R-Car

Re: [PATCH v9 8/9] rockchip: Move to standard boot

On Sun, Apr 23, 2023 at 10:46:27PM +, Jonas Karlman wrote: > Hi Simon, > > On 2023-04-08 22:44, Simon Glass wrote: > > Drop the distro-boot scripts and use standard boot instead. > > With the "Drop patches which enable BOOTSTD_DEFAULT" in v9 we must imply > BOOTSTD_DEFAULTS or we run into

Re: [PATCH v9 8/9] rockchip: Move to standard boot

Hi Simon, On 2023-04-08 22:44, Simon Glass wrote: > Drop the distro-boot scripts and use standard boot instead. With the "Drop patches which enable BOOTSTD_DEFAULT" in v9 we must imply BOOTSTD_DEFAULTS or we run into the following on anything rk not rk3399. ## Error: "distro_bootcmd" not

Re: [PATCH] patman: Declare the future Series memory

On Mon, Apr 24, 2023 at 06:16:00AM +1200, Simon Glass wrote: > This member is used in series.MakeCcFile() so should be declared in the > Series class. > > Add a declaration to silence the warning. > > Signed-off-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc

Re: Pull request: u-boot-rockchip-20230421

On Sun, Apr 23, 2023 at 08:36:41AM +0800, Kever Yang wrote: > Hi Tom, > > This is the first PR for rockchip platform, and still many patches are in the > list for some reason, suppose to have one more PR in next week. OK. > Please pull the updates for rockchip platform: > - Add rk3588 evb

[PATCH] patman: Declare the future Series memory

This member is used in series.MakeCcFile() so should be declared in the Series class. Add a declaration to silence the warning. Signed-off-by: Simon Glass ---

[PATCH v1 5/5] ddr: altera: Add IOSSM mailbox support for DDR driver

From: Sin Hui Kho Add IOSSM mailbox support for DDR driver to access memory interface implemented on an IO96B instance. Signed-off-by: Sin Hui Kho --- drivers/ddr/altera/Makefile| 2 +- drivers/ddr/altera/iossm_mailbox.c | 847 +

[PATCH v1 4/5] arm: socfpga: agilex7: Add DDR handoff data support for AGILEX7

From: Sin Hui Kho Add AGILEX7 supported DDR handoff data Signed-off-by: Sin Hui Kho --- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 11 ++- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 4 2 files changed, 14 insertions(+), 1 deletion(-) diff --git

[PATCH v1 3/5] arm: socfpga: soc64: Add F2SDRAM sideband manager base address for SOC64

From: Sin Hui Kho F2SDRAM sideband manager in MPFE is used in DDR driver to configure the data traffic path. Signed-off-by: Sin Hui Kho --- arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH v1 2/5] arm: socfpga: agilex7: Add boot scratch register used for DDR driver

From: Sin Hui Kho Add boot scratch register 8 in system manager used for AGILEX7 DDR driver. Signed-off-by: Sin Hui Kho --- .../include/mach/system_manager_soc64.h | 19 ++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git

[PATCH v1 1/5] ddr: altera: agilex7: Add SDRAM driver for AGILEX7

From: Sin Hui Kho Add SDRAM driver for AGILEX7 SoC. Signed-off-by: Sin Hui Kho --- drivers/ddr/altera/Makefile| 1 + drivers/ddr/altera/sdram_agilex7.c | 331 + drivers/ddr/altera/sdram_soc64.c | 15 +- drivers/ddr/altera/sdram_soc64.h | 9 +- 4

[PATCH v1 0/5] Add new DDR driver support for Agilex7

From: Sin Hui Kho *** BLURB HERE *** Sin Hui Kho (5): ddr: altera: agilex7: Add SDRAM driver for AGILEX7 arm: socfpga: agilex7: Add boot scratch register used for DDR driver arm: socfpga: soc64: Add F2SDRAM sideband manager base address for SOC64 arm: socfpga: agilex7: Add DDR

[PATCH v1 6/6] arm: socfpga: agilex7: Add base address for AGILEX7

From: Sin Hui Kho Add base address support for AGILEX7. Reuse same base as Agilex. Signed-off-by: Sin Hui Kho --- arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff

[PATCH v1 5/6] arm: socfpga: agilex7: Add clock manager support for AGILEX7

From: Sin Hui Kho Add clock manager driver support for AGILEX7 by reuse Agilex clock manager. Signed-off-by: Sin Hui Kho --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 +- arch/arm/mach-socfpga/misc.c

[PATCH v1 4/6] arm: socfpga: agilex7: Add SPL for AGILEX7 SoC

From: Sin Hui Kho Add SPL support for AGILEX7 SoC. Signed-off-by: Sin Hui Kho --- arch/arm/mach-socfpga/Makefile | 3 + arch/arm/mach-socfpga/spl_agilex7.c | 87 + 2 files changed, 90 insertions(+) create mode 100644 arch/arm/mach-socfpga/spl_agilex7.c diff

[PATCH v1 3/6] arm: dts: agilex7: Add base dtsi and devkit dts

From: Sin Hui Kho Add device tree files for AGILEX7 SoC platform. All clock setting is reuse from Agilex. Signed-off-by: Sin Hui Kho --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex7-u-boot.dtsi | 98 +++ arch/arm/dts/socfpga_agilex7.dtsi

[PATCH v1 2/6] board: intel: agilex7: Add socdk board support for Intel AGILEX7 SoC

From: Sin Hui Kho Add socdk board support for Intel AGILEX7 SoC Signed-off-by: Sin Hui Kho --- board/intel/agilex7-socdk/MAINTAINERS | 7 +++ board/intel/agilex7-socdk/Makefile| 7 +++ board/intel/agilex7-socdk/socfpga.c | 7 +++ 3 files changed, 21 insertions(+) create

[PATCH v1 1/6] arm: socfpga: agilex7: Enable AGILEX7 SoC build

From: Sin Hui Kho Add build support for AGILEX7 SoC. Signed-off-by: Sin Hui Kho --- arch/arm/mach-socfpga/Kconfig | 18 + arch/arm/mach-socfpga/Makefile | 14 +++- configs/socfpga_agilex7_defconfig | 95 +

[PATCH v1 0/6] Add new device Agilex7 support

From: Sin Hui Kho *** BLURB HERE *** Sin Hui Kho (6): arm: socfpga: agilex7: Enable AGILEX7 SoC build board: intel: agilex7: Add socdk board support for Intel AGILEX7 SoC arm: dts: agilex7: Add base dtsi and devkit dts arm: socfpga: agilex7: Add SPL for AGILEX7 SoC arm: socfpga:

Re: Pull request for efi-2023-07-rc1-2

On Fri, Apr 21, 2023 at 02:20:27PM +0200, Heinrich Schuchardt wrote: > Dear Tom, > > The following changes since commit 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79: > > Merge tag 'u-boot-nand-20230417' of > https://source.denx.de/u-boot/custodians/u-boot-nand-flash (2023-04-17 > 10:47:33 -0400)

Re: [PULL] u-boot-riscv/master

On Fri, Apr 21, 2023 at 12:41:14AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79: > > Merge tag 'u-boot-nand-20230417' of > https://source.denx.de/u-boot/custodians/u-boot-nand-flash (2023-04-17 > 10:47:33 -0400) > > are

Re: Please pull u-boot-watchdog/master

On Thu, Apr 20, 2023 at 12:02:19PM +0200, Stefan Roese wrote: > Hi Tom, > > please pull the following watchdog related patches: > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature

Re: [PULL] Pull request for u-boot master / v2023.07 = u-boot-stm32_20230409​

On Wed, Apr 19, 2023 at 11:35:58AM +0200, Patrice CHOTARD wrote: > Hi Tom > > Please pull the STM32 related fixes for u-boot/master, v2023.07: > u-boot-stm32-20230419 > > CI status: > https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/16033 > > The following changes since commit

Re: Pull request for u-boot-nand-20230422

On Sun, Apr 23, 2023 at 12:03:28AM +0200, Dario Binacchi wrote: > Hi Tom, > > The following changes since commit 5db4972a5bbdbf9e3af48ffc9bc4fec73b7b6a79: > > Merge tag 'u-boot-nand-20230417' of > https://source.denx.de/u-boot/custodians/u-boot-nand-flash (2023-04-17 > 10:47:33 -0400) > >

Re: [PATCH v5 1/3] starfive: pci: Add StarFive JH7110 pcie driver

On Sunday 23 April 2023 18:58:57 Minda Chen wrote: > From: Mason Huo > > Add pcie driver for StarFive JH7110, Also add PLDA > PCIe controller common driver functions. > > Several devices are tested: > a) M.2 NVMe SSD > b) Realtek 8169 Ethernet adapter. > > Signed-off-by: Mason Huo >

[PATCH v5 1/3] starfive: pci: Add StarFive JH7110 pcie driver

From: Mason Huo Add pcie driver for StarFive JH7110, Also add PLDA PCIe controller common driver functions. Several devices are tested: a) M.2 NVMe SSD b) Realtek 8169 Ethernet adapter. Signed-off-by: Mason Huo Signed-off-by: Minda Chen --- drivers/pci/Kconfig| 13 ++

[PATCH v5 3/3] riscv: dts: starfive: Enable PCIe host controller

From: Mason Huo Enable and add pinctrl configuration for PCIe host controller. Also add JH7110 stg syscon configuration. Signed-off-by: Mason Huo Signed-off-by: Minda Chen --- .../dts/jh7110-starfive-visionfive-2.dtsi | 11 +++ arch/riscv/dts/jh7110.dtsi| 88

[PATCH v5 2/3] configs: starfive-jh7110: Add support for PCIe host driver

From: Mason Huo also add the nvme driver and rtl8169 support. Signed-off-by: Mason Huo Signed-off-by: Minda Chen --- configs/starfive_visionfive2_12a_defconfig | 10 ++ configs/starfive_visionfive2_13b_defconfig | 10 ++ 2 files changed, 20 insertions(+) diff --git

[PATCH v5 0/3] Add StarFive JH7110 PCIe drvier support

This patchset needs to apply after patchset in [1]. These PCIe series patches are based on the JH7110 RISC-V SoC and VisionFive V2 board. [1] https://patchwork.ozlabs.org/project/uboot/cover/20230329034224.26545-1-yanhong.w...@starfivetech.com The PCIe driver depends on gpio, pinctrl, clk and

Re: [PATCH v8 00/24] Fixes for Rockchip NFC driver part 1

On 4/23/23 03:51, Kever Yang wrote: > Hi Johan, > > On 2023/4/21 23:34, Johan Jonker wrote: >> >> On 4/21/23 05:15, Kever Yang wrote: >>> Hi Johan, >>> >>> I got below error report from CI test, I think it should be relate to >>> this patch set. >>> >>>

[PATCH v9] core: fdtaddr: use map_sysmem() as cast for the return

For the devfdt_get_addr_index_ptr() and devfdt_get_addr_size_index_ptr() function use map_sysmem() function as cast for the return for use in sandbox. Also fix sandbox test. Signed-off-by: Johan Jonker --- Apply after: [PATCH v8 00/24] Fixes for Rockchip NFC driver part 1 with replacement: