On 7/19/23 10:49, Ashok Reddy Soma wrote:
gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.
Signed-off-by: Ashok Reddy Soma
---
drivers/clk/clk_zynqmp.c | 2 ++
1 file changed, 2 insertions(+)
d
On 7/20/23 09:28, Ashok Reddy Soma wrote:
Add gem_tsu and gem0_rx till gem3_rx to return proper register from
zynqmp_clk_get_register. Otherwise firmware won't be able to set clock
for these due to incorrect register address.
Signed-off-by: Ashok Reddy Soma
---
drivers/clk/clk_zynqmp.c |
On Thu, Jul 20, 2023 at 06:27:56PM +0300, Roger Quadros wrote:
>
>
> On 20/07/2023 12:55, Maxime Ripard wrote:
> > Dropping ranges entirely doesn't work since the register offset on the
> > MDIO device node will now be completely off, so we need to adjust it to
> > the right value without the tra
On 7/21/2023 12:39 PM, Mathew McBride wrote:
Board revision C (production) and later require the SFP+
retimer to be turned on (or reset) on boot, by way of issuing
a command to the board's microcontroller (via I2C).
The comparison statement here was incorrect, as the board
ID decrements every
On 7/21/2023 12:39 PM, Mathew McBride wrote:
The DPAA2 DPL (data plane layout) file was previously
being loaded into 0x8030, and set to be applied
just before hand off to the kernel.
When a FIT image with a load_address of 0x8000 was
booted with bootm, the DPL in memory was overwritte
On 7/21/2023 12:39 PM, Mathew McBride wrote:
Change the firmware on microSD path to "firmware/traverse/ten64"
as per EBBR section 4.2[1].
The Traverse firmware tools now locate the DPAA2 firmware
and configuration files under that path on the rescue
SD card image.
If a user then installs a st
On 7/21/2023 12:39 PM, Mathew McBride wrote:
The recovery environment[1] on the Ten64 is a OpenWrt-
based ramdisk stored on the NAND intended to help with
system setup tasks.
Before the bootargs were not being set for the recovery
command, relying instead on the existing bootargs variable.
E
On 7/21/2023 12:39 PM, Mathew McBride wrote:
The default Ten64 MTD configuration reserves two ubifs partitions
for OpenWrt residing on NAND flash. Add the bootcmd for this system
into the default environment.
Signed-off-by: Mathew McBride
Reviewed-by: Peng Fan
On 7/21/2023 12:39 PM, Mathew McBride wrote:
The recovery-firmware and OpenWrt-NAND do not yet have bootflow
/bootstd entrypoints, so add bootmenu entries to make them
accessible.
Signed-off-by: Mathew McBride
Reviewed-by: Peng Fan
On 7/21/2023 12:39 PM, Mathew McBride wrote:
This restores NVMe functionality after PCI(e) NVMe support
was split out from the NVMe driver.
Signed-off-by: Mathew McBride
Reviewed-by: Peng Fan
On 7/21/2023 12:39 PM, Mathew McBride wrote:
Ensure nvme devices are scanned before reaching the shell,
otherwise extra user intervention ("nvme scan") is required
before they are visible to bootdev/bootflow.
Signed-off-by: Mathew McBride
Reviewed-by: Peng Fan
On 7/21/2023 12:39 PM, Mathew McBride wrote:
The GE0 (first Gigabit Ethernet interface) is used as the
'serial number' for the board and appliance.
To ensure the 'true' board S/N is available regardless of how
the DPAA2 subsystem is configured, use serial# so it is passed in
the device tree.
On 7/21/2023 12:39 PM, Mathew McBride wrote:
The watchdog driver was previously enabled but not used
until U-Boot's fsl-ls1088a.dtsi was updated to describe them.
Some Linux distributions (e.g Debian 11) do not engage the
SP805 watchdogs, causing unexpected resets after boot.
To conserve the
On 7/21/2023 12:39 PM, Mathew McBride wrote:
With the previous updates to the device tree, Ten64
can use Standard Boot 'out of the box'.
Signed-off-by: Mathew McBride
Reviewed-by: Peng Fan
On 7/21/2023 12:39 PM, Mathew McBride wrote:
Allow individual Layerscape boards to opt-out of fsl_setenv_bootcmd
by declaring the original function as weak.
fsl_setenv_bootcmd is used to change the bootcmd based on the
TF-A boot source (e.g QSPI vs SD/MMC) for reasons including
secure boot /
On 7/21/2023 12:39 PM, Mathew McBride wrote:
Our bootcmd is the same regardless of where the SoC
loaded it's code from, so we don't want
fsl_setenv_bootcmd to do anything.
Signed-off-by: Mathew McBride
Reviewed-by: Peng Fan
On 7/21/2023 12:39 PM, Mathew McBride wrote:
The u-boot version of the LS1088A device tree has
an extra compatible (simple-mfd) added to &fsl_mc
to facilitate usage with U-Boot's device model.
Unfortunately FreeBSD will only match the single
"fsl,qoriq-mc" exactly when the node is a "bus"
obj
On 7/21/2023 12:39 PM, Mathew McBride wrote:
Ten64 board revision D is a variant that removes the USB hub
and PCIe expander/switch, but is otherwise compatible with the
main production "C" version.
At the same time, revise the printf specifiers (PCB version
"1064-0201%s") to reduce the number
Some veyron boards seem to have Winbond SPI flash chips instead of
GigaDevice ones. At the very least, coreboot builds for veyron boards
have them enabled [1]. Enable support for them here as well.
[1] https://review.coreboot.org/c/coreboot/+/9719
Signed-off-by: Alper Nebi Yasak
---
configs/ch
On 2023/7/15 18:19, Pegorer Massimo wrote:
Definition of function board_debug_uart_init() must be under
CONFIG_DEBUG_UART_BOARD_INIT and not under CONFIG_DEBUG_UART,
as it was: see debug_uart.h. In this way the debug uart can
be used but its board-specific initialization skipped by
configuratio
On 21/07/2023 10:46, Maxime Ripard wrote:
> On Thu, Jul 20, 2023 at 06:27:56PM +0300, Roger Quadros wrote:
>>
>>
>> On 20/07/2023 12:55, Maxime Ripard wrote:
>>> Dropping ranges entirely doesn't work since the register offset on the
>>> MDIO device node will now be completely off, so we need to
On Fri, Jul 21, 2023 at 12:14:35PM +0300, Roger Quadros wrote:
>
>
> On 21/07/2023 10:46, Maxime Ripard wrote:
> > On Thu, Jul 20, 2023 at 06:27:56PM +0300, Roger Quadros wrote:
> >>
> >>
> >> On 20/07/2023 12:55, Maxime Ripard wrote:
> >>> Dropping ranges entirely doesn't work since the register
On 2023/7/15 18:19, Pegorer Massimo wrote:
Call to board_debug_uart_init() is useless, as mainline U-Boot can
not build TPL for rk3308, and proprietary ddr.bin to be used as TPL
is responsible to init debug uart. Moreover current implementation
of board_debug_uart_init() is not compatible with
On 2023/7/15 18:19, Pegorer Massimo wrote:
Some ROCK Pi S SKU/models are not equipped with SD-NAND (eMMC),
therefore SPL needs access to sdmmc: add it to rk3308-u-boot.dtsi
with bootph-all property.
Signed-off-by: Massimo Pegorer
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/
On 2023/7/15 18:19, Pegorer Massimo wrote:
Boot devices defined in rk3308.c and in rk3308.dtsi do not match, causing
'same-as-spl' feature not to work. Update DTS definitions, aligning to
Linux kernel DTS and to other Rockchip DTS files, i.e. from dwmmc to mmc.
Add rk3308-rock-pi-s.dtb in dtb-
On 5/17/23 13:46, Eugen Hristev wrote:
On 5/15/23 16:16, Tom Rini wrote:
On Mon, May 15, 2023 at 03:57:14PM +0300, Eugen Hristev wrote:
On 5/15/23 15:52, Tom Rini wrote:
On Mon, May 15, 2023 at 03:36:24PM +0300, Eugen Hristev wrote:
On 5/6/23 01:03, Tom Rini wrote:
On Tue, Apr 25, 2023 at 04
Hi Heinrich,
xypron.g...@gmx.de wrote on Thu, 20 Jul 2023 19:55:39 +0200:
> Am 20. Juli 2023 18:39:17 MESZ schrieb Miquel Raynal
> :
> >Hello,
> >
> >qianfangui...@163.com wrote on Fri, 25 Mar 2022 18:04:46 +0800:
> >
> >> It's very strange. And I can't detect it's a bug of usb or dlmalloc.
>
Hi Tom,
tr...@konsulko.com wrote on Thu, 20 Jul 2023 14:34:52 -0400:
> On Thu, Jul 20, 2023 at 06:39:17PM +0200, Miquel Raynal wrote:
> > Hello,
> >
> > qianfangui...@163.com wrote on Fri, 25 Mar 2022 18:04:46 +0800:
> >
> > > It's very strange. And I can't detect it's a bug of usb or dlmallo
We should target to unify the code for different block devices in SPL to
reduce code size.
MMC, USB, SATA, and Semihosting use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to
indicate the filename to load.
NVMe uses CONFIG_SPL_PAYLOAD in spl_blk_load_image().
CONFIG_SPL_PAYLOAD is meant to define which binar
On Thu, Jul 20, 2023 at 06:47:43PM +0300, Roger Quadros wrote:
> On 20/07/2023 12:55, Maxime Ripard wrote:
> > The binding represents the MDIO controller as a child device tree
> > node of the MAC device tree node.
> >
> > The U-Boot driver mostly ignores that child device tree node and just
> > h
The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.
Define the cache line size for QEMU on RISC-V to be 64 bytes.
Signed-off-by: Heinrich Schuchardt
---
arch/Kconfig | 1 +
arch/riscv/Kconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/Kconfig
Hi,
On Fri, Jul 21, 2023 at 12:59:33AM +0300, Roger Quadros wrote:
> Hi,
>
> We need to track the Device tree in Linux.
> The approved property for MAC address EFUSE is "ti,syscon-efuse".
>
> Use that and drop custom property "mac_efuse".
On a SK-AM62:
Reviewed-by: Maxime Ripard
Tested-by: Ma
Hi,
This series is based on:
https://lore.kernel.org/all/20230713072019.3153871-1...@ti.com/
https://lore.kernel.org/all/20230720215935.107398-1-rog...@kernel.org/
It fixes the issue of Linux booting from the DT embedded by U-boot. The
main issue there is that U-Boot doesn't handle the MDIO child
The binding represents the MDIO controller as a child device tree
node of the MAC device tree node.
The U-Boot driver mostly ignores that child device tree node and just
hardcodes the resources it uses to support both the MAC and MDIO in a
single driver.
However, some resources like pinctrl muxin
The MDIO pinctrl nodes can't be duplicated between the child and device,
because if we ever boot Linux with our DT it will try to attach that
pinctrl configuration to both the MAC and MDIO devices, which will
result in failure to probe.
Signed-off-by: Maxime Ripard
---
arch/arm/dts/k3-am625-sk-u
Dropping ranges entirely doesn't work since the register offset on the
MDIO device node will now be completely off, so we need to adjust it to
the right value without the translation.
We also need to have an empty ranges property for the reg address to be
properly evaluated.
Signed-off-by: Maxime
Hi Tom,
please pull these patches to your tree. CI is not reporting any issue.
The biggest part is adding support for versal-net mini configuration for non
volatile memories programming and also DT changes based on our effort to be
aligned with dt-schema validation.
Thanks,
Michal
The follow
On 09:40-20230715, Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> This adds initial support for the Toradex Verdin AM62 Quad 1GB WB IT
> V1.0A module. They are strapped to boot from their on-module eMMC.
> U-Boot supports booting from the on-module eMMC only, DFU support is
> disabled for now
Hi,
this is finally the series adding support for the new SoC series that
covers the Allwinner D1 siblings R528 and T113s. They all share the
same die, although the D1 and D1s use RISC-V cores, which requires more
plumbing, to use the sunxi code across two architectures. Getting the
R528 support i
At the moment the sun4i EMAC driver relies on hardcoded CONFIG_MACPWR
Kconfig symbols to enable potential PHY regulators. As we want to get rid
of those, we need to find the regulator by chasing up the DT.
The sun4i-emac binding puts the PHY regulator into the MDIO node, which
is the parent of the
So far we were open-coding the pincontroller's GPIO output/input access
in each function using that.
Provide functions that wrap that nicely, and follow the existing pattern
(set/get_{bank,}), so users don't need to know about the internals, and
we can abstract the new D1 pinctrl more easily.
Sig
The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
the power for the Ethernet "MAC" (mostly PHY, really).
In the DT this is described with the phy-supply property in the MAC DT
node, pointing to a (GPIO controlled) regulator. Since we need Ethernet
only in U-Boot proper, and u
So far every Allwinner SoC used the same basic pincontroller/GPIO
register frame, and just differed by the number of implemented banks and
pins, plus some special functionality from time to time. However the D1
and successors use a slightly different pinctrl register layout.
Use that opportunity to
On the Allwinner platform we were describing a quite comprehensive
memory map in a per-SoC header unser arch/arm.
In the old days that was used by every driver, but nowadays it should
only be needed by SPL drivers (not using the DT). Many addresses in
there were never used, and some are not needed
U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code
to more easily include platform specific GPIO headers. This should not
be needed in a DM world anymore, since the generic GPIO framework
handles that nicely.
For Allwinner boards we still need to deal with non-DM GPIO in the S
For the first time since at least the Allwinner A10 SoCs, the D1 (and
related cores) use a new pincontroller MMIO register layout, so we
cannot use our hardcoded, fixed offsets anymore.
Ideally this would all be handled by devicetree and DM drivers, but for
the DT-less SPL we still need the legacy
Apart from using the new pinctrl MMIO register layout, the Allwinner D1
and related SoCs still need to usual set of mux values hardcoded in
U-Boot's pinctrl driver.
Add the values we need so far to this list, so that DM based drivers
will just work without further ado.
Signed-off-by: Andre Przywar
The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL.
Just enable that when we program that PLL.
Signed-off-by: Andre Przywara
---
arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 1 +
arch/arm/mach-sunxi/clock_sun50i_h6.c | 12 +++-
2 files changed, 8
The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is
new P0 divider at bits [18:16], and the M divider is 1.
Add code to support this version of "PLL6".
Signed-off-by: Andre Przywara
---
.../include/asm/arch-sunxi/clock_sun50i_h6.h | 2 ++
arch/arm/mach-sunxi/clock_sun50i_h
From: Samuel Holland
Since the D1 CCU binding is defined, we can add support for its
gates/resets, following the pattern of the existing drivers.
Signed-off-by: Samuel Holland
Reviewed-by: Andre Przywara
Acked-by: Sean Anderson
Signed-off-by: Andre Przywara
---
drivers/clk/sunxi/Kconfig
At the moment all Allwinner DRAM initialisation routines are stored in
arch/arm/mach-sunxi, even though those "drivers" are just a giant
collection of writel's, without any architectural dependency.
The R528/T113-s SoC (with ARM cores) and the D1/D1s Soc (with RISC-V
cores) share the same die, so
The Allwinner D1/R528/T113 SoCs have a very minimal separate
"management" power plane, with almost no device attached to it (so
no r_i2c or r_uart). This means we don't need to flip any clock gates in
the PRCM block, which in fact those SoCs do not have.
Prepare the code for those SoCs by making t
This adds the remaining code bits to teach U-Boot about Allwinner's
newest SoC generation. This was introduced with the RISC-V based
Allwinner D1 SoC, which actually shares a die with the ARM cores versions
called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM).
This adds the new Kcon
The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the
same DRAM initialisation code.
Make use of prior art here and lift some code from awboot[1], which
carried init code based on earlier decompilation efforts, but with a
GPL2 license tag.
This code has been heavily reworked and
At the moment we have each SoC's memory map defined in its own cpu.h,
which is included in include/configs/sunxi_common.h. This will be a
problem with the introduction of Allwinner RISC-V support.
Remove the inclusion of that header file from the common config header,
instead move the required ser
The Allwinner T113-s SoC is apparently using the same (or at least a very
similar) die as the D1/D1s, but replaces the single RISC-V core with
two Arm Cortex-A7 cores.
Since the D1 core .dtsi already describes all common peripherals, we
just need a DT describing the ARM specific peripherals: the CP
From: Samuel Holland
D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
on a single die, or at a pair of dies derived from the same design.
D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
T113 contain a pair of Cortex-A7's. D1 and R528 are the full ver
This copies the T113s specific DTs from the Linux kernel tree
(v6.4-rc1), and adds a defconfig to get the board booted.
Signed-off-by: Andre Przywara
---
arch/arm/dts/Makefile | 2 +
.../arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts | 35 +
arch/arm/dts/sunxi-d1s-t113-
Allwinner seems to typically stick to a common MMIO memory map for
several SoCs, but from time to time does some breaking changes, which
also introduce new generations of some peripherals. The last time this
happened with the H6, which apart from re-organising the base addresses
also changed the cl
Hi Tom,
please pull the first part of the sunxi pull request for this cycle:
For once this adds USB support for two SoCs: the H616 and the F1C100s
series. The rest is support for LPDDR3 DRAM chips on H616 boards.
Gitlab CI passed, and I booted that briefly on an H616 and an F1C200s
board. I don'
On Thu, Jul 20, 2023 at 02:13:38PM -0600, Simon Glass wrote:
> Hi Tom,
>
> I am bringing in the binman changes now. There are going to be some
> minor tweaks to templating as well as various patches from others, but
> most are based on these patches.
>
>
> https://source.denx.de/u-boot/custodia
On Fri, Jul 21, 2023 at 8:59 PM Heinrich Schuchardt
wrote:
>
> The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.
>
> Define the cache line size for QEMU on RISC-V to be 64 bytes.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/Kconfig | 1 +
> arch/riscv/Kconf
On 7/18/23 13:53, lukas.funke-...@weidmueller.com wrote:
From: Lukas Funke
Add the Xilinx Bootgen as bintool. Xilinx Bootgen is used to create
bootable SPL (FSBL in Xilinx terms) images for Zynq/ZynqMP devices. The
btool creates a signed version of the SPL. Additionally to signing the
key so
On 7/18/23 13:53, lukas.funke-...@weidmueller.com wrote:
From: Lukas Funke
This series adds two etypes to create a verified boot chain for
Xilinx ZynqMP devices. The first etype 'xilinx-fsbl-auth' is used to
create a bootable, signed image for ZynqMP boards using the Xilinx
Bootgen tool. Th
Commit 7d84fbb57312 ("spl: Provide more information on boot failure") left
debug code to let boot_from_devices() always fail if CONFIG_SHOW_ERRORS=y.
Remove the debug code.
Fixes: 7d84fbb57312 ("spl: Provide more information on boot failure")
Signed-off-by: Heinrich Schuchardt
---
common/spl/sp
In SPL environment variables may not be enabled.
Suggested-by: Tom Rini
Signed-off-by: Heinrich Schuchardt
---
disk/part.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/disk/part.c b/disk/part.c
index 3a9315c0ab..6a30335a48 100644
--- a/disk/part.c
+++ b/disk/part.
The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.
Define the cache line size for QEMU on RISC-V to be 64 bytes.
Signed-off-by: Heinrich Schuchardt
---
v2:
Select SYS_CACHE_SHIFT_6 for GENERIC_RISCV and not for
TARGET_QEMU_VIRT (as suggested by Bin)
---
Hi Neha,
On Wed, 19 Jul 2023 at 13:11, Simon Glass wrote:
>
> Hi Neha,
>
> On Wed, 19 Jul 2023 at 05:08, Neha Malcom Francis wrote:
> >
> > Hi Simon
> >
> > On 18/07/23 18:54, Simon Glass wrote:
> > > Collections can used to collect the contents of other entries into a
> > > single entry, but th
With the basic template feature in place, some problems have come to
light.
Firstly, keeping the template around while processing entries seems
unnecessary and perhaps confusing, so this is removed.
Secondly this series aims to support phandles in a more intuitive way,
rather than just ignoring t
This file aids debugging when binman fails to get far enough to write out
the final devicetree file. Write it immediate after template processing.
Signed-off-by: Simon Glass
---
tools/binman/binman.rst | 4
tools/binman/control.py | 14 --
tools/binman/ftest.py | 9
Without the 'dirty' flag properties are not written back to the
devicetree when synced. This means that new properties copied over to a
node are not always written out.
Fix this and add a test.
Signed-off-by: Simon Glass
---
tools/dtoc/fdt.py | 1 +
tools/dtoc/test/dtoc_test_
Show the operations being performed, when debugging is enabled.
Convert a mistaken 'print' in test_copy_subnodes_from_phandles() while we
are here.
Signed-off-by: Simon Glass
---
tools/dtoc/fdt.py | 5 +
tools/dtoc/test_fdt.py | 3 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
Allow phandles to be copied over from a template. This can potentially
cause duplicate phandles, but we can deal with that later.
Signed-off-by: Simon Glass
---
tools/dtoc/fdt.py | 2 +-
tools/dtoc/test_fdt.py | 15 ---
2 files changed, 9 insertions(+), 8 deletions(-)
diff --
It is not necessary to keep templates around after they have been
processed. They can cause confusion and potentially duplicate phandles.
Remove them.
Use the same means of detecting a template node in _ReadImageDesc so that
the two places are consistent.
Signed-off-by: Simon Glass
---
tools/
This provides support for phandles to be copied over from templates. This
is not quite safe, since if the template is instantiated twice (i.e. in
two different nodes), then duplicate phandles will be found.
This patch is provided for some initial experimentation.
Signed-off-by: Simon Glass
---
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:
- mtrr_commit() will re-initialize all MTRR registers from index 0,
using the settings previously added by mtrr_add_request() and saved
in gd->
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:
- mtrr_commit() will re-initialize all MTRR registers from index 0,
using the settings previously added by mtrr_add_request() and saved
in gd->
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:
- mtrr_commit() will re-initialize all MTRR registers from index 0,
using the settings previously added by mtrr_add_request() and saved
in gd->
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:
- mtrr_commit() will re-initialize all MTRR registers from index 0,
using the settings previously added by mtrr_add_request() and saved
in gd->
From: Simon Glass
This function used to be for adding a list of requests to be actioned on
relocation. Revert it back to this purpose, to avoid problems with boards
which need control of their MTRRs (i.e. those which don't use FSP).
The mtrr_set_next_var() function is available when the next fre
On Sat, 13 May 2023 00:59:30 +0200, Heinrich Schuchardt wrote:
> For testing semihosting we need to pass parameter -semihosting.
>
>
Applied, thanks!
[1/1] qemu_arm64_na: enable semihosting
commit: 610263e34c6ceba0de5cd69a7c4e5a6205b886f9
Best regards,
--
Tom
Some coding convention fixes for print_resetinfo().
Signed-off-by: Bin Meng
---
common/board_f.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index e5969ec9a2..db37522f61 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -148
On Sat, Jul 22, 2023 at 12:01 AM Heinrich Schuchardt
wrote:
>
> The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.
>
> Define the cache line size for QEMU on RISC-V to be 64 bytes.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v2:
> Select SYS_CACHE_SHIFT_6 for G
Hi Simon
On 21/07/23 21:37, Simon Glass wrote:
With the basic template feature in place, some problems have come to
light.
Firstly, keeping the template around while processing entries seems
unnecessary and perhaps confusing, so this is removed.
Secondly this series aims to support phandles in
On Fri, Jul 21, 2023 at 05:32:20PM +0200, Heinrich Schuchardt wrote:
> Commit 7d84fbb57312 ("spl: Provide more information on boot failure") left
> debug code to let boot_from_devices() always fail if CONFIG_SHOW_ERRORS=y.
>
> Remove the debug code.
>
> Fixes: 7d84fbb57312 ("spl: Provide more in
Hi Heinrich,
On Fri, 21 Jul 2023 at 09:32, Heinrich Schuchardt
wrote:
>
> Commit 7d84fbb57312 ("spl: Provide more information on boot failure") left
> debug code to let boot_from_devices() always fail if CONFIG_SHOW_ERRORS=y.
>
> Remove the debug code.
>
> Fixes: 7d84fbb57312 ("spl: Provide more
On Fri, Jul 21, 2023 at 03:30:54PM +0200, Michal Simek wrote:
> Hi Tom,
>
> please pull these patches to your tree. CI is not reporting any issue.
> The biggest part is adding support for versal-net mini configuration for non
> volatile memories programming and also DT changes based on our effort
On Fri, Jul 21, 2023 at 02:48:57PM +0100, Andre Przywara wrote:
> Hi Tom,
>
> please pull the first part of the sunxi pull request for this cycle:
>
> For once this adds USB support for two SoCs: the H616 and the F1C100s
> series. The rest is support for LPDDR3 DRAM chips on H616 boards.
>
> Gi
This series aims to eliminate the use of additional custom repositories
such as k3-image-gen (K3 Image Generation) repo and core-secdev-k3 (K3
Security Development Tools) that was plumbed into the U-Boot build flow
to generate boot images for TI K3 platform devices. And instead, we move
towards usi
The ti-board-config entry loads and validates a given YAML config file
against a given schema, and generates the board config binary. K3
devices require these binaries to be packed into the final system
firmware images.
Reviewed-by: Simon Glass
Signed-off-by: Neha Malcom Francis
---
tools/binma
The ti-secure entry contains certificate for binaries that will be
loaded or booted by system firmware whereas the ti-secure-rom entry
contains certificate for binaries that will be booted by ROM. Support
for both these types of certificates is necessary for booting of K3
devices.
Reviewed-by: Sim
Board config binary artifacts must be generated to be used by binman to
package sysfw.itb and tiboot3.bin for all K3 devices.
For devices that follow combined flow, these board configuration
binaries must again be packaged into a combined board configuration
blobs to be used by binman to package t
By providing entries in the binman node of the device tree, binman will
be able to find and package board config artifacts generated by
TIBoardConfig with sysfw.bin and generate the final image sysfw.itb.
It will also pick out the R5 SPL and sign it with the help of TI signing
entry and generate th
Added YAML configs for J7200
Signed-off-by: Neha Malcom Francis
---
board/ti/j721e/board-cfg_j7200.yaml | 36 +
board/ti/j721e/pm-cfg_j7200.yaml| 12 +
board/ti/j721e/rm-cfg_j7200.yaml| 2065 +++
board/ti/j721e/sec-cfg_j7200.yaml | 380 +
4 files change
Support has been added for both HS-SE(SR 2.0), HS-FS(SR 2.0) and GP
images.
HS-SE:
* tiboot3-j7200_sr2-hs-evm.bin
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-j7200_sr2-hs-fs-evm.bin
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-j7200
Added YAML configs for AM65x
Signed-off-by: Neha Malcom Francis
---
board/ti/am65x/board-cfg.yaml | 36 +
board/ti/am65x/pm-cfg.yaml| 12 +
board/ti/am65x/rm-cfg.yaml| 2068 +
board/ti/am65x/sec-cfg.yaml | 379 ++
4 files changed, 2495 insertion
Support has been added for both HS-SE(SR 2.0) and GP(SR 2.0) images.
HS-SE:
* tiboot3-am65x_sr2-hs-evm.bin
* sysfw-am65x_sr2-hs-evm.itb
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-am65x_sr2-gp-evm.bin
* sysfw.itb --> sysfw-am65x_sr2-gp-ev
Added YAML configs for AM64xx
Signed-off-by: Neha Malcom Francis
---
board/ti/am64x/board-cfg.yaml | 36 +
board/ti/am64x/pm-cfg.yaml| 12 +
board/ti/am64x/rm-cfg.yaml| 1400 +
board/ti/am64x/sec-cfg.yaml | 380 +
4 files changed, 1828 inser
Support added for HS and GP boot binaries for AM64x.
HS-SE:
* tiboot3-am64x_sr2-hs-evm.bin
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-am64x_sr2-hs-fs-evm.bin
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-am64x-gp-evm.bin
* tispl.bin_unsigned
* u-boot.i
Added YAML configs for J721S2
Signed-off-by: Neha Malcom Francis
---
board/ti/j721s2/board-cfg.yaml | 36 +
board/ti/j721s2/pm-cfg.yaml| 12 +
board/ti/j721s2/rm-cfg.yaml| 2901
board/ti/j721s2/sec-cfg.yaml | 379 +
4 files changed, 3328 insert
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