this might be fine now.
Does that make sense?
Cheers,
Andre
On 17 July 2024 18:51:53 BST, Tom Rini wrote:
>On Wed, Jul 17, 2024 at 03:34:15PM +0100, Andre Przywara wrote:
>
>> Sync the devicetree files from the official Linux kernel tree, v6.10.
>> This is covering Allwinne
the .dts files for the Tanix TX1 TV box and
three Anbernic handheld gaming devices.
As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.
Signed-off-by: Andre Przywara
---
arch/arm/dts/sun50i-a64-bananapi-m64.dts | 2
ignificantly increases the performance. Also changing the limit in the
> > DT gets reflected in the driver and in the read speed. Also verified
> > that the values read from the SPI flash are the same in all cases.
> >
> > > Signed-off-by: Michael Walle
> >
&g
to fetch changes up to 674e4f994f5da537cab62ad86bc8bdf5acaae88c:
spi: sunxi: drop max_hz handling (2024-07-16 01:40:40 +0100)
----
Andre Przywara (8):
power: regulator: add AXP717 support
power: pmic: sunxi: only build AXP drivers for SPL
On Fri, 12 Jul 2024 19:14:57 +0200
Michael Walle wrote:
Hi,
> If the maximum frequency is requested, we still fall into the CDR2
> handling. But there the minimal divider is 2. For the sun6i and sun8i we
> can do better with the CDR1 setting where the minimal divider is 1:
> SPI_CLK = MOD_CLK
On Fri, 12 Jul 2024 18:28:15 +0100
Peter Robinson wrote:
> On Fri, 12 Jul 2024 at 18:25, Michael Walle wrote:
> >
> > Right now, the maximal transfer speed from an SPI flash on a V3s is
> > about 240kb/s. That is pretty slow. It turns out, that due to an
> > error u-boot is setting the maximum
limit in the
DT gets reflected in the driver and in the read speed. Also verified
that the values read from the SPI flash are the same in all cases.
> Signed-off-by: Michael Walle
Reviewed-by: Andre Przywara
Tested-by: Andre Przywara
I will make this part of the first 2024.10 PR.
Cheers
On Fri, 12 Jul 2024 17:53:48 +0100
Andre Przywara wrote:
> The axp.c drivers are only used for the SPL, for U-Boot proper we
> have a separate, DM compliant driver.
> Mask the build instructions with CONFIG_SPL_BUILD, to avoid them being
> build for U-Boot proper as well.
For
On Fri, 31 May 2024 16:21:38 +0200
Tobias Schramm wrote:
Hi Tobias,
> Previously enabling I2C1 when using a V3s-based SoC had no effect.
> Set pinmux on PE21 and PE22 to I2C1 function when enabling I2C1 on
> V3s-based SoCs.
Can you say what this patch is about?
Is there any V3s board that has
On Sun, 14 Jul 2024 20:20:44 +1200
"Ryan Walklin" wrote:
Hi Ryan,
> On Sat, 13 Jul 2024, at 4:53 AM, Andre Przywara wrote:
>
> > #define AXP209_I2C_ADDR0x34
> > +#define AXP717_I2C_ADDR0x34
> >
> > #define
On Sat, 29 Jun 2024 02:22:14 +1000
John Watts wrote:
Hi,
> On Fri, Jun 28, 2024 at 04:17:27PM +0100, Andre Przywara wrote:
> > > I do not know if this patch is still a
> > > necessity; though if John is nudging about it, it probably is.
> >
> > Yes ap
for the index we keep
the code cleaner.
Also remove the old driver, and switch the Makefile to include the new,
generic driver.
Signed-off-by: Andre Przywara
---
drivers/power/Makefile | 2 +-
drivers/power/axp305.c | 82 -
drivers/power/axp_spl.c | 16
3
version.
Signed-off-by: Andre Przywara
---
drivers/power/Makefile | 2 +-
drivers/power/axp313.c | 133
drivers/power/axp_spl.c | 14 +
3 files changed, 15 insertions(+), 134 deletions(-)
delete mode 100644 drivers/power/axp313.c
diff --git a/drivers
chip in I2C mode.
This allows to set up the correct voltage for the DRAM chips and the
CPU cores.
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/pmic_bus.c | 3 +++
board/sunxi/board.c| 2 +-
drivers/power/Kconfig | 17 +
drivers/power/Makefile
, that exports axp_set_dcdc() functions to set up
the buck converters. For now this just contains the bits for the (new)
AXP717, but it's not wired up anywhere yet.
Signed-off-by: Andre Przywara
---
drivers/power/axp_spl.c | 143
1 file changed, 143 insertions
The axp.c drivers are only used for the SPL, for U-Boot proper we
have a separate, DM compliant driver.
Mask the build instructions with CONFIG_SPL_BUILD, to avoid them being
build for U-Boot proper as well.
Signed-off-by: Andre Przywara
---
drivers/power/Makefile | 2 ++
1 file changed, 2
The X-Powers AXP717 is a PMIC with four buck converters and a number
of LDOs, one of which is actually fixed (so not modelled here).
Add the compatible string and the respective regulator ranges to allow
drivers to adjust voltages.
Signed-off-by: Andre Przywara
Reviewed-by: Ryan Walklin
is a good
idea.
Cheers,
Andre
Changelog v1 .. v2:
- rebase against latest master
- merge originally separate AXP717 SPL driver into patch 4/6
- include AXP717 U-Boot proper support patch
- drop AXP707 support for now
Andre Przywara (6):
power: regulator: add AXP717 support
power: pmic: sunxi: only
On Thu, 11 Jul 2024 15:40:47 +0200
"Michael Walle" wrote:
> On Tue May 14, 2024 at 1:43 AM CEST, Michael Walle wrote:
> > The V3s is identical regarding register layout, clocks and resets to
> > the sun6i variants. Therefore, we can just add the MACH_SUN8I_V3S to
> > the sun6i compatible ones.
>
On Thu, 27 Jun 2024 17:25:57 -0600
Sam Edwards wrote:
Hi Sam,
thanks for coming back so quickly!
> On 6/27/24 09:06, Andre Przywara wrote:
> > On Thu, 8 Jun 2023 13:56:31 -0600
> > Sam Edwards wrote:
> >
> > Hi,
> >
> > John asked me have a look at t
On Thu, 8 Jun 2023 13:56:31 -0600
Sam Edwards wrote:
Hi,
John asked me have a look at this.
> Since many sunxi boards do not implement a `board_usb_init`, it's
I am confused, what has this have to do with gadget support? *No* sunxi
board build provides board_usb_init(), but apparently this
On Sun, 23 Jun 2024 14:30:24 -0600
Simon Glass wrote:
> This binary does not prevent the system from booting. Mark it optional
> so that U-Boot can be built without it.
>
> Signed-off-by: Simon Glass
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
>
> (no changes sin
Hi,
some Allwinner devices use some kind of "secure boot", which requires the
SPL image to be build wrapped in a TOC0 format instead of the normal EGON
format. mkimage supports that for a while, but for that to work it
requires some private key in the current directory. This key is easily
On Fri, 31 May 2024 16:33:48 +0200
Tobias Schramm wrote:
Hi Tobias,
> This patchset adds support for Ethernet on V3s-based SoCs, adding in
> required clock gates, resets to the CCU driver and finally a matching
> configuration for the sun8i_emac driver.
Michael already sent identical patches
ow very easy, and we will
> > need it soon enough.
> > The other AXP SPL drivers are more complex, and support more regulators,
> > but my hunch is that we really just need the DC/DC converters in the
> > SPL. However I need to prove and test this, so I will convert the othe
the position in the array for the index we keep
the code cleaner.
Signed-off-by: Andre Przywara
---
drivers/power/axp_spl.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/power/axp_spl.c b/drivers/power/axp_spl.c
index e38895c5c7d..8c9698612b5 100644
--- a/drivers
for the index we keep
the code cleaner.
Also remove the old driver, and switch the Makefile to include the new,
generic driver.
Signed-off-by: Andre Przywara
---
drivers/power/Makefile | 2 +-
drivers/power/axp305.c | 82 -
drivers/power/axp_spl.c | 15
3
version.
Signed-off-by: Andre Przywara
---
drivers/power/Makefile | 2 +-
drivers/power/axp313.c | 133
drivers/power/axp_spl.c | 13
3 files changed, 14 insertions(+), 134 deletions(-)
delete mode 100644 drivers/power/axp313.c
diff --git a/drivers
We now have a generic AXP SPL driver implementation, that already covers
the DC/DC converters of the AXP717 PMIC.
Remove the old, dedicated driver and switch to the new generic driver.
This should not introduce any change in behaviour.
Signed-off-by: Andre Przywara
---
drivers/power/Makefile
, that exports axp_set_dcdc() functions to set up
the buck converters. For now this just contains the bits for the (new)
AXP717, but it's not wired up anywhere yet.
Signed-off-by: Andre Przywara
---
drivers/power/axp_spl.c | 141
1 file changed, 141 insertions
The axp.c drivers are only used for the SPL, for U-Boot proper we
have a separate, DM compliant driver.
Mask the build instructions with CONFIG_SPL_BUILD, to avoid them being
build for U-Boot proper as well.
Signed-off-by: Andre Przywara
---
drivers/power/Makefile | 2 ++
1 file changed, 2
regulators,
but my hunch is that we really just need the DC/DC converters in the
SPL. However I need to prove and test this, so I will convert the other
AXP chips later.
Please have a look and comment whether the approach in general is a good
idea.
Cheers,
Andre
Andre Przywara (6):
power: pmic
his would be all we need, but
indeed everything else falls into place, when none of the newer SoCs are
used.
Regression-tested on an H616.
> SPI boot was tested on a custom board with a Gigadevice GD25Q64 8MiB
> SPI flash.
>
> Signed-off-by: Michael Walle
Reviewed-by: Andre Prz
for that SoC.
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> drivers/net/sun8i_emac.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
> index 8bff4fe9a9e..94bcd40acb8 100644
> --- a/drivers/net/sun8i_emac.c
Linux driver:
Reviewed-by: Andre Przywara
Thanks!
Andre
> ---
> drivers/clk/sunxi/clk_v3s.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
> index 6524c13540e..0402d5ed190 100644
> --- a/drivers/clk/su
The X-Powers AXP717 is a PMIC with four buck converters and a number
of LDOs, one of which is actually fixed (so not modelled here).
Add the compatible string and the respective regulator ranges to allow
drivers to adjust voltages.
Signed-off-by: Andre Przywara
---
drivers/power/pmic/axp.c
for the DRAM chips and the CPU cores.
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/pmic_bus.c | 3 ++
board/sunxi/board.c| 2 +-
drivers/power/Kconfig | 17 +--
drivers/power/Makefile | 1 +
drivers/power/axp717.c | 92
the Anbernic handheld gaming devices.
Add AXP717 support to the DM driven AXP regulator driver, and also an SPL
version, as we need to program the DRAM voltage rail correctly before
attempting to initialise the DRAM controller.
Cheers,
Ander
Andre Przywara (2):
power: pmic: sunxi: add AXP717 SPL
d.
Extend the existing offset calculation code to consider the different
sector offset when running on an H616 SoC. This allows to load U-Boot
on any H616 device when the SPL is not located at 8KB.
Signed-off-by: Andre Przywara
---
arch/arm/mach-sunxi/board.c | 5 -
1 file changed, 4 insert
CONFIG_SYSRESET_PSCI up into an SPL and a U-Boot proper version,
and let the former *depend* on SPL_ARM_PSCI_FW.
This allows to enable CONFIG_SYSRESET_PSCI on platforms without SPL PSCI
support.
Signed-off-by: Andre Przywara
---
changelog v1 ... v2:
- change name of symbol to comply with CONFIG_$(SPL_TPL_
it from this change as well, but this
needs some testing and can easily be a separate patch.
> Signed-off-by: Peter Hoyes
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> arch/arm/cpu/armv8/Kconfig | 8
> arch/arm/cpu/armv8/generic_timer.c | 27 ++
01/33,
I compiled all 168 sunxi boards successfully.
> Signed-off-by: Tom Rini
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> Cc: Jagan Teki
> Cc: Andre Przywara
> ---
> arch/arm/cpu/armv7/sunxi/psci.c | 1 -
> arch/arm/cpu/armv7/sunxi/sra
On Tue, 23 Apr 2024 09:10:05 +0100
Peter Hoyes wrote:
Hi,
> From: Peter Hoyes
>
> Polling cntpct_el0 in a tight loop for delays is inefficient.
> This is particularly apparent on Arm FVPs, which do not simulate
> real time, meaning that a 1s sleep can take a couple of orders
> of magnitude
ouldn't come up with a reason why "sev" would need
one as well, so even while the kernel has this, this seems to be more a
copy incident rather than something intentional.
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> arch/arm/include/asm/system.h | 9 +
&
On Tue, 23 Apr 2024 19:01:44 -0600
Tom Rini wrote:
Hi Tom,
> On Wed, Apr 24, 2024 at 12:46:04AM +0100, Andre Przywara wrote:
> > At the moment enabling CONFIG_SYSRESET_PSCI *selects* SPL_ARM_PSCI_FW,
> > even though this is a platform design property, so nothing any driver
>
On Tue, 23 Apr 2024 12:55:55 +0200
Quentin Schulz wrote:
> Hi Peter,
>
> On 4/23/24 10:10, Peter Hoyes wrote:
> > From: Peter Hoyes
> >
> > Polling cntpct_el0 in a tight loop for delays is inefficient.
> > This is particularly apparent on Arm FVPs, which do not simulate
> > real time, meaning
later.
Signed-off-by: Andre Przywara
---
arch/arm/dts/sun50i-h313-tanix-tx1.dts | 183 +
1 file changed, 183 insertions(+)
create mode 100644 arch/arm/dts/sun50i-h313-tanix-tx1.dts
diff --git a/arch/arm/dts/sun50i-h313-tanix-tx1.dts
b/arch/arm/dts/sun50i-h313-tanix-tx1.dts
defconfig for that board, and add the devicetree file to the
Makefile, for it to be built.
The DRAM parameters were taken from the vendor firmware on the eMMC.
Signed-off-by: Andre Przywara
---
arch/arm/dts/Makefile | 1 +
configs/tanix_tx1_defconfig | 25 +
2 files changed, 26
on to kernels.
This also adds new devicetrees, for some LonganPi H616 board, and the
Remix Mini PC. The latter will get a defconfig next.
As before, this omits the non-backwards compatible changes to the R_INTC
controller, to remain compatible with older kernels.
Signed-off-by: Andre Przywara
---
arch
cal TV box.
The devicetree file has been imported from the Linux tree already, so
just add a defconfig and enable the DTB build in the Makefile. The SoC
has the "secure boot" fuse burnt, so we need to generate a TOC0 image
instead of the standard Allwinner eGON image format for the SPL.
Signed-of
sktop" device from 2015, and the Tanix TX1,
which is a tiny TV box with an H313 SoC.
The DT for the latter is preliminary for now, as it hasn't been merged
into Linus' tree yet - though that's supposed to happen in about a few
weeks time.
Please have a look!
Cheers,
Andre
Andre Przywara (4):
CONFIG_SYSRESET_PSCI up into an SPL and a U-Boot proper version,
and let the former *depend* on SPL_ARM_PSCI_FW.
This allows to enable CONFIG_SYSRESET_PSCI on platforms without SPL PSCI
support.
Signed-off-by: Andre Przywara
---
drivers/sysreset/Kconfig | 8 +++-
drivers/sysreset/Makefile | 2 +-
2 files
to fetch changes up to 192c5c9e51c1ef100c3d027d253ffad26ff75a68:
sunxi: sun9i: make more clock functions SPL only (2024-04-22 01:12:26 +0100)
Andre Przywara (9):
usb: musb-new: add Allwinner F1C100s support
sunxi: move
On Wed, 13 Mar 2024 13:33:23 +0800
lhdj...@126.com wrote:
Hi,
> From: lhdjply
>
> 111
There should be a proper commit message here, explaining *why* this
patch is needed.
So what does this patch or which problem does it solve?
Please note that I consider those "SUNxx_GPy_UARTz" symbols
On Fri, 9 Jun 2023 13:37:16 +
路辉 wrote:
Hi,
> From 570b40e19de75511d9ce066e1a28333ada04baf2 Mon Sep 17 00:00:00 2001
> From: Lu Hui
> Date: Mon, 29 May 2023 22:26:25 +0800
> Subject: [PATCH] drivers: pinctrl-sunxi: add suniv spi1 function
There should be a commit message, explaining *why*
On Sat, 13 Apr 2024 21:43:52 +0800
da...@189.cn wrote:
Hi,
thanks for sending a patch!
> From: lalakii
>
> Add "DRAM_SUN50I_H616_TRIM_SIZE" option for 1.5gb board.
>
> Signed-off-by: lalakii
> ---
> arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h | 1 +
> arch/arm/mach-sunxi/Kconfig
On Thu, 11 Apr 2024 14:31:02 +1000
John Watts wrote:
Hi,
> Hi there,
>
> I've been using my own independent implementation of this patch but
> today I gave this one a test in my tree and found out it works.
>
> The code looks fine in comparison, so here's a Tested-by and a
> Reviewed-by.
>
>
On Thu, 11 Apr 2024 15:14:14 +1000
John Watts wrote:
Hi John,
> The T113 supports UART1 and UART2 on PG and PD pins respectively.
> Add support for these in U-Boot so we can use them.
So those bits are just for the *debug* UARTs. Traditionally this is UART0,
with some particular pinmux,
On Wed, 20 Mar 2024 11:33:16 -0400
Tom Rini wrote:
Hi,
> On Wed, Mar 20, 2024 at 08:52:30PM +0530, Devarsh Thakkar wrote:
> > Hi Tom, Lukas,
> >
> > Thanks for the patch Lukas.
> >
> > On 20/03/24 20:00, Tom Rini wrote:
> > > On Wed, Mar 20, 2024 at 02:19:26PM +0100,
bled and locked bootloader, so
> the u-boot has to be built with TOC0.
> DRAM settings are taken from Allwinner's boot0 for this box.
Ah, thanks for figuring those out, that's very helpful.
>
> Cc: Andre Przywara
>
> Signed-off-by: Kamil Kasperski
> ---
> arch/arm/dts/Make
5 01:16:56 +)
--------
Andre Przywara (1):
sunxi: H616: Add OrangePi Zero 2W board support
Andrey Skvortsov (2):
sunxi: reorganize mctl_mem_matches_* functions
sunxi: restore modified memory
Ludwig Kormann (1):
su
es like soft reset and Linux's ramoops mechanism.
>
> Fix this problem by saving and restoring the content of the DRAM cells
> that is used for the test writes.
>
> Signed-off-by: Andrey Skvortsov
Reviewed-by: Andre Przywara
Merged to sunxi/master.
Cheers,
Andre
&
ortsov
thanks for the changes, that looks good now!
Reviewed-by: Andre Przywara
Merged to sunxi/master.
Cheers,
Andre
> ---
> arch/arm/include/asm/arch-sunxi/dram.h | 1 +
> arch/arm/mach-sunxi/dram_helpers.c | 20 ++--
> arch/arm/mach-sunxi/dram_sunxi_dw.c|
On Thu, 15 Feb 2024 17:56:10 +0100
Frieder Schrempf wrote:
Hi Frieder,
> On 15.02.24 17:50, Andre Przywara wrote:
> > On Thu, 15 Feb 2024 14:35:19 +0100
> > Frieder Schrempf wrote:
> >
> >> From: Frieder Schrempf
> >>
> >> The datasheet
On Thu, 15 Feb 2024 14:35:19 +0100
Frieder Schrempf wrote:
> From: Frieder Schrempf
>
> The datasheet can be found here:
> https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf
>
> Signed-off-by: Frieder Schrempf
> Reviewed-by: Fabio Estevam
> ---
> Changes in v3:
> * none
ation of
> >>>>>>>>>> reset some USB 2.0 disks weren't detected on
> >>>>>>>>>> Allwinner based boards.
> >>>>>>>>>>
> >>>>>>>>>> Resetting only when hub is USB 3.0 fixes it
On Mon, 12 Feb 2024 13:40:31 -0500
Tom Rini wrote:
> On Sat, Feb 10, 2024 at 05:37:03PM +0000, Andre Przywara wrote:
>
> > On Mon, 4 Dec 2023 01:09:30 +0000
> > Andre Przywara wrote:
> >
> > Hi Joe, Ramon, Tom,
> >
> > for some reason patchwo
maximum slope the
> AXP209 supports.
>
> Link: https://bugs.debian.org/1060752
> Cc: Olliver Schinagl
> Cc: Priit Laes
> Cc: Maxime Ripard
> Signed-off-by: Philippe Coval
Thanks for the changes, this looks good to me now.
Reviewed-by: Andre Przywara
I w
On Mon, 12 Feb 2024 01:38:36 +0300
Andrey Skvortsov wrote:
Hi Andrey,
> thank you for the valuable feedback!
>
> On 24-02-11 13:13, Andre Przywara wrote:
> > On Sun, 11 Feb 2024 12:28:24 +0300
> > Andrey Skvortsov wrote:
> >
> > Hi Andrey,
> >
>
On Sun, 11 Feb 2024 12:28:24 +0300
Andrey Skvortsov wrote:
Hi Andrey,
thanks for taking care of this upstream!
> In newer 1.2 PinePhone board revisions LIS3MDL magnetometer was replaced by
> AF8133J. They use the same PB1 pin in different modes.
>
> LIS3MDL uses it as an gpio input to handle
On Mon, 4 Dec 2023 01:09:30 +
Andre Przywara wrote:
Hi Joe, Ramon, Tom,
for some reason patchwork put this on my plate, but it looks like
genuine network code to me, and the problem definitely doesn't affect
sunxi.
As tagged below, I am happy with this change, so if there are no
objections
On Fri, 02 Feb 2024 03:35:24 +0100
Dragan Simic wrote:
Hi,
> Hello Andre,
>
> On 2024-02-02 01:12, Andre Przywara wrote:
> > On Thu, 1 Feb 2024 18:35:28 + Shantur Rathore
> > wrote:
> >> On Thu, Feb 1, 2024 at 4:46 PM Andre Przywara
> >> wrot
On Thu, 1 Feb 2024 18:35:28 +
Shantur Rathore wrote:
Hi Shantur,
> Hi Andre,
>
> On Thu, Feb 1, 2024 at 4:46 PM Andre Przywara wrote:
> >
> > On Thu, 1 Feb 2024 09:39:54 +
> > Shantur Rathore wrote:
> >
> > Hi Shantur,
> >
> &g
On Mon, 22 Jan 2024 22:15:30 +0100
patrick9...@free.fr wrote:
Hi Patrick,
> From: Patrick Lerda
>
> Indeed, the DDR3 has a non-zero probability to not be properly
> initialized. This could be the PLL that is not locked or anything else.
> When this happens and the code tests the correct board
On Thu, 1 Feb 2024 09:39:54 +
Shantur Rathore wrote:
Hi Shantur,
> On Tue, Jan 30, 2024 at 2:01 PM Andre Przywara wrote:
> >
> > On Sat, 9 Dec 2023 18:10:56 +
> > Shantur Rathore wrote:
> >
> > Hi,
> >
> > > Currently wh
On Thu, 1 Feb 2024 14:30:14 +0100
Ludwig Kormann wrote:
Hi,
> This option can be used to modify the initial SPL
> CPU clock frequency.
>
> This follows an earlier discussion regarding A20
> CPUs dying after reboot in SPL initialization due to
> incompatible CPU clock frequency and core
running
> clock cycles.”
>
> This is already implemented in clock_set_pll1(), but was
> still missing in clock_init_safe().
>
> Signed-off-by: Ludwig Kormann
Good catch, thanks for sending this!
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> arch/arm/mach-sunxi/cl
On Wed, 31 Jan 2024 14:26:02 +0100
Ludwig Kormann wrote:
Hi,
> thanks for your feedback!
thanks for the quick reply!
> Am 31.01.24 um 13:36 schrieb Andre Przywara:
> > On Wed, 31 Jan 2024 11:49:43 +0100
> > Ludwig Kormann wrote:
> >
> > Hi Ludwig,
> >
&g
On Wed, 31 Jan 2024 11:49:43 +0100
Ludwig Kormann wrote:
Hi Ludwig,
thanks for taking care and sending a patch, though I scratch my head about
this a bit. My main concern is why this would be an issue *now*, 11 years
after the A20's release, and with tons of boards out there in operation.
Also
to the Makefile to actually build the .dtb.
The DRAM parameters were derived from the values found in the BSP DRAM
drivers on the SPI NOR flash.
Signed-off-by: Andre Przywara
---
arch/arm/dts/Makefile | 1 +
board/sunxi/MAINTAINERS | 5 +
configs/orangepi_zero2w_defconfig
On Sat, 9 Dec 2023 18:10:56 +
Shantur Rathore wrote:
Hi,
> Currently when a hub is turned on, all the ports are powered on.
> This works well for hubs which have individual power control.
>
> For the hubs without individual power control this has no effect.
> Mostly in these scenarios the
On Tue, 31 Oct 2023 01:39:53 -0500
Samuel Holland wrote:
Hi Samuel,
> The device tree binding for the PHY provides VBUS supplies as regulator
> references. Now that all boards have the appropriate regulator uclass
> drivers enabled, the PHY driver can switch to using them. This replaces
>
On Mon, 29 Jan 2024 12:34:18 -0500
Tom Rini wrote:
Hi Tom,
> On Mon, Jan 29, 2024 at 05:24:49PM +0000, Andre Przywara wrote:
> > On Mon, 29 Jan 2024 15:55:43 +
> > Andre Przywara wrote:
> >
> > Hi Tom,
> >
> > > please pull the sunx
On Mon, 29 Jan 2024 15:55:43 +
Andre Przywara wrote:
Hi Tom,
> please pull the sunxi/master branch, containing the first part of the
I just saw that the CI pipeline failed on missing maintainer entries for
the two new boards. Is that a showstopper for you? Shall I update the
bra
On Tue, 31 Oct 2023 00:17:40 -0500
Samuel Holland wrote:
Hi,
> Some 32-bit SoCs can use SCP firmware to implement additional PSCI
> functionality, such as system suspend. In order to load this firmware
> from SPL, we need to generate and use a FIT instead of a legacy image.
>
> Adjust the
On Sun, 21 Jan 2024 01:15:28 +
Andre Przywara wrote:
Hi,
> On Thu, 28 Dec 2023 13:29:15 +0800
> Chuanhong Guo wrote:
>
> Hi,
>
> thanks for taking care and sending a patch!
>
> > FriendlyElec NanoPi Duo2 is a tiny SBC with Allwinner H3 and
> > Ampak AP
On Thu, 18 Jan 2024 17:56:55 +
Andre Przywara wrote:
> On Thu, 18 Jan 2024 11:45:08 -0500
> Nick Alilovic wrote:
>
> Hi Nick,
>
> > This is a Chinese TV box based on Allwinner H618 SoC.
> >
> > The DRAM parameters were derived from the values found in a
On Wed, 17 Jan 2024 00:19:05 +
Andre Przywara wrote:
Hi,
> On Fri, 8 Dec 2023 01:39:45 +
> Andre Przywara wrote:
>
> Hi Samuel,
>
> > On Tue, 31 Oct 2023 00:17:41 -0500
> > Samuel Holland wrote:
> >
> > Hi,
> >
> > > Now
:
sunxi: Consider SPL size limitations for FIT loading (2024-01-29 14:31:00
+)
----
Andre Przywara (7):
sunxi: cleanup sunxi-common.h
sunxi: sun50i-h6: remove unneeded base addresses from header
sunxi: sun4i:
. Otherwise, phyaddr initialization will not be necessary,
> as it is not needed in case of a fixed-link config.
>
> Signed-off-by: Maksim Kiselev
Thanks, looks good now:
Reviewed-by: Andre Przywara
Queued for the first PR.
Cheers,
Andre
> ---
> drivers/net/sun8i_emac.c | 7 ++-
> 1 fi
y: Maksim Kiselev
Reviewed-by: Andre Przywara
> ---
>
> I tested this patch on LC-PI-T113 board.
> This board can be found on eBay or Aliexpress, and looks like
> that it is widespread enough to send this patch to the upstream :)
... it would be even better to have a DT and defcon
On Tue, 31 Oct 2023 01:39:52 -0500
Samuel Holland wrote:
Hi Samuel,
> On many boards, the USB ports are powered by the PMIC's "drivevbus"
> regulator. In preparation for switching the USB PHY driver to use the
> regulator uclass instead of a virtual GPIO pin, ensure these boards
> have AXP PMIC
On Mon, 22 Jan 2024 11:09:31 +
Andre Przywara wrote:
Hi,
I just realised that I forgot to CC: the linux-sunxi list on this.
Could anyone please have a brief look and confirm that I didn't miss
anything in this update? It's mostly about adding DTs for new boards, so
that we can add U-Boot
On Mon, 22 Jan 2024 11:49:59 -0500
Tom Rini wrote:
Hi Tom,
> On Mon, Jan 22, 2024 at 11:45:15AM +0000, Andre Przywara wrote:
> > On Wed, 10 Jan 2024 16:05:36 +0530
> > Sumit Garg wrote:
> >
> > Hi,
> >
> > I certainly welcome this more automatic synch
On Wed, 10 Jan 2024 16:05:36 +0530
Sumit Garg wrote:
Hi,
I certainly welcome this more automatic synchronisation of the DTs,
however have one comment about the upcoming sync process:
> ...
> However, Linux kernel DT maintainers proposed [2] for U-Boot to rather
> use devicetree-rebasing repo
controller, to remain compatible with older kernels.
Signed-off-by: Andre Przywara
---
.../dts/sun50i-h616-bigtreetech-cb1-manta.dts | 35 +++
arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi | 138 +
arch/arm/dts/sun50i-h616-bigtreetech-pi.dts | 63
arch/arm/dts/sun50i-h616.dtsi
On Thu, 28 Dec 2023 13:29:15 +0800
Chuanhong Guo wrote:
Hi,
thanks for taking care and sending a patch!
> FriendlyElec NanoPi Duo2 is a tiny SBC with Allwinner H3 and
> Ampak AP6212 WiFi module. The device-tree for it is already
> available in u-boot source tree. Add a default config for it.
>
On Fri, 19 Jan 2024 21:11:07 +0300
Maxim Kiselev wrote:
Hi Maxim,
> пт, 19 янв. 2024 г. в 20:35, Andre Przywara :
> >
> > On Tue, 16 Jan 2024 19:58:56 +0300
> > Maxim Kiselev wrote:
> >
> > Hi Maxim,
> >
> > > вт, 16 янв. 2024 г. в 03:18, A
On Tue, 16 Jan 2024 19:58:56 +0300
Maxim Kiselev wrote:
Hi Maxim,
> вт, 16 янв. 2024 г. в 03:18, Andre Przywara :
> >
> > On Thu, 15 Jun 2023 00:44:06 +0300
> > Maxim Kiselev wrote:
> >
> > Hi Maxim,
> >
> > > From: Maksim Kiselev
> > &g
now:
Reviewed-by: Andre Przywara
I will queue this after the DT files have been merged.
Cheers,
Andre
> ---
> This defconfig relies on the synced sun50i-h618-transpeed-8k618-t.dts file.
>
> configs/transpeed-8k618-t_defconfig | 27 +++
> 1 file changed, 27 inser
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