Hi Marek,
>> Just check if the mainline SPL generated from this branch works on your
>> platform please.
I tested U-boot generated from the branch you specified:
U-Boot 2016.03-11349-g5d09125-dirty (Apr 09 2016 - 00:42:24 +0200)
Works pretty well.
All needed functionality works for me. I tested
> Just check if the mainline SPL generated from this branch works on your
> platform please.
Ok. I will test it but probably during the weekend.
Because it requires me to merge my configuration to it.
I will write back once I will have some results.
Best regards,
Denis Bakhvalov
_
Hi Marek,
> you mentioned you have problems with DRAM init on your AV, right ?
> Try this u-boot-socfpga/ddr branch [1] , see if it works for you and
> please let me know. The more testing the better.
>
> [1]
> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr
Are you a
Hi Marek,
> Do "dcache off" and then update the flash again, it will work. That's
> the cache issue which we cannot track down.
Thank you for you quick support!
Maybe it's worth to invent a temporary solution?
Because in other way users will face problems which are hard to find (I've been
chasi
Dear U-Boot support,
I'm migrating to new U-Boot version from 2013 and now have problem with writing
to the flash.
I have custom board with Altera Arria 5 SocFpga.
U-Boot version: 2016.03-rc1
My flash:
SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB, total
64 MiB
I'm r
CONFIG_SPI_FLASH_BAR was deleted from socfpga_common.h
and placed in socfpga_*_defconfig where it makes sense.
Signed-off-by: Denis Bakhvalov
Reported-by: Denis Bakhvalov
Cc: Marek Vasut
---
configs/socfpga_arria5_defconfig | 1 +
configs/socfpga_cyclone5_defconfig | 1 +
configs/soc
Hi
> > It's I belive in socfpga_common.h and it should be migrated to
> > socfpga_*_defconfig where it makes sense. Do you want to submit
> > a patch for this ?
>
> I put it in my todo list.
> Once I will finish with u-boot bringup I will submit the patch.
> Currently I have Ethernet not working
CONFIG_SPI_FLASH_BAR was deleted from socfpga_common.h
and placed in socfpga_*_defconfig where it makes sense.
Signed-off-by: Denis Bakhvalov
Reported-by: Marek Vasut
Cc: Dinh Nguyen
---
configs/socfpga_arria5_defconfig | 1 +
configs/socfpga_cyclone5_defconfig | 1 +
configs/socfpga
Hi,
Working perfectly!
Thanks for helping me remove this nasty workaround.
> We should parse the OF node phy-mode, which describes which mode your
> PHY uses.
Right!
Best regards,
Denis Bakhvalov
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Hello Dear U-Boot support,
Please comment on this also.
I have custom board with Altera Arria 5 SocFpga onboard.
U-Boot version: 2016.03-rc1
I had probems with configuring fpga from u-boot:
U-Boot > bridge disable
U-Boot > run config_fpga
FPGA: Could not configure
Command failed, result=-2
So,
Hi,
I solved the Ethernet problem on our board.
The problem was in the register below:
Link:
http://wl.altera.com/literature/hb/arria-v/hps.html#topic/sfo1410067853518.html
Registers used by the EMACs. All fields are reset by a cold or warm reset.
Module Instance Base AddressRegister Addres
Hi,
> Why are you constantly hung on this FPGA part ? The ethernet is not
> routed through the FPGA, it is connected directly to the HPS. Thus,
> you don't have to care about the FPGA at all, you only care about the
> configuration of the HPS.
Please excuse me for my small experience in this topi
Hi Marek, Dinh,
> Are you booting using mainline U-Boot SPL ? :-)
No, we use SPL from U-Boot 2013.
I can quess what you will say now, but it somehow worked before (combination
SPL + U-Boot from 2013).
Is there a way to capture fpga dumps?
I can then compare them to working case.
I can assume t
Hi Marek,
> Perform usual test, disable cache (dcache off) .
I tried and result is still the same.
UPD: I did a little trick:
1. I started ping from the board side. That made the board listen to incoming
packets (calling in infinite loop eth_rx() ).
2. Started ping from PC side.
3. In this case
Hi,
> However there is still no ping in U-Boot.
> After power reset I did:
>
> ># bridge disable
> ># fpga load 0
> ># bridge enable
>
> ># md 0xff706000 1
> ff706000: 0074 <-- this means fpga is in user mode
>
> ># setenv ethaddr ...
> ># setenv ipaddr ...
> ># setenv netmask ...
>
Hi Marek,
> What do you mean by this ? Is your ethernet controller synthesised in
> the FPGA ? The arriaV socdk u-boot uses the top-side ethernet port,
> which is connected to the ethernet controller in the HPS.
I managed to get it working.
Right after configuring fpga from Linux I made a soft re
Hi,
> It seems like your PHY is not recongnised. Could there be some reset
> line which is left asserted ?
I'm afraid I don't know how to check that.
But I have previous version of U-Boot (2013) where Ethernet is working.
Maybe I can check it there?
I already tried to go that path, but code is q
rmail/u-boot/2016-March/247290.html
Let's continue discussion there. :)
Best regards,
Denis Bakhvalov
MBB Radio Platforms, RFSW
-Original Message-
From: EXT Marek Vasut [mailto:ma...@denx.de]
Sent: Friday, March 04, 2016 13:20
To: Bakhvalov, Denis (Nokia - PL/Wroclaw) ; EXT
Dear U-Boot support,
I'm migrating to new U-Boot version from 2013 and now have Ethernet not working
both in U-Boot and in Linux (after booting).
I have custom board with Altera Arria 5 SocFpga onboard.
U-Boot version: 2016.03-rc1
In logs I can see:
Net: No ethernet found.
With more verbos
Hi Marek,
> It's I belive in socfpga_common.h and it should be migrated to
> socfpga_*_defconfig where it makes sense. Do you want to submit
> a patch for this ?
I put it in my todo list.
Once I will finish with u-boot bringup I will submit the patch.
Currently I have Ethernet not working :(
B
Hi Jagan,
> Sorry, I couldn't understand the issue nor what you solved? because,
> socfpga_arria5_defconfig by default have CONFIG_SPI_FLASH_BAR enabled
> and even sf probe looks no warning for enabling the same. If you
> haven't enable CONFIG_SPI_FLASH_BAR then spi_flash core will give
> warning
Hi Marek,
>Try enabling CONFIG_SPI_FLASH_BAR in your board config ;-)
That solved my issue.
Thank you very much.
I removed workaround from the code.
Best regards,
Denis Bakhvalov
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Hi Jagan, Heiko,
> Did you enable CONFIG_SPI_FLASH_SPANSION on your config, becuase
> S25FL512S is already been added u-boot. Pls- check the same and let me
> know if you find any issues while detecting the flash.
> Whether the driver detecting flash or not with RDID, please define
> DEBUG on dri
Hello Heiko,
> Which U-Boot version? Which board?
This is U-Boot v2016.03-rc1.
I have custom board with socfpga Arria5 onboard.
> Where does this leading 0xff come from? There seems a problem
> with your spi nor flash driver?
Yes, you're right. I have problems with the driver.
As I mentioned in
Hi,
I found that I have problem with reading flash contents:
When dumping the flash from Linux env:
$ cat /dev/mtd5 > /tmp/flash.bin
: 55424923 0100 0003
But when I dump the flash contents from U-Boot I see this:
=> sf read 0x1B00 0x01B0 0x1000
=> md 0x1B0
Dear U-Boot support,
I have problems while running following commands in U-Boot:
U-Boot => sf probe 0 0 0
SF: Detected S25FL512S with page size 512, total: 67108864
U-Boot => mtdparts
device nor0 , # parts = 4
#: namesizeoffset mask_flags
0: boot
Hi Marek,
> That's fine, just check if you did some modifications to the altera fork
> of u-boot. Especially interesting would be PLL/pinmux/DRAM config.
I tried to launch altera branch from here:
https://github.com/altera-opensource/u-boot-socfpga.
It didn't work out of the box as well.
I will
Hi Marek,
> > Press the "WARM RESET" button of the HPS (located top-right, if you have
> > the board oriented with HPS ethernet on the top-left). Do you
> > see any console output then ? You do use the top-right miniUSB port
> > for console, right ?
>
> Currently board is integrated in RF unit. I
> > I tried mainline U-boot with your patches as well as socfpga branch.
> > Still no success.
>
> Did you try the image I sent you ? That one is tested to work on AV SoCDK.
I tried it also. The same result.
> > There is no output on the console.
> > Once again when I'm uploading old version of U
Hi Marek,
I tried mainline U-boot with your patches as well as socfpga branch.
Still no success.
There is no output on the console.
Once again when I'm uploading old version of U-boot and preloader (from 2013)
at least I can see the output on the console.
What could be the next step?
Best regar
> There is output, but it takes a while for the USB-to-UART chip to kick
> in after restart, so you don't see it. I will send you two more patches,
> so apply them and it should get you up and running. The QSPI NOR boot
> was not enabled on AV/CV SoCDK.
> You can also grab the latest stuff here:
>
$ quartus_hps -c 1 -o PV -a 0x0 u-boot-with-spl.sfp.bin
// here ".bin" because current programmer requires so. I think it shouldn't be
a problem.
>From manual:
"HPS Flash Programmer
The utility accepts a Binary File with a required ".bin" extension.
The HPS flash programmer command-line syntax is
Sorry.
My bad.
Best regards,
Denis Bakhvalov
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n ;
Chin Liang See ; Bakhvalov, Denis (Nokia - PL/Wroclaw)
Subject: [PATCH] arm: socfpga: Add missing CONFIG_BUILD_TARGET
Add the missing CONFIG_BUILD_TARGET to get u-boot-with-spl.sfp built
automatically upon running make in the source tree.
Signed-off-by: Marek Vasut
Cc: Dinh Nguyen
C
Hi Marek,
Here are my build steps:
denis@DendiMachine:~/WorkSpace/u-boot$ make clean
CLEAN dts/../arch/arm/dts
CLEAN dts
CLEAN examples/standalone
CLEAN tools
CLEAN tools/lib tools/common
CLEAN spl/arch spl/board spl/cmd spl/common spl/drivers spl/dts spl/fs
spl/lib spl/u
Hi Marek,
> Please just use mainline everything. If you use Arria V SoCDK, you can
> just grab 2016.01 , compile it and write u-boot-with-spl-dtb.sfp to
> offset 0x0 of the QSPI and it should just magically work.
I haven't found the file with the name u-boot-with-spl-dtb.sfp.
denis@DendiMachine:
Hi Marek,
> That's not mainline SPL. Please use mainline SPL with mainline U-Boot.
> Mixing and matching various versions of U-Boot and SPL is not supported.
> Is there any reason why you are using non-mainline SPL ?
We received information from Altera that we should stick to this previous
vers
Hi,
Thank you for you responses!
@To Marek:
> It would be very helpful to see the whole boot output, not just U-Boot output.
> For example SPL output is missing. Are you using mainline U-Boot SPL or not ?
Here is the output from SPL:
U-Boot SPL 2013.01.01-svn564 (May 27 2015 - 17:58:12)
Board
Hi Wolfgang,
Thank you for your quick reply.
> 1) Is there any specific reason for using JFFS2? We consider this
> pretty much deprecated today and usually tend to prefer UBI/UBIFS.
Yes, I'm aware that jffs2 is quite old and ubifs is a successor of jffs2, but
the reason is that current Linux
Dear U-boot Support,
My name is Denis and I'm representing Nokia.
We want to have flexibility in choosing which Linux kernel image to load for
different HW configurations.
But we don't want to define several partitions and use hardcoded addresses on
the flash to fetch the needed
Linux kernel im
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