On 23.02.2023 13:28, Mihai Sain wrote:
> The PMC_MCK1 clock id for the ebi node is 23.
>
> Fixes: 4ce85577ac ("ARM: dts: at91: sama7g5/sama7g5ek: align with Linux DT")
> Signed-off-by: Mihai Sain
Reviewed-by: Claudiu Beznea
> ---
> arch/arm/dts/sama7g5.dtsi | 2 +-
> 1 file changed, 1
On 24.01.2023 00:00, Simon Glass wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> The SPL_TPL part is in the wrong place. Fix it.
>
> Signed-off-by: Simon Glass
> Fixes: 71d4393f846 ("sysreset: Add Atmel/Microchip sysreset driver")
On 23.12.2022 14:33, Sergiu Moga wrote:
> Add the configs required to use the SAM9X60's USB clock.
>
> Signed-off-by: Sergiu Moga
Reviewed-by: Claudiu Beznea
> ---
> configs/sam9x60_curiosity_mmc_defconfig | 1 +
> configs/sam9x60ek_mmc_defconfig | 1 +
>
On 23.12.2022 14:33, Sergiu Moga wrote:
> In order for some of the functionalities, such as the USB clocks,
> to work properly we need some clocks to be properly initialised
> at the very beginning of booting.
>
> Signed-off-by: Sergiu Moga
Reviewed-by: Claudiu Beznea
> ---
>
On 23.12.2022 14:33, Sergiu Moga wrote:
> Register into DM the clocks required to properly enable USB functionality
> within the bootloader.
>
> Signed-off-by: Sergiu Moga
Reviewed-by: Claudiu Beznea
> ---
> drivers/clk/at91/sam9x60.c | 33 +
> 1 file
On 23.12.2022 14:33, Sergiu Moga wrote:
> Implement sam9x60 USB clock driver. This clock has
> three parents: PLLA, UPLL and MAINXTAL. The driver is
> aware of the three possible parents with the help of the
> two mux tables provied to the driver during the registration
> of the clock.
>
>
On 12.12.2022 15:39, Sergiu Moga wrote:
> In order to have USB functionality, drivers for SAMA7's
> USB 2.0 PHY's have been added. There is one driver
> for UTMI clock's SFR and RESET required functionalities and
> one for its three possible subclocks of the phy's themselves.
> In order for this
On 08.12.2022 11:47, Sergiu Moga wrote:
> Add support for at91 reset controller's basic assert/deassert
> operations. Since this driver conflicts with the
> SYSRESET driver because they both bind to the same RSTC node,
> implement a custom bind hook that would manually bind the
> sysreset driver,
On 08.12.2022 11:47, Sergiu Moga wrote:
> Implement sam9x60 USB clock driver. This clock has
> three parents: PLLA, UPLL and MAINXTAL. The driver is
> aware of the three possible parents with the help of the
> two mux tables provied to the driver during the registration
> of the clock.
>
>
On 12.12.2022 11:59, Eugen Hristev wrote:
> The PMC node is not an interrupt provider, so it must not have
> interrupt-cells.
>
> This fixes the warning (on newer DTC):
> arch/arm/dts/sama5d2.dtsi:82.22-602.6: Warning (interrupt_provider):
> /ahb/apb/pmc@f0014000: '#interrupt-cells' found, but
On 25.11.2022 09:54, Eugen Hristev wrote:
> Copy include file dt-bindings/mfd/at91-usart.h from Linux
>
> Signed-off-by: Eugen Hristev
Reviewed-by: Claudiu Beznea
> ---
> include/dt-bindings/mfd/at91-usart.h | 17 +
> 1 file changed, 17 insertions(+)
> create mode 100644
On 25.11.2022 09:54, Eugen Hristev wrote:
> As documented in bindings doc in kernel 6.0:
> https://elixir.bootlin.com/linux/v6.0/source/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
>
> Signed-off-by: Eugen Hristev
Reviewed-by: Claudiu Beznea
> ---
>
On 25.11.2022 09:54, Eugen Hristev wrote:
> Align the DT with current Linux 6.1 tree, wherever possible.
>
> Signed-off-by: Eugen Hristev
Reviewed-by: Claudiu Beznea
> ---
> arch/arm/dts/at91-sama7g5ek.dts | 23 +++
> arch/arm/dts/sama7g5.dtsi | 27
On 17.08.2022 10:04, Eugen Hristev wrote:
> From: Mihai Sain
>
> ddrck and qspick should have mck_div as parent clocks to be in sync with
> linux driver.
>
> Signed-off-by: Mihai Sain
Reviewed-by: Claudiu Beznea
> ---
> drivers/clk/at91/sam9x60.c | 4 ++--
> 1 file changed, 2
On 23.03.2021 18:54, Manuel Luís Reis wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi again,
>
>> There are timers on the board. How come it used to work, before the
>> commit that breaks it ?
>>
>> I understand that nobody registers
Hi Eugen,
On 23.02.2021 11:41, Eugen Hristev - M18282 wrote:
> On 27.01.2021 15:00, Claudiu Beznea wrote:
>> SAMA7G5 supports slew rate configuration. Adapt the driver for this.
>> For switching frequencies lower than 50MHz the slew rate needs to
>> be enabled. Since most of the pins on SAMA7G5
On 07.10.2020 21:37, Sean Anderson wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> No timer drivers return an error from get_count. Instead of possibly
> returning an error, just return the count directly.
>
> Signed-off-by: Sean
On 07.10.2020 20:49, Sean Anderson wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 9/7/20 11:36 AM, Claudiu Beznea wrote:
>> Add support for Microchip PIT64B timer. The timer is 64 bit length and
>> is used as a free running counter
Hi Eugen,
On 06.10.2020 09:32, Eugen Hristev - M18282 wrote:
> On 05.10.2020 17:58, Claudiu Beznea wrote:
>> Add SAM9X60 clock support compatible with CCF.
>>
>> Signed-off-by: Claudiu Beznea
>> ---
>
> Hi Claudiu,
>
>> drivers/clk/at91/Makefile | 1 +
>> drivers/clk/at91/sam9x60.c |
Hi Eugen,
On 06.10.2020 09:39, Eugen Hristev - M18282 wrote:
> On 05.10.2020 17:58, Claudiu Beznea wrote:
>> Use u-boot,dm-pre-reloc for slow xtal and main xtal.
>>
>> Signed-off-by: Claudiu Beznea
>> ---
>
> Hi Claudiu,
>
> For this patch and the following DT patches:
>
> the
Hi Eugen,
On 22.09.2020 11:32, Eugen Hristev - M18282 wrote:
> On 07.09.2020 18:36, Claudiu Beznea wrote:
>> Add support for Microchip PIT64B timer. The timer is 64 bit length and
>> is used as a free running counter (in continuous mode with highest values
>> for period registers). The clock
Hi Simon,
On 05.08.2020 18:11, Claudiu Beznea wrote:
> Clock re-parenting is not binding the clock's device to its new
> parent device, it only calls the clock's ops->set_parent() API. The
> changes in this commit re-parent the clock device to its new parent
> so that subsequent operations like
On 04.08.2020 18:29, Simon Glass wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Claudiu,
>
> On Tue, 4 Aug 2020 at 09:25, wrote:
>>
>> Hi Simon,
>>
>> On 04.08.2020 18:08, Simon Glass wrote:
>>> EXTERNAL EMAIL: Do not click links
Hi Simon,
On 04.08.2020 18:08, Simon Glass wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Claudiu,
>
> On Tue, 4 Aug 2020 at 01:19, wrote:
>>
>>
>>
>> On 04.08.2020 05:00, Simon Glass wrote:
>>> EXTERNAL EMAIL: Do not click links
On 04.08.2020 05:00, Simon Glass wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Claudiu,
>
> On Wed, 29 Jul 2020 at 08:52, Claudiu Beznea
> wrote:
>>
>> clk_get_by_indexed_prop() retrieves a clock with dev member being set
>> with
On 04.08.2020 05:00, Simon Glass wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Claudiu,
>
> On Wed, 29 Jul 2020 at 08:51, Claudiu Beznea
> wrote:
>>
>> In common clock framework the relation b/w parent and child clocks is
>>
On 04.08.2020 05:00, Simon Glass wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On Wed, 29 Jul 2020 at 08:51, Claudiu Beznea
> wrote:
>>
>> Clock re-parenting is not binding the clock's device to its new
>> parent device, it only
On 04.08.2020 05:00, Simon Glass wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Claudiu,
>
> On Wed, 29 Jul 2020 at 08:51, Claudiu Beznea
> wrote:
>>
>> Check pointer returned by dev_get_parent().
>>
>> Signed-off-by: Claudiu
On 04.08.2020 05:00, Simon Glass wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Claudiu,
>
> On Wed, 29 Jul 2020 at 08:51, Claudiu Beznea
> wrote:
>>
>> Check hw and hw->dev before dereference it.
>>
>> Signed-off-by: Claudiu
From: Claudiu Beznea
Add drive strength support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea
---
drivers/pinctrl/pinctrl-at91.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
From: Claudiu Beznea
Add compatibles for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea
---
drivers/pinctrl/pinctrl-at91.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 134ee851d978..62ee7668ab17 100644
---
From: Claudiu Beznea
Add slew rate support for SAM9X60 pin controller.
Signed-off-by: Claudiu Beznea
---
drivers/pinctrl/pinctrl-at91.c | 34 ++
include/dt-bindings/pinctrl/at91.h | 4
2 files changed, 38 insertions(+)
diff --git
From: Claudiu Beznea
Hi,
This series adds support for drive strength and slew rate support for
Microchip SAMX60's pin controller. For drive strenght we could have 2
values: low, high. For slew rate we could have 2 values: enable, disabled.
Thank you,
Claudiu Beznea
Claudiu Beznea (4):
From: Claudiu Beznea
SAM9X60 uses high and low drive strengths. To implement this, in
at91_pinctrl_mux_ops::set_drivestrength we need bit numbers of
drive strengths (1 for low, 2 for high), thus change the code to
allow the usage of drive strength bit numbers.
Signed-off-by: Claudiu Beznea
---
34 matches
Mail list logo