[PATCH 00/11] drivers: Driver support for ADI SC5xx SoCs

at times and currently passes CI. Greg Malysa (4): pinctrl: Add support for ADI SC5XX-family pinctrl gpio: Add support for SC5XX-family processor GPIO driver net: Add support for ADI SC5xx SoCs with DWC QoS ethernet dma: Add driver for ADI SC5xx-family SoC MDMA functionality Nathan

[PATCH 11/11] mmc: Add support for ADI SC5XX-family processor SDHCI peripherals

From: Nathan Barrett-Morrison Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Nathan Barrett-Morrison

[PATCH 10/11] spi: Add support for ADI SC5XX-family processor SPI peripherals

Malysa Signed-off-by: Greg Malysa Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Co-developed-by: Piotr Wojtaszczyk Signed-off-by: Piotr Wojtaszczyk Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed

[PATCH 09/11] remoteproc: Add in SHARC loading for ADI SC5XX-family processors

time through the U-Boot interface. Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Co-developed-by: Piotr Wojtaszczyk Signed-off-by: Piotr Wojtaszczyk Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off

[PATCH 08/11] dma: Add driver for ADI SC5xx-family SoC MDMA functionality

Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Greg Malysa --- MAINTAINERS | 1 + drivers/dma/Kconfig | 7 ++ drivers/dma/Makefile | 1 + drivers/dma/adi_dma.c | 255 ++ 4

[PATCH 07/11] watchdog: Add support for ADI SC5XX-family watchdog peripheral

From: Nathan Barrett-Morrison Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Nathan Barrett-Morrison

[PATCH 06/11] net: Add support for ADI SC5xx SoCs with DWC QoS ethernet

: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Greg Malysa --- MAINTAINERS | 1 + drivers/net/Kconfig | 7 +++ drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 6 ++ drivers/net

[PATCH 05/11] i2c: Add support for ADI SC5XX-family I2C peripheral

From: Nathan Barrett-Morrison Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by

[PATCH 04/11] usb: musb-new: Add support for Analog Devices SC5xx SoCs

From: Nathan Barrett-Morrison This adds support for the MUSB-based USB controller found in the Analog Devices SC57x and SC58x SoCs. Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off

[PATCH 03/11] gpio: Add support for ADI ADP5588 GPIO expander chips

From: Nathan Barrett-Morrison This adds support for the ADP588 GPIO expander from Analog Devices. It is accessed over I2C and provides up to 18 pins. It is largely a port of the Linux driver developed by Michael Hennerich Signed-off-by: Ian Roberts Signed-off-by: Greg Malysa Signed-off-by

[PATCH 02/11] gpio: Add support for SC5XX-family processor GPIO driver

Signed-off-by: Arturs Artamonovs Signed-off-by: Greg Malysa --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 9 ++ drivers/gpio/Makefile| 1 + drivers/gpio/gpio-adi-adsp.c | 179 +++ 4 files changed, 190 insertions(+) create

[PATCH 01/11] pinctrl: Add support for ADI SC5XX-family pinctrl

-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Greg Malysa --- --- MAINTAINERS| 1 + drivers/pinctrl/Kconfig| 8 ++ drivers/pinctrl/Makefile | 1

Re: [PATCH] usb: dwc2: Add in version 4xx compatibility

> > > > If you have access to the hardware that has a 4.20a dwc2 controller, > > maybe you can help testing the patch above patch as well? My hardware unfortunately only has a 4.00a controller so I cannot test the 4.20a reset functionality. However, Kongyang Liu's patch works for me as a replaceme

Re: [GIT PULL] Please pull u-boot-mmc master

On Tue, Apr 30, 2024 at 3:42 AM Francesco Dolcini wrote: > > On Mon, Apr 29, 2024 at 03:39:53PM -0500, Judith Mendez wrote: > > A patch in this series caused a regression for AM62x SK with the > > following error: > > +1, this affects also Verdin AM62. Hi, please try https://patchwork.ozlabs.org

Re: [PATCH] mmc: sdhci: Correct ADMA_DESC_LEN to 12

of the v4 support? What about mirroring the kernel's dynamic behavior by checking the combination of capabilities and control registers to figure out which mode to use rather than hardcoding it? -- Greg Malysa Timesys Corporation

Re: [GIT PULL] Please pull u-boot-mmc master

a random value instead of NULL to start off, so it isn't called and adma_addr is not populated correctly? Thanks, Greg -- Greg Malysa Timesys Corporation

[PATCH v2 1/4] arch: arm: Add Analog Devices SC5xx machine type

reused by all boards - Early initialization for system clocks and DDR controller Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs

[PATCH v2 0/4] arm: Add Analog Devices SC5xx Machine Type

iewed #include usage and pruned unnecessary files - Passes gitlab CI run locally - Added gptimer driver to this series because a minimal system can't boot without it Greg Malysa (1): drivers: timer: Add in driver support for ADI SC5XX-family GP timer peripheral Nathan Barrett-Morrison (

[PATCH v2 2/4] drivers: clk: adi: Add in SC5XX-family clock driver

From: Nathan Barrett-Morrison This adds support for the SC5XX clock trees which are required for reading clock speeds on the SoCs. This is largely a port of the same support for Linux, which has not yet been submitted upstream. Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co

[PATCH v2 3/4] drivers: serial: Add in UART for ADI SC5XX-family processors

From: Nathan Barrett-Morrison Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Nathan Barrett-Morrison --- (no

[PATCH v2 4/4] drivers: timer: Add in driver support for ADI SC5XX-family GP timer peripheral

Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Greg Malysa --- Changes in v2: - Added gptimer driver to this series

[PATCH v2] mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_ops

developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- Changes in v2: - Switch from #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) to #ifdef CONFIG_MMC_SDHCI_ADMA_HELPERS, as CONFIG_I

Re: [PATCH] mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_ops

y. There is no CONFIG_SPL_SDHCI_ADMA_HELPERS so CONFIG_IS_ENABLED fails while building the SPL version of sdhci-adma.o as the structure definition is different. This only appears on platforms which have CONFIG_SPL_MMC enabled, which our platform did not, so I missed this interaction earlier. I apologize for this mistake. This will be fixed in v2 by changing the #if back to #ifdef CONFIG_MMC_SDHCI_ADMA_HELPERS, which I will submit after CI finishes running to verify on all platforms. Thanks, Greg -- Greg Malysa Timesys Corporation

Re: [PATCH] usb: dwc2: Add in version 4xx compatibility

Hi Mattijs, > Please avoid top-posting when replying, it makes following the > discussion more difficult: > https://www.kernel.org/doc/html/latest/process/submitting-patches.html#use-trimmed-interleaved-replies-in-email-discussions Will do. Sorry about that; I'm still learning about this approach

Re: [PATCH 0/3] arm: Add Analog Devices SC5xx Machine Type

I'm afraid I have to admit I don't know. I'll work with our IT team to make sure we can run CI locally, and when v2 comes around the answer will be yes. On Thu, Apr 11, 2024 at 7:52 PM Tom Rini wrote: > > On Thu, Apr 11, 2024 at 07:37:27PM -0400, Greg Malysa wrote: >

Re: [PATCH 1/3] arch: arm: Add Analog Devices SC5xx machine type

on them--possibly it was just necessary for the initial set of init code we started with. I believe we're not using the mach type constants anywhere so that will be straightforward to drop as well. Thanks, Greg On Thu, Apr 11, 2024 at 7:58 PM Tom Rini wrote: > > On Thu, Apr 11, 2024 a

[PATCH 1/3] arch: arm: Add Analog Devices SC5xx machine type

reused by all boards - Early initialization for system clocks and DDR controller Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs

[PATCH 0/3] arm: Add Analog Devices SC5xx Machine Type

This series adds support for the ADI SC5xx machine type and includes two core drivers that are required for being able to boot any board--a UART driver and the clock tree driver. Our corresponding Linux support relies on u-boot configuring the clocks correctly before booting, so it is not possibl

[PATCH 2/3] drivers: clk: adi: Add in SC5XX-family clock driver

From: Nathan Barrett-Morrison This adds support for the SC5XX clock trees which are required for reading clock speeds on the SoCs. This is largely a port of the same support for Linux, which has not yet been submitted upstream. Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co

[PATCH 3/3] drivers: serial: Add in UART for ADI SC5XX-family processors

From: Nathan Barrett-Morrison Co-developed-by: Greg Malysa Signed-off-by: Greg Malysa Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts Signed-off-by: Vasileios Bimpikas Signed-off-by: Utsav Agarwal Signed-off-by: Arturs Artamonovs Signed-off-by: Nathan Barrett-Morrison

[PATCH 00/11] cadence-qspi: Add DTR support including PHY mode calibration

This series introduces support for DTR mode for the Cadence QSPI/OSPI IP. We have been developing it against the SC594/SC598 from ADI, so there are some limitations specific to our hardware's capabilities. Ideally this series could be enhanced with features introduced in a patch series submitted

[PATCH 11/11] spi: cadence-quadspi: Implement high speed calibration

: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- doc/device-tree-bindings/spi/spi-cadence.txt | 9 + drivers/spi/cadence_qspi.c | 392 +-- drivers/spi/cadence_qspi.h | 77 ++-- drivers/spi/cadence_qspi_apb.c

[PATCH 07/11] spi: cadence-quadspi: Remove redundant DTR state

Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi/cadence_qspi.c | 6 ++ drivers/spi/cadence_qspi.h | 1 - drivers/spi/cadence_qspi_apb.c | 27 --- 3 files changed, 14 insertions

[PATCH 10/11] spi: cadence-quadspi: Add DT control of max Read Delay Capture value

-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- doc/device-tree-bindings/spi/spi-cadence.txt | 2 ++ drivers/spi/cadence_qspi.c | 9 - drivers/spi/cadence_qspi.h | 2 ++ 3 files changed, 12 insertions(+), 1

[PATCH 09/11] spi: cadence-quadspi: Add support for memory DMA channel transfers

added later for platforms that need it. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi/cadence_qspi.c | 47 drivers/spi/cadence_qspi.h | 31 +-- drivers/spi

[PATCH 08/11] spi: cadence-quadspi: Direct mode does not support zero length addresses

From: Ian Roberts It is not possible to configure the Cadence SPI IP block to use a zero length address in DMA read or write commands. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi

[PATCH 06/11] spi: cadence-quadspi: unconditionally disable auto status register reads

this feature for now. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi/cadence_qspi_apb.c | 46 ++ 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a

[PATCH 01/11] mtd: spi-nor: Add calibration hook for high speed SPI

read commands and all enabled fast IO modes. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- --- doc/device-tree-bindings/spi/spi-bus.txt | 4 + drivers/mtd/spi/Kconfig | 12

[PATCH 04/11] spi: cadence-quadspi: enable opcode extension based on command length

Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi/cadence_qspi_apb.c | 66 +- 1 file changed, 49 insertions(+), 17 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi

[PATCH 05/11] spi: cadence-quadspi: disable automatic write enable

-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 72e92cc997

[PATCH 03/11] spi: cadence-quadspi: Enable DDR bit for DTR commands

From: Ian Roberts The Cadence octal SPI IP read instruction register requires a bit to be set to indicate if the read opcode is a compliant DDR read command. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts

[PATCH 02/11] mtd: spi-nor: Octal DTR support for IS25*x

From: Ian Roberts ISSI IS25*x series SPIflash chips are capable of Octal IO and DDR. Add spi-nor support to enable and operate in these modes. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- drivers

Re: [PATCH 01/19] spi: cadence_qspi: Add support for DDR PHY mode

orithm doesn't appear to re-calibrate the read capture delay register, which is required whenever the clock or IO mode changes. At Timesys we have a set of patches that implement DDR and PHY calibration for the same Cadence IP that presents different solutions to the above issues. However, our

Re: [PATCH] mtd: spi-nor: Add support to exit 4-byte mode

Configure the BAR - discover bank cmds and read current bank */ > nor->addr_width = 3; > + set_4byte(nor, info, 0); > ret = read_bar(nor, info); > if (ret < 0) > return ret; > -- > 2.37.6 > Thanks, Greg -- Greg Malysa Timesys Corporation

Re: [PATCH] usb: dwc2: Add in version 4xx compatibility

50 AM Marek Vasut wrote: > > On 3/26/24 3:32 AM, Greg Malysa wrote: > > From: Nathan Barrett-Morrison > > > > This adds the Synopsys device id for version 4xx of the designware > > IP block and extends the version check to include it to permit > > new hardware

Upcoming Analog Devices SoC Support Submission

spective subsystem maintainers, but it seems rude to have a 20-element patch series that gets resubmitted each time feedback comes in for one component. If we break it down into separate patches for each piece, what would be the best way to ensure that all of the dependencies are merged in order?

[PATCH] usb: dwc2: Add in version 4xx compatibility

From: Nathan Barrett-Morrison This adds the Synopsys device id for version 4xx of the designware IP block and extends the version check to include it to permit new hardware to run. It does not add any 4xx-specific features. Signed-off-by: Ian Roberts Signed-off-by: Greg Malysa Signed-off-by

[PATCH] mmc: Support 32-bit only ADMA on 64-bit platforms

number of platforms where these statements are not equivalent. Using 32 bits is opt-in and existing 64 bit platforms should be unaffected by this change. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Co-developed-by: Ian Roberts Signed-off-by: Ian Roberts

[PATCH] mmc: sdhci: Fix potential ADMA descriptor table overflow

transaction larger than actual_max_transfer is issued. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- --- include/sdhci.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include

[PATCH] mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_ops

developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Greg Malysa Signed-off-by: Ian Roberts --- --- drivers/mmc/fsl_esdhc.c | 2 +- drivers/mmc/sdhci-adma.c | 41 +++- drivers/mmc/sdhci.c | 8 +--- includ

[PATCH v2] build: Revive and update LDR format support

did not need to be created. Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Ian Roberts Signed-off-by: Greg Malysa --- Changes in v2: - Add HAS_LDR prerequisite to avoid prompting for LDR_CPU on unrelated platforms - Fixed accidentally moving

[PATCH] build: Revive and update LDR format support

did not need to be updated Co-developed-by: Nathan Barrett-Morrison Signed-off-by: Nathan Barrett-Morrison Signed-off-by: Ian Roberts Signed-off-by: Greg Malysa --- Kconfig | 9 - Makefile | 2 +- scripts/Makefile.spl | 5 + 3 files changed, 14 insertions