there is CSI/DSI connector.
The dts files are identical to the ones submitted to the upstream kernel.
Signed-off-by: Stefan Mavrodiev
---
Changes for v2:
- Reworked defconfig
- Synced dts with upstream kernel
- Added maintainer
arch/arm/dts/Makefile| 1 +
arch/arm
Originally dram clock was set to 480MHz, but this behaves
unstable. To improve stability the clock is reduced to 384MHz
Signed-off-by: Stefan Mavrodiev
---
configs/A20-OLinuXino-Lime2_defconfig | 2 +-
configs/A20-OLinuXino-Lime_defconfig | 2 +-
configs/A20-Olimex-SOM-EVB_defconfig | 2 +-
3
Hi,
I've notice that you've reduced DRAM clock for Lime2 and Lime, but not
for A20-SOM.
Is there any specific reason for this?
Regards,
Stefan Mavrodiev
Olimex LDT
On 10/11/2016 12:38 PM, Hans de Goede wrote:
Hi,
On 10/11/2016 10:44 AM, Stefan Mavrodiev wrote:
Originally
rectly.
+
return log_ret(ret);
}
--
2.17.1
P.S.
You should cc to all maintainers. You can use ./scripts/get_maintainer.pl.
Best regards,
Stefan Mavrodiev
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Hi,
On 7/2/19 11:42 AM, Nicolas Chauvet wrote:
Le mar. 2 juil. 2019 à 09:41, Stefan Mavrodiev a écrit :
Hi,
On 6/27/19 9:56 PM, marvi...@posteo.de wrote:
Am Freitag, 21. Juni 2019, 22:01:35 CEST schrieb Marc Dietrich:
Fixes: 57e7775413 ("video: backlight: Parse PWM polarity cell"
On 7/2/19 12:05 PM, Stefan Mavrodiev wrote:
Hi,
On 7/2/19 11:42 AM, Nicolas Chauvet wrote:
Le mar. 2 juil. 2019 à 09:41, Stefan Mavrodiev a
écrit :
Hi,
On 6/27/19 9:56 PM, marvi...@posteo.de wrote:
Am Freitag, 21. Juni 2019, 22:01:35 CEST schrieb Marc Dietrich:
Fixes: 57e7775413 ("
This patch enables the reading of the polarity cell from a PWM
phandle and calls pwm_set_invert().
---
drivers/video/pwm_backlight.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index bd733f5f1c..0a08a76af1 100644
---
This patch enables the reading of the polarity cell from a PWM
phandle and calls pwm_set_invert().
Not all platforms have polarity cell, so skip if it's not pressent.
Signed-off-by: Stefan Mavrodiev
---
Changes for v2:
- Check if phandle has polarity cell
- Add missing signed-o
fdt32_t.
[1] Documentation/devicetree/bindings/mtd/partition.txt
Signed-off-by: Stefan Mavrodiev
---
common/fdt_support.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 42583e3ed8..b0501e12e6
On 4/21/19 10:33 PM, Simon Glass wrote:
Hi Stefan,
On Fri, 12 Apr 2019 at 02:46, Stefan Mavrodiev wrote:
When using fdt_fixup_mtdparts() offset and length cell sizes
are limited to 4 bytes (1 cell). However if the mtd device is
bigger then 4GiB, then #address-cells and #size-cells are
8
fdt32_t.
[1] Documentation/devicetree/bindings/mtd/partition.txt
Signed-off-by: Stefan Mavrodiev
---
Changes for v2:
- Use fdt_setprop_u64() and ..._u32() instead of fdt_setprop()
- Add size value using fdt_appendprop_u64() and ..._u32()
common/fdt_support.c | 31
On 12/14/18 5:55 PM, Maxime Ripard wrote:
On Fri, Dec 14, 2018 at 04:14:31PM +0200, Stefan Mavrodiev wrote:
On 12/14/18 11:25 AM, Maxime Ripard wrote:
On Thu, Dec 13, 2018 at 09:12:57AM +0200, Stefan Mavrodiev wrote:
On 12/6/18 8:41 AM, Stefan Mavrodiev wrote:
On 12/5/18 5:46 PM, Maxime
On 12/17/18 8:37 AM, Stefan Mavrodiev wrote:
On 12/14/18 5:55 PM, Maxime Ripard wrote:
On Fri, Dec 14, 2018 at 04:14:31PM +0200, Stefan Mavrodiev wrote:
On 12/14/18 11:25 AM, Maxime Ripard wrote:
On Thu, Dec 13, 2018 at 09:12:57AM +0200, Stefan Mavrodiev wrote:
On 12/6/18 8:41 AM, Stefan
On 12/20/18 12:14 PM, Jagan Teki wrote:
On Fri, Dec 14, 2018 at 3:48 PM Jagan Teki wrote:
On Wed, Dec 5, 2018 at 5:58 PM Stefan Mavrodiev wrote:
Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
On 12/20/18 12:45 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 3:59 PM Stefan Mavrodiev wrote:
On 12/20/18 12:14 PM, Jagan Teki wrote:
On Fri, Dec 14, 2018 at 3:48 PM Jagan Teki wrote:
On Wed, Dec 5, 2018 at 5:58 PM Stefan Mavrodiev wrote:
Current driver doesn't check i
On 12/20/18 12:56 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 4:18 PM Stefan Mavrodiev wrote:
On 12/20/18 12:45 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 3:59 PM Stefan Mavrodiev wrote:
On 12/20/18 12:14 PM, Jagan Teki wrote:
On Fri, Dec 14, 2018 at 3:48 PM Jagan Teki wrote:
On
On 12/20/18 1:54 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 4:49 PM Stefan Mavrodiev wrote:
On 12/20/18 12:56 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 4:18 PM Stefan Mavrodiev wrote:
On 12/20/18 12:45 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 3:59 PM Stefan Mavrodiev wrote
On 12/20/18 2:38 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 5:38 PM Stefan Mavrodiev wrote:
On 12/20/18 1:54 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 4:49 PM Stefan Mavrodiev wrote:
On 12/20/18 12:56 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 4:18 PM Stefan Mavrodiev wrote
On 12/20/18 2:44 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 6:12 PM Stefan Mavrodiev wrote:
On 12/20/18 2:38 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 5:38 PM Stefan Mavrodiev wrote:
On 12/20/18 1:54 PM, Jagan Teki wrote:
On Thu, Dec 20, 2018 at 4:49 PM Stefan Mavrodiev wrote
To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE.
However even the controller is enabled, the mux for the pins
are not set.
This patch follows the existing mux method. Since the pads are
different, separate check is added for each i2c.
Tested with A64-SOM204 board.
Signed-off-by: Stefan
sh test:
0 erase: 11363 ticks, 90 KiB/s 0.720 Mbps
1 check: 825 ticks, 1241 KiB/s 9.928 Mbps
2 write: 2472 ticks, 414 KiB/s 3.312 Mbps
3 read: 815 ticks, 1256 KiB/s 10.048 Mbps
Test passed
0 erase: 11363 ticks, 90 KiB/s 0.720 Mbps
1 check: 825 ticks, 1241 KiB/s 9.928 Mbps
2 write: 2472 ticks, 414 KiB/s 3.
On 2/18/19 12:38 PM, Jagan Teki wrote:
Hi Stefan,
On Fri, Feb 15, 2019 at 12:12 PM Stefan Mavrodiev wrote:
[snip]
+static const unsigned long sun4i_spi_bits[] = {
Same here, make it uint32_t, since it describes register masks in 32 bit
registers.
+[SPI_GCR_TP]= BIT(18
= 1008MHz
However if the requested clock is 816, n is 22.66 rounded
to 22, which results:
(24MHz * 28 * 3) / 2 = 792MHz
Changing k to 4 satisfies both system clocks:
(24E6 * 21 * 4) / 2 = 1008MHz
(24E6 * 17 * 4) / 2 = 816MHz
Signed-off-by: Stefan Mavrodiev
---
arch/arm/mach-sunxi
From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.
Signed-off-by: Stefan Mavrodiev
---
Changes for v2:
- The pin mux is
On 11/03/2017 01:07 PM, Karsten Merker wrote:
On Fri, Nov 03, 2017 at 08:56:51AM +0200, Stefan Mavrodiev wrote:
From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC
"just to test", and it's
turn out it wasn't not OK,
because it should be compatible with linux, u-boot and etc. What's the
point since it's just for testing...?
Sorry again, but can someone explain to me, that to do?
I'm not trying to pick on you guys. J
On 02/08/2018 09:03 AM, Jagan Teki wrote:
On Thu, Feb 8, 2018 at 11:54 AM, Stefan Mavrodiev
wrote:
On 02/07/2018 07:19 PM, Maxime Ripard wrote:
On Wed, Feb 07, 2018 at 12:55:54PM +0530, Jagan Teki wrote:
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 =
PU: Allwinner A20 (SUN7I)
Model: Olimex A20-OLinuXino-LIME2
I2C: ready
DRAM: 1 GiB
MMC: SUNXI SD/MMC: 0
Signed-off-by: Stefan Mavrodiev
---
drivers/i2c/mvtwsi.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 30bee0d.
cards.
On A20-SOM204-EVB-eMMC there is eMMC card (KLMAG2GEND) which complains
about it. Maybe there is other boards with similar problem?
So the fix is to match delays for both u-boot and kernel.
Signed-off-by: Stefan Mavrodiev
---
drivers/mmc/sunxi_mmc.c | 8
1 file changed, 4 insertions
From rev.J A20-OLinuXino-MICRO has eMMC option. For now this is
only 4GB, but in the future size may increase.
The dts file is the same from mainline kernel.
Signed-off-by: Stefan Mavrodiev
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun7i-a20-olinuxino-micro
On 09/04/2017 08:55 AM, Stefan Mavrodiev wrote:
From rev.J A20-OLinuXino-MICRO has eMMC option. For now this is
only 4GB, but in the future size may increase.
The dts file is the same from mainline kernel.
Signed-off-by: Stefan Mavrodiev
---
arch/arm/dts/Makefile
On 09/13/2017 03:24 PM, Jagan Teki wrote:
On Mon, Sep 4, 2017 at 11:25 AM, Stefan Mavrodiev wrote:
From rev.J A20-OLinuXino-MICRO has eMMC option. For now this is
only 4GB, but in the future size may increase.
The dts file is the same from mainline kernel.
Signed-off-by: Stefan Mavrodiev
From rev.J A20-OLinuXino-MICRO has eMMC option. For now this is
only 4GB, but in the future size may increase.
The dts file is the same from mainline kernel.
Signed-off-by: Stefan Mavrodiev
---
Changes for v2:
- Synced with latest u-boot
- Removed MMC3 CD pin configuration
arch/arm/dts
On 09/27/2017 04:19 PM, Maxime Ripard wrote:
Hi Stefan,
You should also put Jagan Teki as recipients.
On Wed, Sep 27, 2017 at 07:19:10AM +, Stefan Mavrodiev wrote:
From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes
From revision J the board uses new phy chip LAN8710. Compared
with RTL8201, RA17 pin is TXERR. It has pullup which causes phy
not to work. To fix this PA17 is muxed with GMAC function. This
makes the pin output-low.
Signed-off-by: Stefan Mavrodiev
---
arch/arm/dts/sun7i-a20-olinuxino-micro.dts
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel (currently 4.15.0-rc1).
Signed-off-by: Stefan Mavrodiev
---
Tested with A20-OLinuXino-Lime2 with W25Q128 chip. The output is:
=> sspi
=> sf probe
SF: Detected w25q128bv with page size 256 Bytes,
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel (currently 4.15.0-rc1).
Signed-off-by: Stefan Mavrodiev
---
Changes for v2:
- Updated copyright including original owners
- Remove write/read register function. They are replaced with direct opts
On 12/13/2017 07:19 AM, Jagan Teki wrote:
On Fri, Dec 8, 2017 at 5:08 PM, Jagan Teki wrote:
On Fri, Dec 8, 2017 at 2:05 PM, Stefan Mavrodiev wrote:
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel (currently 4.15.0-rc1).
Signed-off-by: Stefan
On 12/13/2017 08:27 AM, Jagan Teki wrote:
On Wed, Dec 13, 2017 at 11:43 AM, Stefan Mavrodiev wrote:
On 12/13/2017 07:19 AM, Jagan Teki wrote:
On Fri, Dec 8, 2017 at 5:08 PM, Jagan Teki
wrote:
On Fri, Dec 8, 2017 at 2:05 PM, Stefan Mavrodiev
wrote:
Add spi driver for sun4i, sun5i and sun7i
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel.
Signed-off-by: Stefan Mavrodiev
---
Changes for v3:
- Add required changes in dts and defeconfig file for testing
Changes for v2:
- Updated copyright including original owners
- Remove write
94 KiB/s 0.752 Mbps
3 read: 8872 ticks, 115 KiB/s 0.920 Mbps
=>
Signed-off-by: Stefan Mavrodiev
---
arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 21 +
configs/A20-OLinuXino-Lime2_defconfig | 8
2 files changed, 29 insertions(+)
diff --git a/arch/arm/d
On 12/26/2017 11:47 AM, Jagan Teki wrote:
On Fri, Dec 22, 2017 at 3:30 PM, Stefan Mavrodiev wrote:
Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
- Exposing spi0 alternative pins in the dts file
- Add alias node, enabling driver probing
- Enable spi flash
On 01/02/2018 01:01 PM, Stefan Mavrodiev wrote:
On 12/26/2017 11:47 AM, Jagan Teki wrote:
On Fri, Dec 22, 2017 at 3:30 PM, Stefan Mavrodiev
wrote:
Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
- Exposing spi0 alternative pins in the dts file
- Add alias node
On 01/22/2018 10:36 AM, Jagan Teki wrote:
On Tue, Jan 2, 2018 at 4:31 PM, Stefan Mavrodiev
wrote:
On 12/26/2017 11:47 AM, Jagan Teki wrote:
On Fri, Dec 22, 2017 at 3:30 PM, Stefan Mavrodiev
wrote:
Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
- Exposing spi0
By default PHY address used for sunxi boards is 1. Some new boards
(A20-SOM204-EVB) uses different address.
The code enables selective PHY address via menuconfig inside ARM
submenu. The option has default value of 1.
Signed-off-by: Stefan Mavrodiev
---
arch/arm/mach-sunxi/Kconfig| 9
. Others are not usable with A20 SoC: PCIe and USB3.
This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel, except some nodes are removed to make file
compatible with existing dtsi file.
[1] https://www.olimex.com/Products/SOM204/
Signed-off-by: Stefan Mavrodiev
A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired
to MMC2 slot.
This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel.
Signed-off-by: Stefan Mavrodiev
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun7i-a20
On 01/30/2018 09:15 AM, Stefan Mavrodiev wrote:
On 01/22/2018 10:36 AM, Jagan Teki wrote:
On Tue, Jan 2, 2018 at 4:31 PM, Stefan Mavrodiev
wrote:
On 12/26/2017 11:47 AM, Jagan Teki wrote:
On Fri, Dec 22, 2017 at 3:30 PM, Stefan Mavrodiev
wrote:
Driver testing is done with A20-OLinuXino
. Others are not usable with A20 SoC: PCIe and USB3.
This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel, except some nodes are removed to make file
compatible with existing dtsi file.
[1] https://www.olimex.com/Products/SOM204/
Signed-off-by: Stefan Mavrodiev
A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired
to MMC2 slot.
This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel.
Signed-off-by: Stefan Mavrodiev
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun7i-a20
leted.
- devkit3250- The PHY_ADDR is in hex format (0x1F).
Manually CONFIG_PHY_ADDR=31 is added in
the defconfig.
After the changes the suspicious defconfigs passes building.
Signed-off-by: Stefan Mavrodiev
---
R
: PCIe and USB3.
This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel, except some nodes are removed to make file
compatible with existing dtsi file.
Signed-off-by: Stefan Mavrodiev
Acked-by: Maxime Ripard
---
Changes for v2:
- Add missing MAINTAINERS
A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired
to MMC2 slot.
This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel.
Signed-off-by: Stefan Mavrodiev
Acked-by: Maxime Ripard
---
Changes for v2:
- Add missing MAINTAINERS entry
On 02/02/2018 02:54 PM, Maxime Ripard wrote:
On Fri, Feb 02, 2018 at 11:37:03AM +0200, Stefan Mavrodiev wrote:
A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired
to MMC2 slot.
This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel
leted.
- devkit3250- The PHY_ADDR is in hex format (0x1F).
Manually CONFIG_PHY_ADDR=31 is added in
the defconfig.
After the changes the suspicious defconfigs passes building.
Signed-off-by: Stefan Mavrodiev
Acked-by: Maxime Ripard
---
Ch
On 02/01/2018 04:45 PM, Jagan Teki wrote:
On Thu, Feb 1, 2018 at 8:08 PM, Stefan Mavrodiev
wrote:
On 01/30/2018 09:15 AM, Stefan Mavrodiev wrote:
On 01/22/2018 10:36 AM, Jagan Teki wrote:
On Tue, Jan 2, 2018 at 4:31 PM, Stefan Mavrodiev
wrote:
On 12/26/2017 11:47 AM, Jagan Teki wrote:
On
Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel.
Signed-off-by: Stefan Mavrodiev
---
Changes for v4:
- Sync patch with u-boot-sunxi (80719938c9f901cc6b90b85d8065d084a03c06ae)
- Change wait_for_bits() to wait_for_bits_le32()
- Change CCTL
00 0x1000 0x100
device 0 offset 0x1000, size 0x100
SF: 256 bytes @ 0x1000 Read: OK
=> cmp.b 0x5000 0x5100 0x100
Total of 256 byte(s) were the same
Signed-off-by: Stefan Mavrodiev
---
arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 30 ++
conf
On 02/07/2018 08:39 AM, Jagan Teki wrote:
On Wed, Feb 7, 2018 at 12:00 PM, Stefan Mavrodiev
wrote:
On 02/06/2018 06:48 PM, Jagan Teki wrote:
On Tue, Feb 6, 2018 at 6:44 PM, Stefan Mavrodiev
wrote:
Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
- Exposing spi0
On 02/06/2018 06:48 PM, Jagan Teki wrote:
On Tue, Feb 6, 2018 at 6:44 PM, Stefan Mavrodiev wrote:
Driver testing is done with A20-OLinuXino-Lime2. Testing
requirements are:
- Exposing spi0 alternative pins in the dts file
- Add alias node, enabling driver probing
- Add flash sub-node
On 02/07/2018 09:25 AM, Jagan Teki wrote:
On Wed, Feb 7, 2018 at 12:35 PM, Stefan Mavrodiev
wrote:
On 02/07/2018 08:39 AM, Jagan Teki wrote:
On Wed, Feb 7, 2018 at 12:00 PM, Stefan Mavrodiev
wrote:
On 02/06/2018 06:48 PM, Jagan Teki wrote:
On Tue, Feb 6, 2018 at 6:44 PM, Stefan Mavrodiev
Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).
The patch add simple check if the destination pointer is NULL.
Signed-off-by: Stefan Mavrodiev
---
drivers/spi/sun4i_spi.c | 3 ++-
1
When the device is in peripheral mode there is no
struct usb_bus_priv allocated pointer, as the uclass driver
("usb_dev_generic") doesn't call per_device_auto_alloc_size.
This results in writing to the internal SDRAM at
priv->desc_before_addr = true;
Signed-off-by
On 12/5/18 2:57 PM, Marek Vasut wrote:
On 12/05/2018 01:49 PM, Stefan Mavrodiev wrote:
When the device is in peripheral mode
Can you have two devices, one in peripheral mode and one in host mode,
on the same system ?
Not 100% sure, but I'm thinking there is only one OTG port for
all
On 12/5/18 5:46 PM, Maxime Ripard wrote:
On Wed, Dec 05, 2018 at 02:27:57PM +0200, Stefan Mavrodiev wrote:
Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
SDRAM ( address 0 ).
The patch add simple check i
On 12/6/18 8:41 AM, Stefan Mavrodiev wrote:
On 12/5/18 5:46 PM, Maxime Ripard wrote:
On Wed, Dec 05, 2018 at 02:27:57PM +0200, Stefan Mavrodiev wrote:
Current driver doesn't check if the destination pointer is NULL.
This cause the data from the FIFO to be stored inside the internal
On 12/5/18 3:16 PM, Marek Vasut wrote:
On 12/05/2018 02:06 PM, Stefan Mavrodiev wrote:
On 12/5/18 2:57 PM, Marek Vasut wrote:
On 12/05/2018 01:49 PM, Stefan Mavrodiev wrote:
When the device is in peripheral mode
Can you have two devices, one in peripheral mode and one in host mode,
on the
On 12/14/18 11:25 AM, Maxime Ripard wrote:
On Thu, Dec 13, 2018 at 09:12:57AM +0200, Stefan Mavrodiev wrote:
On 12/6/18 8:41 AM, Stefan Mavrodiev wrote:
On 12/5/18 5:46 PM, Maxime Ripard wrote:
On Wed, Dec 05, 2018 at 02:27:57PM +0200, Stefan Mavrodiev wrote:
Current driver doesn't che
e new output is:
...
Net: eth0: ethernet@1c3
...
Signed-off-by: Stefan Mavrodiev
---
drivers/net/sun8i_emac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 0629b16e57..e6cb074bc4 100644
--- a/driver
Can someone review this patch?
Best regards,
Stefan
On 7/31/19 4:15 PM, Stefan Mavrodiev wrote:
clock_sun6i.c is used for sun6i, sun8i and sun50i SoC families.
PLL1 clock sets the default system clock, defined as:
sun6i: 100800
sun8i: 100800
sun50i: 81600
With the current
From: Stefan Mavrodiev
---
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/sun8i-a33-olinuxino.dts | 223 +++
configs/A33_OLinuXino_defconfig | 29 +
3 files changed, 254 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/sun8i
Sets LDO3 and LDO4 regulators at 2.8V. In the current config
these are off. This causes kernel to hang during
axp209 initialization.
Signed-off-by: Stefan Mavrodiev
---
configs/A20-OLinuXino_MICRO_defconfig | 2 ++
configs/A20-Olimex-SOM-EVB_defconfig | 2 ++
2 files changed, 4 insertions
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