Hi,
+Jagan
On 26/04/19 2:52 PM, Weijie Gao wrote:
> Some SPI controllers can't write nor->page_size bytes in a single step
> because their TX FIFO is too small, but when that happens we should
> make sure a WRITE_EN command before each write access and READ_SR command
> after each write access
Bin,
On 26/04/19 7:33 PM, Bin Meng wrote:
> Hi Simon,
>
> On Fri, Apr 26, 2019 at 7:26 AM Simon Glass wrote:
>>
>> Hi Bin,
>>
>> I find that 'sf test 0 1000' does not work anymore since this commit:
>>
>> c4e8862308 mtd: spi: Switch to new SPI NOR framework
>>
>> Have you seen any problems?
Hi,
On 24/04/19 6:32 PM, Rajat Srivastava wrote:
> Some Freescale QSPI controllers require driver to send only 16 bytes
> aligned data to TxFIFO while performing flash write operation. The extra
> data is not actually written on flash. The patch enables driver to send
> 16 bytes aligned data to
On 25/04/19 5:20 PM, Rajat Srivastava wrote:
>
>
>> -Original Message-----
>> From: Vignesh Raghavendra
>> Sent: Wednesday, April 24, 2019 10:17 PM
>> To: Rajat Srivastava ; u-boot@lists.denx.de;
>> ja...@openedev.com
>> Cc: Ashish Kumar
On 26/04/19 4:56 AM, Simon Glass wrote:
> Hi Bin,
>
> I find that 'sf test 0 1000' does not work anymore since this commit:
>
> c4e8862308 mtd: spi: Switch to new SPI NOR framework
>
> Have you seen any problems? This seems to prevent proper SPI flash
> writing (not sure about reading).
>
purposes.
Signed-off-by: Peter Ujfalusi
Signed-off-by: Vignesh Raghavendra
---
drivers/dma/ti/k3-udma.c | 33 +
1 file changed, 9 insertions(+), 24 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index f78a01aa8f8c..f896e2958755 100644
On 24-Apr-19 6:10 PM, Rajat Srivastava wrote:
> Signed-off-by: Ashish Kumar
> Signed-off-by: Rajat Srivastava
Commit message is missing. But from $patch subject, I infer that $patch
is adding new feature and not actually fixing something broken?
If so, you should move the driver over to use
Hi.
On 24-Apr-19 6:10 PM, Rajat Srivastava wrote:
> From: Ashish Kumar
>
> Signed-off-by: Ashish Kumar
> ---
> drivers/mtd/spi/spi-nor-ids.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index
AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.
Signed-off-by: Vignesh Raghavendra
---
board/ti/am65x/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index
.
Signed-off-by: Vignesh Raghavendra
---
arch/Kconfig | 9 +
arch/arm/cpu/armv8/cache_v8.c | 10 ++
2 files changed, 19 insertions(+)
diff --git a/arch/Kconfig b/arch/Kconfig
index 2f3d07c13a18..760023b19a81 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -227,6
/disabling dcache by U-Boot and are special case.
Vignesh Raghavendra (2):
arch: armv8: Provide a way to disable cache maintenance ops
board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build
arch/Kconfig | 9 +
arch/arm/cpu/armv8/cache_v8.c | 10
Hi,
On 08/04/19 10:32 PM, Vignesh Raghavendra wrote:
> This series adds a Kconfig to disable cache maintenance operations on
> a coherent architectures. And disable cache flush/invalidate ops for
> SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent)
>
> Vignesh
On 16/04/19 5:29 PM, Rajat Srivastava wrote:
Maximum write size in a single write operation in
spi_nor_write_data() function can be equal to slave
tx buffer, which is adjusted in spi_mem_adjust_op_size()
and write operation gets fragmented.
Previously data write for the above fragmentation
to 4c96c61216719155b3a1d51f6373e996335861de:
spi: ti_qspi: Convert to spi-mem ops (2019-04-17 17:43:54 +0530)
Vignesh Raghavendra (2):
spi: ti_qspi: Drop non DM code
spi: ti_qspi: Convert to spi-mem ops
doc/driver-model
Tom, Jagan
On 16/04/19 9:31 PM, Vignesh Raghavendra wrote:
Now that SPI NOR Supports MMIO SPI controllers via spi-mem framework,
move TI QSPI to SPI MEM framework for better performance and avoid
repeating SPI NOR generic code in the driver.
While at that get rid of non DM code, as all boards
Convert driver to use spi-mem ops in order to support accelerated MMIO
flash interface in generic way and for better performance.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tom Rini
---
drivers/spi/ti_qspi.c | 132 ++
1 file changed, 68 insertions
Now that all boards using TI QSPI have moved to DM and DT, drop non DM
code completely.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tom Rini
---
drivers/spi/Kconfig | 13 +-
drivers/spi/Makefile | 2 +-
drivers/spi/ti_qspi.c| 231
, dra7xx EVMs. Build tested for all TI platforms using
buildman
v2
* Rebase on top of latest master and Uri's patch [1] removing
cl-som-am57x_defconfig
* Remove more un-needed CONFIGs related to TI QSPI that have not been
* Collect Reviewed-bys
[1] http://patchwork.ozlabs.org/patch/1085281/
Vignesh
On 05/04/19 2:24 PM, Rajat Srivastava wrote:
> Incorporate write enable and status check in the write data
> function itself.
>
> Formerly, Write data function used to break the data to be
> written into smaller chunks and used to send the smaller
> chunks without write enable or status check
On 12/04/19 10:46 AM, Jagan Teki wrote:
On 02/04/19 6:22 AM, Marek Vasut wrote:
> Replace the ad-hoc erase operation implementation with a simple
> spi_mem_op implementation of the same functionality. This is a minor
> optimization and removal of the ad-hoc code.
>
AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.
Signed-off-by: Vignesh Raghavendra
---
Changes since RFC:
Rename config option to SYS_DISABLE_DCACHE_OPS
board/ti/am65x/Kconfig | 1 +
1 file changed, 1 insertion
of same Kconfig across different
architecture, I have added the symbol to top level arch/Kconfig file.
Patch currently disables cache maintenance ops for arm64 only.
Signed-off-by: Vignesh Raghavendra
---
Changes since RFC:
Rename config option to SYS_DISABLE_DCACHE_OPS
arch/Kconfig
This series adds a Kconfig to disable cache maintenance operations on
a coherent architectures. And disable cache flush/invalidate ops for
SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent)
Vignesh Raghavendra (2):
arch: armv8: Provide a way to disable cache maintenance ops
+ Ashish,
On 02/04/19 6:22 AM, Marek Vasut wrote:
> Replace the ad-hoc erase operation implementation with a simple spi_mem_op
> implementation of the same functionality. This is a minor optimization and
> removal of the ad-hoc code.
>
> This however also changes the behavior of the execution of
Ashish,
>
> Hi Vignesh,
> This is working now(READ, WRITE), after some change in fsl_qspi driver, where
> I check for 4byte op codes now.
> But now I see that erase is getting address as ZERO. Which in my opinion is
> because
> spi_nor_erase_sector() call write_reg which has
On 28/03/19 3:37 PM, Ashish Kumar wrote:
>> -Original Message-
>> From: Vignesh Raghavendra
>> Sent: Wednesday, March 27, 2019 9:44 AM
>> To: Ashish Kumar ; Jagan Teki
>> ; u-boot@lists.denx.de; Tom Rini
>>
>> Cc: Kuldeep Singh
>> Subj
On 26/03/19 7:11 PM, Ashish Kumar wrote:
>>
>> On 26/03/19 10:36 AM, Ashish Kumar wrote:
>>> Hello Maintainers,
>>>
>>>
>>>
>>> With latest commit I see that saveenv command corrupts QSPI-flash,
>>> meaning if I read QSPI-flash at 0x0 offset RCW(reset configuration
>>> word) is erased after
On 26/03/19 10:36 AM, Ashish Kumar wrote:
> Hello Maintainers,
>
>
>
> With latest commit I see that saveenv command corrupts QSPI-flash,
> meaning if I read QSPI-flash at 0x0 offset RCW(reset configuration word)
> is erased after saveenv command was executed.
>
> This is tested on
AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_ARCH_IS_COHERENT to avoid cache operations in A53 SPL/U-Boot.
Signed-off-by: Vignesh Raghavendra
---
board/ti/am65x/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index
This series adds a Kconfig to disable cache maintenance operations on
a coherent architectures. And disable cache flush/invalidate ops for
SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent)
Vignesh Raghavendra (2):
arch: armv8: Provide a way to disable cache maintenance ops
of same Kconfig across different
architecture, I have added the symbol to top level arch/Kconfig file.
Patch currently disables cache maintenance ops for arm64 only.
Signed-off-by: Vignesh Raghavendra
---
arch/Kconfig | 7 +++
arch/arm/cpu/armv8/cache_v8.c | 18
On 02-Mar-19 5:02 PM, Stefan Roese wrote:
[...]
>>
>> It would be great if driver could be modified to support 3 and 4 byte
>> addressing modes.
>
> I fail to see, what really is needed to make the SPI driver support
> 3 and 4 byte addressing modes. I recently added the MT7688 SPI
> driver
Hi Stefan,
On 02-Mar-19 3:56 PM, Stefan Roese wrote:
> Hi Chris,
> Hi Vignesh,
>
> On 02.03.19 09:36, Vignesh Raghavendra wrote:
>>
>>
>> On 02-Mar-19 1:15 PM, Chris Packham wrote:
>>> This board uses Micron N25Q256A SPI flash. Enable SPI_FLASH_BAR t
On 02-Mar-19 1:15 PM, Chris Packham wrote:
> This board uses Micron N25Q256A SPI flash. Enable SPI_FLASH_BAR to allow
> us to access the whole chip.
>
> Signed-off-by: Chris Packham
> Cc: Vignesh R
> ---
>
Could add imply SPI_FLASH_BAR to KIRKWOOD_SPI instead? So that we don't
have to fix
On 01/03/19 1:42 PM, Chris Packham wrote:
> On Fri, Mar 1, 2019 at 8:40 PM Chris Packham wrote:
>>
>> On Fri, Mar 1, 2019 at 5:12 PM Vignesh Raghavendra wrote:
>>>
>>>
>>>
>>> On 01/03/19 7:00 AM, Chris Packham wrote:
>>>
On 01/03/19 7:00 AM, Chris Packham wrote:
> On Fri, Mar 1, 2019 at 11:15 AM Chris Packham wrote:
>>
>> Hi All,
>>
>> I was just testing out the db-88f6820-amc on u-boot#master and found
>> that the SPL can't fetch then next stage from SPI.
>>
>> U-Boot SPL 2019.04-rc2-00139-g91c56ed98da7 (Mar
501 - 536 of 536 matches
Mail list logo
