CC and Quad I/O(x4)
24 means 8-bit ecc requirement and Quad I/O(x4)
14 means 4-bit ecc requirement and Quad I/O(x4
Validated by read, erase, write, on Xilinx Zynq
PicoZed FPGA board which included Macronix SPI
Host (drivers/spi/spi-mxic.c).
Signed-off-by: Zhengxun
---
drivers/mtd/nand/spi/
mance of
continuous reads.
Signed-off-by: Zhengxun
---
drivers/mtd/nand/spi/core.c | 96 -
1 file changed, 95 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 6a497e67bb..314506bc7f 100644
--- a/driver
The patch supports setting the "CONT" bit of the configuration
register and adding a continuous read mode flag for identification.
Signed-off-by: Zhengxun
---
drivers/mtd/nand/spi/core.c | 11 +++
include/linux/mtd/spinand.h | 2 ++
2 files changed, 13 insertions(+)
di
Add continuous read state and initialize state to
default false.
Signed-off-by: Zhengxun
---
drivers/mtd/nand/spi/core.c | 8
include/linux/mtd/spinand.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 88d07b625d
This series add support continuous read mode for SPI NAND.
Zhengxun (4):
mtd: spinand: Add support continuous read mode
mtd: spinand: Add continuous read state
mtd: spinand: Add support continuous read operation
mtd: spinand: macronix: Add support for MX35LF2GE4AD
drivers/mtd/nand/spi
format to use hardware correctly.
3. Remove the incompatible functions of Uboot.
Signed-off-by: Zhengxun Li
---
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile| 1 +
drivers/mtd/nand/raw/mxic_nand.c | 603 +++
3 files changed, 610
function to support dummy buswidth
not align data buswidth operation.(ex: 1-1-4, 1-1-8)
4. Add Octal mode support.
Signed-off-by: Zhengxun
---
drivers/spi/Kconfig| 5 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-mxic.c | 546 +
3 files changed, 552
Hi,
Michal Simek 於 2021年6月16日 週三 上午10:05寫道：
>
> Hi,
>
> On 6/16/21 5:26 PM, Zhengxun Li wrote:
> > Hi Sean,
> >
> > Thank you for your reply.
> >
> > Sean Anderson 於 2021年6月15日 週二 下午2:52寫道：
> >>
> >>
> >>
> >>
Hi Sean,
Thank you for your reply.
Sean Anderson 於 2021年6月15日 週二 下午2:52寫道：
>
>
>
> On 6/15/21 1:21 PM, Zhengxun Li wrote:
> > Hi Michal,
> >
> > Sean Anderson 於 2021年6月11日 週五 下午3:07寫道：
> >>
> >>
> >>
> >> On 6/11/21 11:1
Hi Michal,
Sean Anderson 於 2021年6月11日 週五 下午3:07寫道：
>
>
>
> On 6/11/21 11:10 AM, Zhengxun wrote:
> > Add the devicetree binding for the xilinx clocking wizard.
> >
> > Signed-off-by: Zhengxun
> > ---
> > .../clock/xlnx,clocking-wizard.txt
Add the devicetree binding for the xilinx clocking wizard.
Signed-off-by: Zhengxun
---
.../clock/xlnx,clocking-wizard.txt| 43 +++
1 file changed, 43 insertions(+)
create mode 100644 doc/device-tree-bindings/clock/xlnx,clocking-wizard.txt
diff --git a/doc/device
set_rate to modify the frequency.
Signed-off-by: Zhengxun
---
drivers/clk/Kconfig | 11 ++
drivers/clk/Makefile| 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 186
3 files changed, 198 insertions(+)
create mode 100644 drivers/clk/clk
usage in of_to_plat
- get frequencies via clock framework
- delete incorrect naming
Changes in v2:
- naming is aligned with linux
- delete inappropriate description and code
Zhengxun (2):
clk: zynq: Add clock wizard driver
dt-bindings: add xilinx clocking wizard bindings
.../clock/xlnx
Hi,
Sean Anderson 於 2021年6月4日 週五 下午2:22寫道：
>
>
>
> On 6/4/21 1:05 PM, Zhengxun wrote:
> > The Clocking Wizard IP supports clock circuits customized
> > to your clocking requirements. The wizard support for
> > dynamically reconfiguring the clocking primitives f
Add the devicetree binding for the xilinx clocking wizard.
Signed-off-by: Zhengxun
---
.../clock/xlnx,clocking-wizard.txt| 43 +++
1 file changed, 43 insertions(+)
create mode 100644 doc/device-tree-bindings/clock/xlnx,clocking-wizard.txt
diff --git a/doc/device
set_rate to modify the frequency.
Signed-off-by: Zhengxun
---
drivers/clk/Kconfig | 9 ++
drivers/clk/Makefile| 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 186
3 files changed, 196 insertions(+)
create mode 100644 drivers/clk/clk
usage in of_to_plat
- get frequencies via clock framework
- delete incorrect naming
Changes in v2:
- naming is aligned with linux
- delete inappropriate description and code
Zhengxun (2):
clk: zynq: Add clock wizard driver
dt-bindings: add xilinx clocking wizard bindings
.../clock/xlnx
76c0eb27e6
>> --- /dev/null
>> +++ b/drivers/clk/clk-xlnx-clock-wizard.c
>> @@ -0,0 +1,177 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Xilinx 'Clocking Wizard' driver
>> + *
>> + * Copyright (c) 2021 Macronix Inc.
>> +
set_rate to modify the frequency.
Signed-off-by: Zhengxun
---
drivers/clk/Kconfig | 9 ++
drivers/clk/Makefile| 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 177
3 files changed, 187 insertions(+)
create mode 100644 drivers/clk/clk
aligned with linux
- delete inappropriate description and code
Zhengxun (1):
clk: zynq: Add clock wizard driver
drivers/clk/Kconfig | 9 ++
drivers/clk/Makefile| 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 177
3 files changed, 187
set_rate to modify the frequency.
Signed-off-by: zhengxun
---
drivers/clk/Kconfig | 9 ++
drivers/clk/Makefile| 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 177
3 files changed, 187 insertions(+)
create mode 100644 drivers/clk/clk
Add support to enable clock wizard for zynq platform.
Changes in v3:
- remove incorrect usage in of_to_plat
- get frequencies via clock framework
- delete incorrect naming
Changes in v2:
- naming is aligned with linux
- delete inappropriate description and code
zhengxun (1):
clk: zynq: Add
or .plat_auto here.
>>
>> Okay.
>>
>> On the other hand, if we want to add set_phase feature to clock wizard,
>> can you make some suggestions? I checked the clk-uclass and it does not
>> seem to be supported.
>
> Then you have to add it to uclass first but don't know content here.
Okay.
I switched my email account, I hope the declarement didn't offend you.
Thanks,
Zhengxun
Add the Zynq Mxic picozed development board support.
Signed-off-by: Zhengxun Li
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/zynq-mxic-picozed.dts | 72 ++
2 files changed, 74 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/zynq
set_rate to modify the frequency.
Signed-off-by: Zhengxun Li
---
drivers/clk/Kconfig | 9 +++
drivers/clk/Makefile| 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 152
3 files changed, 162 insertions(+)
create mode 100644 drivers
This series add support to enable clock wizard for zynq platform.
Changes in v2:
- naming is aligned with linux
- delete inappropriate description and code
Zhengxun Li (2):
clk: zynq: Add clock wizard driver
board: Add Zynq Mxic picozed development board support
arch/arm/dts/Makefile
The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence,
add SPI_NOR_OCTAL_READ flag for this flash.
Signed-off-by: zhengxun
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index
The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence,
add SPI_NOR_OCTAL_READ flag for this flash.
Signed-off-by: zhengxun
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index
This patch adds an implementation of exec_op, which support octal
mode and quad mode for reading flash and support existing single
mode for reading and writing flash concurrently.
Signed-off-by: zhengxun
---
drivers/spi/renesas_rpc_spi.c | 144 ++
1 file changed
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