On 03.04.2019 14:11, Marek Vasut wrote:
On 4/2/19 7:02 PM, Eugeniu Rosca wrote:
On Tue, Apr 02, 2019 at 06:02:46PM +0200, Marek Vasut wrote:
On 4/2/19 5:40 PM, Eugeniu Rosca wrote:
On Tue, Apr 02, 2019 at 05:28:43PM +0200, Marek Vasut wrote:
On 4/2/19 5:17 PM, Dirk Behme wrote:
On 02.04.19
On 02.04.19 17:40, Eugeniu Rosca wrote:
On Tue, Apr 02, 2019 at 05:28:43PM +0200, Marek Vasut wrote:
On 4/2/19 5:17 PM, Dirk Behme wrote:
On 02.04.19 15:34, Marek Vasut wrote:
On 4/2/19 3:18 PM, Eugeniu Rosca wrote:
With CONFIG_PINCTRL_PFC=n, aarch64-linux-gnu-ld reports:
-8
23f21
("IB/uverbs: Add UVERBS_ATTR_FLAGS_IN to the specs language")
Fixes: f6e545a73f88 ("pfc: rmobile: Add hook to configure pin as GPIO")
Reported-by: Dirk Behme
Signed-off-by: Eugeniu Rosca
Does CONFIG_PINCTRL_PFC=n produce a bootable binary ?
Why not? Main memory, boot
On 17.11.2017 16:04, Marek Vasut wrote:
On 11/17/2017 03:28 PM, Dirk Behme wrote:
Its a valid use case to call ehci_submit_async() with a NULL buffer
with length 0. E.g. from usb_set_configuration().
As invalidate_dcache_range() isn't able to judge if the address
NULL is valid
in ehci_submit_async() as here we know
that we don't have to invalidate such a buffer.
Signed-off-by: Dirk Behme <dirk.be...@de.bosch.com>
---
Notes:
This was found on an older vendor specific U-Boot on an ARMv8 SoC
with a MMU configuration where address 0x is invalid.
The callstack I'v
On 25.06.2016 21:04, Mateusz Kulikowski wrote:
Hi Dirk,
On 23.06.2016 13:33, Dirk Behme wrote:
[...]
Idea: perhaps after this series is merged we can add 2 new commands to u-boot
(SMC/HVC) to
play with hypervisors/secure monitors (and perhaps use some simple
functionality if needed).
How
Hi Mateusz,
On 07.01.2016 22:39, Mateusz Kulikowski wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 07.01.2016 16:06, Michal Simek wrote:
On 6.1.2016 14:04, Mateusz Kulikowski wrote:
On 14.10.2015 18:55, Sergey Temerkhanov wrote:
[...]
Idea: perhaps after this series is merged
On 29.01.2016 10:18, Ian Campbell wrote:
On Fri, 2016-01-29 at 12:04 +0800, Peng Fan wrote:
Hi Dirk,
Cc Ian xen experts.
On Thu, Jan 28, 2016 at 08:06:30PM +0100, Dirk Behme wrote:
Hi,
are there any U-Boot examples/patches to boot Xen on an ARMv8/aarch64
system?
I've found
http
Hi,
are there any U-Boot examples/patches to boot Xen on an ARMv8/aarch64
system?
I've found
http://lists.denx.de/pipermail/u-boot/2015-October/230077.html
what might be helpful.
But maybe I missed anything else?
Many thanks
Dirk
___
U-Boot
Disable the warm reset and enable the cold reset for a more reliable
restart ('reset'). This is taken from the Linux kernel, see imx_src_init()
in arch/arm/mach-imx/src.c.
Signed-off-by: Dirk Behme dirk.be...@de.bosch.com
---
arch/arm/cpu/armv7/mx6/soc.c | 18 ++
1 file changed
.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Reported-by: York Sun york...@freescale.com
Acked-by: Dirk Behme dirk.be...@gmail.com
This fixes the issue [1] for me :)
I'd propose to apply this to 2015.01-rc3.
Thanks!
Dirk
[1] http://lists.denx.de/pipermail/u-boot/2014-December
On 23.11.2014 23:20, Simon Glass wrote:
Hi,
On 21 November 2014 at 16:36, York Sun york...@freescale.com wrote:
Simon,
Shall we consider host error to be an error reported by buildman? I happen to
try a newer version of toolchain from Linaro. Buildman reports this error
Signed-off-by: Dirk Behme dirk.be...@gmail.com
---
tools/buildman/README | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tools/buildman/README b/tools/buildman/README
index bfb2f18..0f8ea20 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -42,7
...@denx.de
Cc: Dirk Behme dirk.be...@gmail.com
Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/spi/mxc_spi.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index f3f029d..3cd93cf 100644
--- a/drivers/spi
On 02.04.2014 05:33, nitin.g...@freescale.com wrote:
From: Nitin Garg nitin.g...@freescale.com
A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg
On 02.04.2014 05:33, nitin.g...@freescale.com wrote:
From: Nitin Garg nitin.g...@freescale.com
Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
diagnostic register
Acked-by: Dirk Behme dirk.be...@de.bosch.com
Best regards
Dirk
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
=imx_3.0.35_4.1.0
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Acked-by: Dirk Behme dirk.be...@gmail.com
Thanks
Dirk
---
Changes since v3:
- Enable l2 cache using the same method as the kernel
Changes since v2:
- Add L2_PL310_BASE definition in imx_regs.h
Changes since v1:
- Fx typo
Hi Fabio,
Am 28.01.2014 15:54, schrieb Fabio Estevam:
Add L2 cache support and enable it by default.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v2:
- Add L2_PL310_BASE definition in imx_regs.h
Changes since v1:
- Fx typo in commit log
Hi Fabio,
On 08.01.2014 14:59, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
According to e9fd66defd (ARM: mx6: define CONFIG_ARM_ERRATA_742230), the
CONFIG_ARM_ERRATA_742230 option should only be applied to multi-core
variants, so restrict its usage for quad and
Am 27.10.2013 18:07, schrieb Detlev Zundel:
...
** Configuring U-Boot through device tree
- _What_ should be configured?
- Google requires every new U-Boot driver to be configured through
device tree in U-Boot
- Configuring U-Boot through device trees shall aim for using the
exact same
Am 19.08.2013 15:55, schrieb Fabio Estevam:
Hi,
I notice slow tftp transfer on mx53qsb and I suspected it could be due
to L2 cache being disabled.
Tried enabling with:
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -45,6 +45,11 @@
#endif
On 26.07.2013 15:42, Andy Green wrote:
On 26 July 2013 20:58, Wolfgang Denk w...@denx.de wrote:
...
you not make sure that you provide optimized implementations for such
functions and consequently #define __HAVE_ARCH_MEMMOVE (and
__HAVE_ARCH_MEMCPY) ?
Yes I found these afterwards...
for bits
19-18 of DRAM_RESET.
My thanks go to Liu Hui(Jason) for this information.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Acked-by: Dirk Behme dirk.be...@de.bosch.com
Thanks
Dirk
---
board/boundary/nitrogen6x/ddr-setup.cfg | 2 +-
1 file changed, 1 insertion(+), 1
.
Signed-off-by: Dirk Behme dirk.be...@de.bosch.com
---
drivers/mmc/fsl_esdhc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 973b19f..431dac2 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
this by inverting the order of the direction/set_value
calls.
Signed-off-by: Dirk Behme dirk.be...@de.bosch.com
---
drivers/gpio/mxc_gpio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index a388064..1d820d4 100644
Dear Wolfgang and Tom,
Am 03.07.2013 11:54, schrieb Wolfgang Denk:
Dear Xiangfu Liu,
In message 4e95a3ba.8000...@pobox.com you wrote:
Add support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device
from Qi hardware:
http://en.qi-hardware.com/wiki/Ben_NanoNote
'emi_slow_pof' to more consistent
'emi_slow_podf'.
Signed-off-by: Jason Liu r64...@freescale.com
Signed-off-by: Andrew Gabbasov andrew_gabba...@mentor.com
Acked-by: Dirk Behme dirk.be...@de.bosch.com
Thanks
Dirk
---
arch/arm/cpu/armv7/mx6/clock.c |8
1 file changed, 4 insertions
Hi,
hopefully ;) a short question: We found that the commit
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=3c945542dad99b1ec4a324ad6b69b8de8829827b
contains two files
board/qi/qi_lb60/qi_lb60.c
include/configs/qi_lb60.h
which seem to be GPL v3 *only*.
Is this ok for U-Boot?
Many thanks
Am 19.06.2013 11:16, schrieb Pierre Aubert:
Signed-off-by: Pierre Aubert p.aub...@staubli.com
CC: Stefano Babic sba...@denx.de
Acked-by: Dirk Behme dirk.be...@gmail.com
Thanks
Dirk
---
arch/arm/include/asm/arch-mx6/imx-regs.h |2 +-
1 files changed, 1 insertions(+), 1 deletions
On 10.06.2013 16:51, Gabbasov, Andrew wrote:
Hi Dirk,
From: Behme, Dirk - Bosch
Sent: Monday, June 10, 2013 16:06
To: Gabbasov, Andrew
Cc: u-boot@lists.denx.de; Stefano Babic; Fleming Andy-AFLEMING
Subject: Re: [U-Boot] [Patch] fsl_esdhc: Fix DMA
between the first
command and interrupts masking.
Reported-by: Dirk Behme dirk.be...@de.bosch.com
Signed-off-by: Andrew Gabbasov andrew_gabba...@mentor.com
Acked-by: Dirk Behme dirk.be...@de.bosch.com
Thanks
Dirk
---
drivers/mmc/fsl_esdhc.c |7 +++
1 file changed, 3 insertions
On 11.05.2013 07:25, Dirk Behme wrote:
The spi clock divisor is of the form x * (2**y), or x y, where x is
1 to 16, and y is 0 to 15. Note the similarity with floating point numbers.
Convert the desired divisor to the smallest number which is = desired divisor,
and can be represented
On 08.04.2013 11:06, Andrew Gabbasov wrote:
Rework the waiting for transfer completion loop condition
to continue waiting until both Transfer Complete and DMA End
interrupts occur. Checking of DLA bit in Present State register
looks not needed in addition to interrupts status checking,
so it can
On 30.05.2013 12:02, Andrew Gabbasov wrote:
The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro
(shifted and or'ed with chip select), so it's incorrect to pass
that macro directly as an argument to gpio_direction_output() call.
The gpio number should be extracted (shifted back)
On 30.05.2013 13:32, Gabbasov, Andrew wrote:
Hi Dirk,
From: Behme, Dirk - Bosch
Sent: Thursday, May 30, 2013 14:50
To: Gabbasov, Andrew
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH] mx6: mx6qsabrelite/nitrogen6x: Fix use of gpio
number in SF
[] = {
void setup_spi(void)
{
- gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
ARRAY_SIZE(ecspi1_pads));
}
Acked-by: Dirk Behme dirk.be...@de.bosch.com
Thanks
Dirk
.
Signed-off-by: Dirk Behme dirk.be...@gmail.com
---
This patch is marked as RFC due to two questions:
1) These ARM instructions are available in ARMv6 and above. Do we have to limit
this code somehow to = ARMv6? I couldn't find any #define to do this in
U-Boot (?)
2) I'm not sure about
Am 10.05.2013 18:56, schrieb Måns Rullgård:
Dirk Behme dirk.be...@gmail.com writes:
Use the specialized ARM instructions for swapping 16 and 32 bit values
instead of using the generic ones from include/linux/byteorder/swab.h.
The x86 version in arch/x86/include/asm/byteorder.h was taken
Am 10.05.2013 20:44, schrieb Troy Kisky:
On 5/9/2013 10:34 PM, Dirk Behme wrote:
Am 09.05.2013 20:00, schrieb Troy Kisky:
On 5/8/2013 10:19 PM, Dirk Behme wrote:
The spi clock divisor is of the form x * (2**y), or x y, where
x is
1 to 16, and y is 0 to 15. Note the similarity
a divisor
which could be almost twice as large as needed.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Signed-off-by: Dirk Behme dirk.be...@gmail.com
---
Notes:
- Changes in v2: Make the alogrithm simpler by removing the -1 as proposed
by Troy. Make the pre_div
Am 09.05.2013 20:00, schrieb Troy Kisky:
On 5/8/2013 10:19 PM, Dirk Behme wrote:
The spi clock divisor is of the form x * (2**y), or x y, where
x is
1 to 16, and y is 0 to 15. Note the similarity with floating point
numbers.
Convert the desired divisor to the smallest number which
-by: Dirk Behme dirk.be...@gmail.com
---
Note: Changes in v2: Use pre_div divider /16 instead of /15 in the
first version of this patch.
drivers/spi/mxc_spi.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index
a divisor
which could be almost twice as large as needed.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Signed-off-by: Dirk Behme dirk.be...@gmail.com
---
drivers/spi/mxc_spi.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/spi
Am 03.05.2013 22:47, schrieb Troy Kisky:
On 5/2/2013 10:58 PM, Dirk Behme wrote:
Do you want to say you propose
post_div = pre_div / 16;
pre_div = 16;
?
yes, that's what I said
If so:
First, I agree that we have to use the same dividers in both lines.
But, second, this would mean
From: Dirk Behme dirk.be...@gmail.com
Fix two issues with the calculation of pre_div and post_div:
1. pre_div: While the calculation of pre_div looks correct, to set the
CONREG[15-12] bits pre_div needs to be decremented by 1:
The i.MX 6Dual/6Quad Applications Processor Reference Manual
On 02.05.2013 20:38, Troy Kisky wrote:
On 5/2/2013 3:59 AM, Dirk Behme wrote:
From: Dirk Behme dirk.be...@gmail.com
Fix two issues with the calculation of pre_div and post_div:
1. pre_div: While the calculation of pre_div looks correct, to set the
CONREG[15-12] bits pre_div needs
Am 14.04.2013 09:08, schrieb Dirk Behme:
Am 10.04.2013 01:06, schrieb Fabio Estevam:
From: Fabio Estevam fabio.este...@freescale.com
The glitch in the SPI clock line, which commit 3cea335c34 (spi:
mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas
re-introduced by
commit
Am 10.04.2013 01:06, schrieb Fabio Estevam:
From: Fabio Estevam fabio.este...@freescale.com
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset
Am 08.04.2013 11:06, schrieb Andrew Gabbasov:
Rework the waiting for transfer completion loop condition
to continue waiting until both Transfer Complete and DMA End
interrupts occur. Checking of DLA bit in Present State register
looks not needed in addition to interrupts status checking,
so it
Am 06.04.2013 02:55, schrieb Fabio Estevam:
From: Fabio Estevam fabio.este...@freescale.com
mx6slevk board is a development board from Freescale based on the mx6 solo-lite
processor.
For details about mx6slevk, please refer to:
Am 06.04.2013 15:15, schrieb Fabio Estevam:
From: Fabio Estevam fabio.este...@freescale.com
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset
Am 06.04.2013 14:47, schrieb Fabio Estevam:
Hi Dirk,
On Sat, Apr 6, 2013 at 4:27 AM, Dirk Behme dirk.be...@gmail.com wrote:
+DATA 4 0x020c4068 0x
+DATA 4 0x020c406c 0x
+DATA 4 0x020c4070 0x
+DATA 4 0x020c4074 0x
+DATA 4 0x020c4078 0x
+DATA 4 0x020c407c
Am 06.04.2013 16:15, schrieb Fabio Estevam:
On Sat, Apr 6, 2013 at 10:52 AM, Dirk Behme dirk.be...@gmail.com wrote:
Most probably it would be sufficient to enable only the clocks needed for
booting ;) And not all clocks. On the other boards we do
/* set the default clock gate to save power
Am 06.04.2013 18:40, schrieb Fabio Estevam:
Hi Dirk,
On Sat, Apr 6, 2013 at 1:30 PM, Dirk Behme dirk.be...@gmail.com wrote:
... but saving power over the whole (kernel) runtime. I might be wrong, but
to my understanding the kernel doesn't *disable* unneeded clocks?
So it's up
width support
will be enabled in host capabilities otherwise host capabilities are modified
accordingly.
It is tested with a MMCplus card.
Signed-off-by: Abbas Raza abbas_r...@mentor.com
cc: stefano Babic sba...@denx.de
cc: Andy Fleming aflem...@gmail.com
Acked-by: Dirk Behme dirk.be
Am 03.04.2013 11:12, schrieb Stefano Babic:
On 21/03/2013 09:03, Dirk Behme wrote:
Reviewing the ECSPI reset handling shows two issues:
Hi Dirk,
agree completely, only a very minor question..
+
+ reg_ctrl = reg_read(regs-ctrl);
As you says, it makes no sense to read back
Am 02.04.2013 17:49, schrieb Eric Nelson:
Thanks Andrew,
On 04/02/2013 03:04 AM, Andrew Gabbasov wrote:
On iMX6 sometimes the Transfer Complete interrupt occurs earlier
than the DMA part completes its operation. If immediately after that
the read data is used for some data verification, those
Hi Fabio,
Am 30.03.2013 22:08, schrieb Fabio Estevam:
From: Fabio Estevam fabio.este...@freescale.com
mx6slevk board is a development board from Freescale based on the mx6 solo lite
processor.
For details about mx6slevk, please refer to:
for get_board_rev are:
0x63xxx: For mx6quad/dual
0x61xxx: For mx6dual-lite/solo
So adjust get_board_rev() accordingly and make it as weak function, so that we
do not need to define it in every mx6 board file.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Acked-by: Dirk Behme dirk.be
On 26.03.2013 18:04, Fabio Estevam wrote:
Hi Dirk,
On Tue, Mar 26, 2013 at 12:43 PM, Dirk Behme dirk.be...@de.bosch.com wrote:
Hi Fabio,
On 26.03.2013 13:54, Fabio Estevam wrote:
Currently when booting a mx6 solo processor get_cpu_rev() returns 0x62xxx,
which
is an invalid mx6 CPU revision
On 27.03.2013 09:02, Dirk Behme wrote:
On 26.03.2013 18:04, Fabio Estevam wrote:
Hi Dirk,
On Tue, Mar 26, 2013 at 12:43 PM, Dirk Behme dirk.be...@de.bosch.com
wrote:
Hi Fabio,
On 26.03.2013 13:54, Fabio Estevam wrote:
Currently when booting a mx6 solo processor get_cpu_rev() returns
On 27.03.2013 14:37, Fabio Estevam wrote:
On Wed, Mar 27, 2013 at 5:57 AM, Dirk Behme dirk.be...@de.bosch.com wrote:
Some additional rethinking: I missed that we have a Linux kernel, too ;)
c) It's the job of the Linux kernel to export the CPU revision to the VPU
library. In case the Linux
Hi Eric,
On 27.03.2013 15:00, Eric Nelson wrote:
Hi Fabio,
On 03/27/2013 06:37 AM, Fabio Estevam wrote:
On Wed, Mar 27, 2013 at 5:57 AM, Dirk Behme dirk.be...@de.bosch.com wrote:
Some additional rethinking: I missed that we have a Linux kernel, too ;)
c) It's the job of the Linux kernel
Hi Fabio,
On 27.03.2013 18:36, Fabio Estevam wrote:
When booting a Freescale kernel 3.0.35 on a Wandboard solo, the get_board_rev()
returns 0x62xxx, which is not a value understood by the VPU
(Video Processing Unit) library in the kernel and causes the video playback to
fail.
The expected
Am 27.03.2013 20:36, schrieb Fabio Estevam:
Hi Dirk,
On Wed, Mar 27, 2013 at 3:56 PM, Dirk Behme dirk.be...@gmail.com wrote:
This is much better than changing Troy's get_cpu_rev(). Thanks :)
I am glad you like it :-)
But what's about to add this code to
http://git.freescale.com/git
);
--
==
Dirk Behme Robert Bosch Car Multimedia GmbH
CM-AI/PJ-CF32
Phone: +49 5121 49-3274 Dirk Behme
Fax: +49 711 811 5053274 PO Box 77 77 77
mailto:dirk.be...@de.bosch.com D-31132 Hildesheim
driver wants to configure.
I.e. we need a clean reset of SPI block, including the CONREG.
Signed-off-by: Dirk Behme dirk.be...@de.bosch.com
CC: Stefano Babic sba...@denx.de
CC: Fabio Estevam fabio.este...@freescale.com
---
drivers/spi/mxc_spi.c |8
1 files changed, 4 insertions(+), 4
Am 15.03.2013 22:06, schrieb Fabio Estevam:
From: Fabio Estevam fabio.este...@freescale.com
Instead of hardcoding the CPU revision, it is better to use get_cpu_rev().
I think to remember that there is a reason why it is hard coded this
way. Have you tested this with the Vivante GPU driver?
Am 16.03.2013 17:13, schrieb Eric Nelson:
On 03/16/2013 07:58 AM, Fabio Estevam wrote:
Hi Eric,
On Fri, Mar 15, 2013 at 9:20 PM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
This is the **board** revision, right?
At first glance, the kernel seems to be getting the silicon revision
On 04.03.2013 15:16, Dirk Behme wrote:
From: Knut Wohlrab knut.wohl...@de.bosch.com
The i.MX6 common timer uses the 32-bit variable tbl (time base lower)
to record the overflow of the 32-bit counter. I.e. if the counter
overflows, the variable tbl does overflow, too.
To capture this overflow
From: Dirk Behme dirk.be...@de.bosch.com
Several ARM timer implementations use gd-arch.tbl to record the
absolute tick count of 32-bit counters, including timer overflows.
For example arch/arm/imx-common/timer.c does:
ulong lastinc;
ulong now = counter value;
if (no overflow
), too.
Return the combined value of tbl and tbu.
lastinc is unused then, remove it.
Signed-off-by: Knut Wohlrab knut.wohl...@de.bosch.com
Signed-off-by: Dirk Behme dirk.be...@de.bosch.com
---
Note: This replaces the patch
http://patchwork.ozlabs.org/patch/224646/
arch/arm/imx-common/timer.c
Dear Wolfgang,
On 04.03.2013 12:10, Wolfgang Denk wrote:
Dear Dirk Behme,
In message 1362387637-32334-1-git-send-email-dirk.be...@de.bosch.com you
wrote:
From: Dirk Behme dirk.be...@de.bosch.com
Several ARM timer implementations use gd-arch.tbl to record the
absolute tick count of 32-bit
Am 15.02.2013 21:45, schrieb Chaves, Kevin:
Hi,
First off, sorry I'm not used to using mailing lists. I'm not sure if this is
the best way to dig for information. We've recently switched to uboot/linux
from wince and I'm trying to understand how configuring uboot works. I'm also
trying to
From: Knut Wohlrab knut.wohl...@de.bosch.com
The USB host interface is routed to plug USB1/J30 on the mother board.
Signed-off-by: Knut Wohlrab knut.wohl...@de.bosch.com
---
Changes in v2:
- Don't add an empty board_ehci_hcd_init() to mx6qsabreauto.c. It's
not needed because
On 16.01.2013 23:54, Simon Glass wrote:
Hi Wolfgang,
On Wed, Jan 16, 2013 at 2:40 PM, Wolfgang Denk w...@denx.de wrote:
Dear Simon Glass,
In message CAPnjgZ3rNhvL98JEOPV=90u-Wr3iEqs8QgqYaz=boohrfrj...@mail.gmail.com
you wrote:
The problem is that a major purpose of the GUIs is to allow
From: Knut Wohlrab knut.wohl...@de.bosch.com
The USB host interface is routed to plug USB1/J30 on the mother board.
Signed-off-by: Knut Wohlrab knut.wohl...@de.bosch.com
---
board/freescale/mx6qsabreauto/mx6qsabreauto.c |7 +++
include/configs/mx6qsabreauto.h | 11
On 03.01.2013 19:24, Fabio Estevam wrote:
In order to mx53 ROM to properly load the U-boot image, its header size should
be multiple of 512 bytes.
...
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
-
On 26.11.2012 17:03, Benoît Thébaudeau wrote:
Hi Eric, all,
On Thursday, August 23, 2012 3:23:20 PM, Eric Nelson wrote:
On 08/23/2012 03:31 AM, Stefano Babic wrote:
On 22/08/2012 12:43, Dirk Behme wrote:
On 14.08.2012 14:52, Benoît Thébaudeau wrote:
This can be useful for fuse-like hardware
Am 16.11.2012 12:30, schrieb Fabio Estevam:
From: Fabio Estevam fabio.este...@freescale.com
If a board does not enable CSPI, there is no need to show the CSPI clock
frequency as part of the 'clock' command.
Reported-by: Dirk Behme dirk.be...@gmail.com
Signed-off-by: Fabio Estevam fabio.este
Am 15.11.2012 22:23, schrieb Fabio Estevam:
From: Fabio Estevam fabio.este...@freescale.com
Print CSPI clock in 'clock' command.
Signed-off-by: Fabio Estevam feste...@gmail.com
---
arch/arm/cpu/armv7/mx5/clock.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
On 13.11.2012 17:31, Andreas Bießmann wrote:
Signed-off-by: Andreas Bießmann andreas.de...@googlemail.com
Cc: Marek Vasut ma...@denx.de
Cc: Wolfgang Denk w...@denx.de
Tested-by: Dirk Behme dirk.be...@de.bosch.com
Thanks
Dirk
---
Makefile |2 +-
1 file changed, 1 insertion(+), 1
On 23.09.2012 17:56, Stefano Babic wrote:
On 22/09/2012 16:37, Fabio Estevam wrote:
On Sat, Sep 22, 2012 at 10:42 AM, Otavio Salvador
ota...@ossystems.com.br wrote:
Hello Eric,
On Fri, Sep 21, 2012 at 5:36 PM, Eric Nelson
eric.nel...@boundarydevices.com wrote:
Signed-off-by: Eric
Hi Troy,
On 22.09.2012 04:38, Troy Kisky wrote:
After this series the same binary will run on a
Saberlite board using any of the pin compatible processors
mx6 quad, mx6 duallite, or mx6 solo. This is accomplished
using a plugin and a table built by mkimage.
Could you briefly explain or give a
On 17.09.2012 18:34, Fabio Estevam wrote:
lowlevel_init.S is not used on mx6,
Yes, but ...
We use lowlevel_init.S on a not yet public custom board to do some
early, custom specific initialization. So I would vote to keep this.
But most probably non-mainline code isn't a reason to keep
On 15.09.2012 05:06, Fabio Estevam wrote:
Hi Jason,
I don't have a mx6qarm2 and would like to ask you if you could please
confirm that Ethernet is functional on mx6qarm2 running the latest
U-boot.
I am trying to get Ethernet working on mx6qsabresd, which also uses
the same AR8031 PHY, but it
On 15.09.2012 05:06, Fabio Estevam wrote:
Hi Jason,
I don't have a mx6qarm2 and would like to ask you if you could please
confirm that Ethernet is functional on mx6qarm2 running the latest
U-boot.
I am trying to get Ethernet working on mx6qsabresd, which also uses
the same AR8031 PHY, but it
On 11.09.2012 18:32, Carolyn Smith wrote:
Thanks to Dirk for your previous advice. We had a pullup on one of the
reserved BOOT_CFG pins that caused problems accessing NOR flash.
Now I can put code in the NOR flash. If the code is incorrect in some way
(not sure how yet), I end up with a board
On 07.09.2012 20:41, Carolyn Smith wrote:
Hello,
I have a custom i.MX6 board that is configured to boot from 16-bit parallel
NOR flash using non-multiplexed I/O with the data on the upper half of the
data bus. I.e. chip select 0 of the EIM bus should be configured so that
MUM = 0 and DSZ =
On 11.09.2012 05:56, Fabio Estevam wrote:
Hi Stefano,
On Thu, Apr 12, 2012 at 7:52 AM, Stefano Babic sba...@denx.de wrote:
This file is identical to imximage.cfg for the mx6qsabrelite board. I
can imagine this is derived board. Why cannot we implement it as a
variant of the original one ? We
On 22.08.2012 13:11, Benoît Thébaudeau wrote:
Hi Dirk,
On Wednesday, August 22, 2012 12:43:05 PM, Dirk Behme wrote:
On 14.08.2012 14:52, Benoît Thébaudeau wrote:
This can be useful for fuse-like hardware, OTP SoC options, etc.
For i.MX6, I have a port of the OTP support from Freescale's U
list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
--
==
Dirk Behme Robert Bosch Car Multimedia GmbH
CM-AI/PJ-CF32
Phone: +49 5121 49-3274 Dirk Behme
The recent U-Boot version 2012.07 has improved drivers
(e.g. MMC and network/FEC) regarding DCache handling.
So it should be safe to use the DCache on the i.MX6, now.
Signed-off-by: Dirk Behme dirk.be...@de.bosch.com
---
include/configs/mx6qsabrelite.h |3 +--
1 files changed, 1 insertions
On 01.08.2012 13:05, Dirk Behme wrote:
A recent Linux kernel (= 3.5) has support for the SGTL 5000 sound
on the SabreLite board. To make this work, U-Boot has to configure the
pin mux for PAD_GPIO_0__CCM_CLKO and PAD_GPIO_3__CCM_CLKO2 correctly.
Taken from Freescale's ER5 U-Boot
A recent Linux kernel (= 3.5) has support for the SGTL 5000 sound
on the SabreLite board. To make this work, U-Boot has to configure the
pin mux for PAD_GPIO_0__CCM_CLKO and PAD_GPIO_3__CCM_CLKO2 correctly.
Taken from Freescale's ER5 U-Boot for the SabreLite.
Signed-off-by: Dirk Behme dirk.be
On 01.08.2012 13:26, Liu Hui-R64343 wrote:
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
On Behalf Of Dirk Behme
Sent: Wednesday, August 01, 2012 7:06 PM
To: u-boot@lists.denx.de
Cc: Dirk Behme
Subject: [U-Boot] [PATCH] mx6q: mx6qsabrelite
On 01.08.2012 14:55, Wolfgang Denk wrote:
Dear Dirk Behme,
In message 5019180c.4060...@de.bosch.com you wrote:
It seems to me that the SGTL5000 kernel feature for the SabreLite was
developed with a Freescale U-Boot (patching the kernel with DT append)
and not tested with the mainline U-Boot
On 01.08.2012 15:33, Thomas Petazzoni wrote:
Le Wed, 1 Aug 2012 15:22:30 +0200,
Dirk Behme dirk.be...@de.bosch.com a écrit :
Probably. But the question is still why this should be changed in
U-Boot. Why doesn't the Linux driver set the pin mux configuration
it needs?
Sorry, I don't know
Hi,
now, after U-Boot v2012.07 is released, I'd like to ask what's the
status the dcache support for i.MX(6)? Is it safe to enable
CONFIG_SYS_DCACHE_OFF now? E.g. for the SabreLite [1]?
And if so, do we have to enable CONFIG_MMC_BOUNCE_BUFFER, too?
Opinions?
Many thanks and best regards
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