On 5.12.2017 08:37, Goldschmidt Simon wrote:
> On 5.12.2017 08:22, Michal Simek wrote:
>>> Which release will this be in? Does it fit into 2018.01 or has that
>>> window already closed?
>>
>> I believe so.
>
> Sorry to bother you again, I'm just not sure I understood your answer.
>
> Was that "I
On 5.12.2017 08:22, Michal Simek wrote:
> > Which release will this be in? Does it fit into 2018.01 or has that
> > window already closed?
>
> I believe so.
Sorry to bother you again, I'm just not sure I understood your answer.
Was that "I beleive so" meant as "yes, 2018.01 unless someone reject
On 4.12.2017 21:14, Goldschmidt Simon wrote:
>
> Hi,
>
> On 4.12.2017 15:27, Michal Simek wrote:
>> [..]
>> ok. Then applied to my xilinx tree.
>
> Great to hear that, thanks!
>
> Which release will this be in? Does it fit into 2018.01 or has that
> window already closed?
I believe so.
Thanks
Hi,
On 4.12.2017 15:27, Michal Simek wrote:
> [..]
> ok. Then applied to my xilinx tree.
Great to hear that, thanks!
Which release will this be in? Does it fit into 2018.01 or has that
window already closed?
Thanks,
Simon
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Hi,
On 2.12.2017 04:29, Simon Glass wrote:
> Hi Michal,
>
> On 29 November 2017 at 03:00, Michal Simek wrote:
>> On 29.11.2017 06:20, Goldschmidt Simon wrote:
>>> On 28.11.2017 14:46, Michal Simek wrote:
On 28.11.2017 10:08, Goldschmidt Simon wrote:
> Simon Goldschmidt wrote:
>> Hi
Hi Michal,
On 29 November 2017 at 03:00, Michal Simek wrote:
> On 29.11.2017 06:20, Goldschmidt Simon wrote:
>> On 28.11.2017 14:46, Michal Simek wrote:
>>> On 28.11.2017 10:08, Goldschmidt Simon wrote:
Simon Goldschmidt wrote:
> Hi Simon,
>
> Simon Glass wrote:
>> I see that
On 29.11.2017 06:20, Goldschmidt Simon wrote:
> On 28.11.2017 14:46, Michal Simek wrote:
>> On 28.11.2017 10:08, Goldschmidt Simon wrote:
>>> Simon Goldschmidt wrote:
Hi Simon,
Simon Glass wrote:
> I see that, although it is adding to the fpga header so presumably
> making it
On 24.11.2017 23:35, Simon Glass wrote:
> Hi Simon,
>
> On 20 November 2017 at 22:38, Goldschmidt Simon
> wrote:
>> Hi,
>>
>>> Simon Glass wrote:
>>> On 10 November 2017 at 07:17, Goldschmidt Simon >> fuchs.com> wrote:
This drops the limit that fpga is only loaded from FIT images for Xilinx.
On 28.11.2017 14:46, Michal Simek wrote:
> On 28.11.2017 10:08, Goldschmidt Simon wrote:
>> Simon Goldschmidt wrote:
>>> Hi Simon,
>>>
>>> Simon Glass wrote:
I see that, although it is adding to the fpga header so presumably
making it harder for someone to move this over.
>>>
>>> Yes, I'm
On 28.11.2017 10:08, Goldschmidt Simon wrote:
> Simon Goldschmidt wrote:
>> Hi Simon,
>>
>> Simon Glass wrote:
>>> I see that, although it is adding to the fpga header so presumably
>>> making it harder for someone to move this over.
>>
>> Yes, I'm not happy with changing the header and even xilinx
Simon Goldschmidt wrote:
> Hi Simon,
>
> Simon Glass wrote:
> > I see that, although it is adding to the fpga header so presumably
> > making it harder for someone to move this over.
>
> Yes, I'm not happy with changing the header and even xilinx C file to add
> functionality for altera. However,
Hi Simon,
Simon Glass wrote:
> I see that, although it is adding to the fpga header so presumably
> making it harder for someone to move this over.
Yes, I'm not happy with changing the header and even xilinx C file to add
functionality for altera. However, this is due to the fact that a core fil
Hi Simon,
On 20 November 2017 at 22:38, Goldschmidt Simon
wrote:
> Hi,
>
>> Simon Glass wrote:
>> On 10 November 2017 at 07:17, Goldschmidt Simon > fuchs.com> wrote:
>> > This drops the limit that fpga is only loaded from FIT images for Xilinx.
>> > This is done by moving the 'partial' check from
Hi,
> Simon Glass wrote:
> On 10 November 2017 at 07:17, Goldschmidt Simon fuchs.com> wrote:
> > This drops the limit that fpga is only loaded from FIT images for Xilinx.
> > This is done by moving the 'partial' check from 'common/image.c' to
> > 'drivers/fpga/xilinx.c' (the only driver supportin
Hi,
On 10 November 2017 at 07:17, Goldschmidt Simon
wrote:
> This drops the limit that fpga is only loaded from FIT images for Xilinx.
> This is done by moving the 'partial' check from 'common/image.c' to
> 'drivers/fpga/xilinx.c' (the only driver supporting partial images yet)
> and supplies a w
This drops the limit that fpga is only loaded from FIT images for Xilinx.
This is done by moving the 'partial' check from 'common/image.c' to
'drivers/fpga/xilinx.c' (the only driver supporting partial images yet)
and supplies a weak default implementation in 'drivers/fpga/fpga.c'.
Signed-off-by:
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