> > Make it an array?
>
> If that works for you, it works for me. Thanks!
>
> #define __mx28_reg_8(name) \
> uint8_t name##[4]; \
> uint8_t name##[4]_set; \
> uint8_t name##[4]_clr; \
> uint8_t name##[4]_tog;
Might be
__
> Make it an array?
If that works for you, it works for me. Thanks!
#define __mx28_reg_8(name) \
uint8_t name##[4]; \
uint8_t name##[4]_set; \
uint8_t name##[4]_clr; \
uint8_t name##[4]_tog;
__
> > Awesome. So after reading your replies, let's just rename mx28_reg to
> > mx28_reg_32 and introduce mx28_reg_8 for this particular problem.
>
> You were probably already foreseeing this when you made your
> suggestion to use accessors, but now I'm working it I see introducing
> mx28_reg_8 may
> Awesome. So after reading your replies, let's just rename mx28_reg to
> mx28_reg_32 and introduce mx28_reg_8 for this particular problem.
You were probably already foreseeing this when you made your
suggestion to use accessors, but now I'm working it I see introducing
mx28_reg_8 may get too mess
> Hi,
>
> > you're only writing data to the register, not clearing them. So maybe
> > some bits remain set?
>
> The assignment will work here. There're only 8 bits, of which 6 are the
> fractional divider, one is de read-only stable indicator (unaffected by
> writes) and the last one is the gatin
Hi,
> I was thinking of this and we might need to introduce either special accessor
> for this particular register or rework include/regs-common.h and introduce
> mx28_reg_8 (which I don't think is a good idea).
I tend to agree with you about introducing mx28_reg_8. It doesn't 'feel right'
becaus
Hi,
> you're only writing data to the register, not clearing them. So maybe some
> bits
> remain set?
The assignment will work here. There're only 8 bits, of which 6 are the
fractional
divider, one is de read-only stable indicator (unaffected by writes) and the
last
one is the gating bit.
The
> You can write:
> writeb(19 , &clkctrl_regs->hw_clkctrl_frac0);
Yes, for the first byte I can (and do), but the three higher bytes
would get ugly with this method:
writeb(bitset >> 8, (unit8_t*)&clkctrl_regs->hw_clkctrl_frac0 + 1);
___
U-Boot mailing li
Hi Fabio,
> Very good, Robert! I tested your patch and it fixes the reboot issue
> on my mx28evk.
You're most welcome! I'm glad to hear it fixes your problem too.
> Also checked in the MX28 Reference Manual about the fact that
> hw_clkctrl_frac0 can only be accessed as bytes.
It's easy to overl
> Hi,
>
> This patch fixes ref_cpu clock setup. This bug leads to a hanging board
> after rebooting from the Kernel, due to failing memory size detection:
> U-Boot 2011.12-svn342 (Feb 02 2012 - 17:20:00)
>
> Freescale i.MX28 family
> I2C: ready
> DRAM: 0 Bytes
>
> The cause of the bug is regi
> Hi,
>
> This patch fixes ref_cpu clock setup. This bug leads to a hanging board
> after rebooting from the Kernel, due to failing memory size detection:
> U-Boot 2011.12-svn342 (Feb 02 2012 - 17:20:00)
>
> Freescale i.MX28 family
> I2C: ready
> DRAM: 0 Bytes
>
> The cause of the bug is regi
On 2/2/12, Robert Deliën wrote:
> Ideally I'd like to set up these registers as uint8_t*. Any ideas? I'll also
> check if bye-lane shifting is done automatically here.
You can write:
writeb(19 , &clkctrl_regs->hw_clkctrl_frac0);
Regards,
Fabio Estevam
__
> > 2. Please grep the locations where hw_clkctrl_frac0 is assigned as
> > 32-bit and change those as well.
>
> Please do the same for hw_clkctrl_frac1 as well. There is one location
> in clock.c where it is read as 32-bit.
I will check all hw_clkctrl_frac* register access, but tomorrow because
t
On 2/2/12, Fabio Estevam wrote:
> 2. Please grep the locations where hw_clkctrl_frac0 is assigned as
> 32-bit and change those as well.
Please do the same for hw_clkctrl_frac1 as well. There is one location
in clock.c where it is read as 32-bit.
Thanks,
Fabio Estevam
__
Hi Robert,
On 2/2/12, Robert Deliën wrote:
> Hi,
>
> This patch fixes ref_cpu clock setup. This bug leads to a hanging board
> after rebooting from the Kernel, due to failing memory size detection:
> U-Boot 2011.12-svn342 (Feb 02 2012 - 17:20:00)
>
>
> Freescale i.MX28 family
>
> I2C: ready
>
>
15 matches
Mail list logo
