> Arrr, my insanity. Wolfgang is correct, of course.
>
Gee, and I was just going to ask why on earth you liked
high-boot :)
I've seen one novel use of high-boot that could make it
useful if you're lazy and can't be bothered plugging in
your debugger ;)
Assuming your board has a toggle switch t
Hi Wolfgang,
> It's already there - see
> http://www.denx.de/wiki/view/DULG/MoreInformationFurtherReading#Section_12.2.4.
Indeed it is :)
Thanks,
Dave
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This SF.Net email is sponsored by the Moblin Your Move Developer's cha
Hi,
I just received an email from Power.org referencing this document:
http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf
"The ePAPR is loosely related to the IEEE 1275 Open Firmware
standard—IEEE Standard for Boot (Initialization Configuration)
Firmware: Core Require
> I have a copy of the Verilog code used in the BCSR
I took a closer look at the Verilog code. Searching
for the I/O port nBCSR_CS within the code shows that
it is synchronized through a single register to the 33MHz
clock (which comes from on-board oscillator, not the
processor) to generate the s
Hi Dave,
> I believe it is timing issue.
> The BCSR read(#LOE) has not enough setup time.
> You may try the two solutions:
> (a) slow down local bus clock
> If you are using default configuration, the local bus clock is
> 66MHz. change the LCRR from div 4 to div 8 to make the local bus clock
>
Hi all,
We're having a rough week with our Freescale MDS boards.
I've just submitted a service request through
Freescale's online system. However, I figured others
(eg. Kim, and Timur) might be interested in the following
problem:
We have an MPC8349E-MDS-PB and an MPC8349EA-MDS-PB that we
are us
Hi Timur,
> - i2c_bus_speed[0] = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
> + temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
> + if (gd->flags & GD_FLG_RELOC)
> + i2c_bus_speed[0] = temp;
Does i2c_init() get called again after relocation?
If the I2C code is only
Hi Jerry,
> One really good trick is how to hook a logic analyzer to those
> itty-bitty balls on the processor. Back when I was a boy, processors
> had 40 legs and no balls. :-D You must have a board with a logic
> analyzer connector.
Thankfully the Freescale MDS boards do have logic
analyz
Hi Timur,
> I'm working on a patch that blocks i2c_init() from writing to
> global variables before relocation has occurred. But if
> you're saying that this patch should not be necessary,
> then that would be better.
The I2C patch is necessary.
Whatever was written to i2c_bus_speed[0] was neve
Hi Jerry,
>> The fix will also not expose the accidental introduction
>> of flash writes in the future, it'll just stop those
>> writes from having any effect.
>
> IOW, it simply hides the bug. :-(
Yeah, I didn't like that as a solution either.
>> It would be nicer to generate an exception if
Hi Wolfgang,
>> We recently debugged a problem where a Flash write on
>> MPC8349E and MPC8349EA processor boards was accidentally
>> occurring during board initialization.
>
> A write to flash should not matter at all.
Thats what I thought, until I saw the logic analyzer
trace show otherwise ...
Hi all,
We recently debugged a problem where a Flash write on
MPC8349E and MPC8349EA processor boards was accidentally
occurring during board initialization.
Under the right conditions, the write appears to put
the flash into a command-mode, rather than read-data mode,
and further reads from the
Hi Timur,
> FE00_9B90 is in the drivers/i2c/fsl_i2c.c code, which
> explains why Ira would see the 'I2C: ' line before lockup.
>
>
> Someone reported this problem last week while I was on vacation.
Did they post directly to you, or the list? I don't recall
seeing anything ... but then
Hi guys,
As noted in Ira's previous posts, he'd managed to get the
MPC8349E and MPC8349EA boards to fail consistently.
Starting with the U-Boot head, and applying Ira's minimal
BCSR access plus linker 32-byte alignment patch, we used a
BDI2000 to set break-points until we identified the flash
add
Hi Felix,
> I will soon have to port U-Boot to a custom board based on AMCC 460EX CPU.
> This board should be very close to Canyonlands evaluation board, but board
> designers decided to use DDR1 instead of DDR2 present on Canyonlands.
>
> Looking at U-Boot 1.3.3 code, I can see that DDR1 support
Hi Russell,
> Reposting on previous issue that is becoming a lot more painful.
>
> Today, I went to my local PC store, and bought EVERY type of DDR2 SODIMM
> memory they had, Kingston, Crucial, PC4200, PC5300 four different kinds
> of memory, and NONE of them will boot with U-boot now.
>
> We
Hi Timur,
>> In either case, you would use the byte-conversion routines to
>> serialize the descriptor entries in memory, or in the source buffer,
>> into the correct endianness before performing enabling the DMA.
>
> Very true. However, this means that if the original data is in
> the wrong end
Hi Timur,
>> When you are dealing with a driver, register accesses need to be
>> in a specific format. The MPC8349EA has some of its registers
>> in big-endian format, and others in little-endian format.
>> Regardless of the mode you operate your processor, you will
>> *have* to use the correct by
Hi Vivek,
Just to clarify these comments:
> It would be a lot easier if you modified the application to work on big-endian
> and little-endian. Just look through the code in places where the endian
> matters, and add cpu_to_be32() and be32_to_cpu() (or similar functions).
When you are dealing
Hi Vivek,
> Sorry, I forgot to tell that we are using MPC8349E processor
> with a "e300 core". And it is clearly mentioned in the e300
> core datasheet that, it supports "True little-endian mode
> for compatibility with other true little-endian devices".
Data sheets need to be read in the wider c
Hi Vivek
> Now due to some reason we have to configure 8349E in little endian mode.
Perhaps you could explain why you feel you need to use
little-endian mode. Readers of the list could offer
some constructive comments.
Regards,
Dave
--
Hi,
> We have a PowerPC 440 EP (from a AMCC Yosemite evaluation kit)
> and we are in the process of evaluating OSes for it. The
> industrial strength ones (like vxWorks) are too much
> feature-wise and money-wise, so we're hoping to try out uC/OS-II.
>
> If someone has tried to do this before, I
Hi Stefan,
>> There does not appear to be a 460EX User's Manual on
>> the AMCC web site. Anyone know where to get it?
>> I created an account just in case it was not visible
>> to guests, but no change.
>
> It's still preliminary, so you probably need to contact
> your AMCC distributor/FAE to get
Hi Ame,
> So maybe I need to clarify some more. The PPC460 data sheet
> is not too clear on this yet. However, here are my thoughts
> on this. Lets just take the simple case as an example. We
> have a plurality of 460s where a single one is the master.
> Between the master and all the slaves i
Hi Stefan,
>> Here's a few ideas then.
Sorry, all of the ideas were based on the MPC8349EA,
which I am currently using. I did not look at the
ppc460 documents, as I was just putting ideas 'out there'.
When the MPC8349EA is booted, you can enable the peripherals
while leaving the core in reset. T
Hi Ame,
> Given that you don't think any of my suggestions are
> possible, I'll have to go download the ppc460 reference
> manual and convince myself :)
There does not appear to be a 460EX User's Manual on
the AMCC web site. Anyone know where to get it?
I created an account just in case it was no
Hi Ame,
>> Yes, what is the main reason you want to do this?
>
> Ok, here is what I want to do. I have a board that has several PPC460s
> on it. Each has its own DDR2. One of them is the master and boots up
> normally today with uboot, launches linux, etc. What I want to do is
> have that mas
Hi Wolfgang,
> This is not necessarily true. There may be many reasons
> why you still want to run a boot loader (like U-Boot) on
> the PCI device's local processor.
Fair enough.
>> If you want to boot your board over PCI, then the board
>> will most likely be a peripheral board (a host would ne
Hi Ame,
> Hello, I saw a reference to PCI booting in the docs, but could
> not find enough detail. We would like to use PCI memory space
> booting on an upcoming design with the PPC460EX. Does Uboot
> currently support that mode of booting? Is it as easy as booting
> from a flash? We are devel
Hi Joakim,
>> See for example cpu/mpc8xx/start.S - while at the moment we really
>> start with .text, it would technically be more approrpriate to change
>> the first 256 bytes (from monitor base to EXC_OFF_SYS_RESET) into
>> .rodata or something like this.
>
> Ahh, now I see what you mean a
Hi André,
> I was just wondering why there's a need to define the HRCW inside a
> header. This _only_ makes sense for the "HRCW from flash on local
> bus"-section. Any hard coded reset word or the use of an I2C Prom
> does make this obsolete.
Right. But there is also no harm in having it :)
>
Hi Andre,
> In "cpu/mpc83xx/start.S" there is a comment :
>
> /*
> * The Hard Reset Configuration Word (HRCW) table is in the first 64
> * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
> * times so the processor can fetch it out of flash whether the flash
> * is 8, 16, 3
Hi Andre,
> has anyone set up the DDR-II controller on a Freescale MPC8343A without ?
> As far as I can see there are only DDR-I boards from Freescale.
>
> Are there any patches not yet posted to handle this ?
Chances are that the MPC8343 DDR controller is much the same
as the MPC8349EA controll
Hi,
Sorry, for the slightly off-topic post, but I figured
someone else might have faced a similar issue.
I'm in the process of bringing up an MPC8349E PowerPC
based board. The board is configured as a compact PCI
peripheral board. The board will boot U-Boot off
on-board Spansion S29GL-N Flash, an
Second .cfg file
[2/2] BDI .cfg for MPC8349EA-MDS-PB
; bdiGDB configuration file for MPC8349EA-MDS-PB board
;--
;
; 2/14/2008 D. W. Hawkins ([EMAIL PROTECTED])
;
; The Freescale MPC8349E/EA PowerQUICC II PowerPC processor
; has two
Hi all,
I've written a couple of BDI2000 .cfg files, with
register settings consistent with the latest
U-Boot source. I've tested it on both the
Freescale boards:
MPC8349E-MDS-PB:
- MPC8349E processor (v1.x silicon)
- DDR1 SDRAM
- Micron Q-Flash
MPC8349EA-MDS-PB:
- MPC8349EA processor (
Hi all,
Once I'd written the email on this subject to the U-Boot
list, I figured it was starting to sound like a Freescale
support request, so I submitted one too. Here's their
response:
"Actually, snooping occurs inside MPC8349 device.
Besides e300 core, other possible masters are:
PCI1,
Hi all,
I'm just reading through the MPC8349EA-MDS-PB board
start-up code to understand it, eg. the initial SRAM
in data-cache trick.
In the BAT setups in include/configs/MPC8349EMDS.h,
some of the CFG_IBAT settings include the bit setting
BATL_MEMCOHERENCE, indicating that those BAT entries
are
Hi Liberty,
> I believe I will prefare crippling the CFI over Crippling the flash
> eeprom as I believe it will be easier on our production team... But I
> will have to play with it some more...
If I understand your earlier posts, you are using a CFI
flash, and then 'hiding' half or more of that
>> So, as the designer, its up to you. But keep in mind that
>> you want to make it hard for a customer to screw up, so
>> a separate EEPROM could be a good choice.
>
> In many cases it ain't. I've seen many board which lost their EEPROM
> contents, typically because of edge condition problems
Jon Smirl wrote:
> I'm new to working on low level code like u-boot. Something I don't
> understand is why things like the Ethernet address are stored in
> eeprom instead of flash. Is this something to do with how boards are
> manufactured? From a high level perspective it doesn't seem to matter
>
onyxtape wrote:
> Hi there,
>
> So what are the steps to get u-boot to boot the hello_world example? I'm
> evaluating the PowerPC 440-based AMCC Yosemite board.
Here are the notes I wrote for the Yosemite board,
they include how to build the standard standalone
example. Perhaps that will help you
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