Tor,
at last I could solve my strange behaviour.
Actually the PHY definitely uses both 2 bit definitions of Rx and Tx Skew at
RGMII Skew Control Reg 0x1c - which are set up by eeprom or strapping.
Due to noise or strapping resistor mismatch these setting are not always
like
I want them to be.
Hi,
On 4/17/2008, Andre Schwarz [EMAIL PROTECTED] wrote:
Tor,
after all my VSC8601 is up and running on MPC8343 :-)
I'm sorry to say that I don't find this patch ok after going through the
manuals :
Register 0x17 is a very coarse setting. If the capabilities of the PHY
should be taken into
Tor,
after all my VSC8601 is up and running on MPC8343 :-)
I'm sorry to say that I don't find this patch ok after going through the
manuals :
Register 0x17 is a very coarse setting. If the capabilities of the PHY
should be taken into account and be configurable we should use the skew
Kim Phillips schrieb:
On Tue, 01 Apr 2008 15:33:10 +0200
Andre Schwarz [EMAIL PROTECTED] wrote:
I would expect something like
if ( priv-flags TSEC_REDUCED )
regs-ecntrl |= ECNTRL_RPM;
yeah, that register should be r/o..
you're right.
The register actually _is_
Kim,
would it help if we donate one or two boards to the custodians ?
Or do you have no time at all for specific testing ?
After bring-up + validation I could offer 1-2 MPC8343B based boards with
2x VSC8601.
The system also has a miniPCI Slot, USB-A and 512MB DDR-II Micron memory.
Please
Tor,
after investigating the tsec code I'm wondering how your PHY works in
RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into
account during tsec_init.
/* Init ECNTRL */
regs-ecntrl = ECNTRL_INIT_SETTINGS;
This will clear bit 27 which indicates RGMII
On Tue, Apr 1, 2008 at 8:33 AM, Andre Schwarz
[EMAIL PROTECTED] wrote:
Tor,
after investigating the tsec code I'm wondering how your PHY works in
RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into
account during tsec_init.
/* Init ECNTRL */
On Tue, Apr 1, 2008 at 9:08 AM, Andre Schwarz
[EMAIL PROTECTED] wrote:
Tor,
after investigating the tsec code I'm wondering how your PHY works in
RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into
account during tsec_init.
/* Init ECNTRL */
Andy Fleming schrieb:
On Tue, Apr 1, 2008 at 8:33 AM, Andre Schwarz
[EMAIL PROTECTED] wrote:
Tor,
after investigating the tsec code I'm wondering how your PHY works in
RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into
account during tsec_init.
/* Init
Andy Fleming schrieb:
On Tue, Apr 1, 2008 at 9:08 AM, Andre Schwarz
[EMAIL PROTECTED] wrote:
Tor,
after investigating the tsec code I'm wondering how your PHY works in
RGMII mode ...
I think that there are some things missing, e.g. taking RGMII into
account during tsec_init.
/* Init
On Tue, 01 Apr 2008 15:33:10 +0200
Andre Schwarz [EMAIL PROTECTED] wrote:
I would expect something like
if ( priv-flags TSEC_REDUCED )
regs-ecntrl |= ECNTRL_RPM;
yeah, that register should be r/o..
@Kim : Did you ever run a MPC834x with a RGMII PHY ? Is it known
Tor Krill wrote:
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing
compensation.
Signed-off-by: Tor Krill [EMAIL PROTECTED]
Acked-by: Ben Warren [EMAIL PROTECTED]
---
drivers/net/tsec.c | 30 ++
Tor Krill wrote:
Ben regarding your call for network related patches. Im not sure if i
should have sent this one to you? Got no reactions on it.
/Tor
No problem. If either Kim Phillips or Andy Fleming blesses it, I'll
pull it in today.
regards,
Ben
On Mon, 31 Mar 2008 10:01:34 -0400
Ben Warren [EMAIL PROTECTED] wrote:
Tor Krill wrote:
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing
compensation.
Signed-off-by: Tor Krill [EMAIL PROTECTED]
Acked-by: Ben Warren [EMAIL
Ben regarding your call for network related patches. Im not sure if i
should have sent this one to you? Got no reactions on it.
/Tor
On 3/28/2008, Tor Krill [EMAIL PROTECTED] wrote:
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing
compensation.
Signed-off-by: Tor Krill [EMAIL PROTECTED]
---
drivers/net/tsec.c | 30 ++
drivers/net/tsec.h |5 +
2 files changed, 35 insertions(+), 0
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