Ian is correct regarding B210 and B200mini not supporting an external LO.
It is worth noting that we do support external LO mode for the N310 (the
AD9371 has the same divide-by-2 as the AD9361) and optionally for the N230.
In any event, the ADI Engineer Zone post in my original message
Robin,
that ADI support thread is not applicable to B2x0, it’s for AD9361 external LO
mode which isn’t used by Ettus products.
In internal LO mode there is always a phase ambiguity in the RF synthesizers
that requires higher level S/W to calibrate and correct for.
The baseband synthesizer can
Marcus is correct and the schematics do in fact provide the answer.
Please refer to p.1 of the B210 schematic. It contains an ADF4002 analog
PLL.
The B200mini clocking circuitry is on p. 4 of the schematic. The PLL is
digital and implemented inside the FPGA.
There is a divide-by-2 for the
On 06/25/2018 11:57 PM, Dan CaJacob wrote:
Without looking at the schematic, I'd guess that the difference is in
the implementation of the PLLs for tracking.
On Mon, Jun 25, 2018 at 11:21 AM Chintan Patel via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi Marcus,
Two
Just speculating, but I wonder if what you're seeing is a result of
quantization error...
On Mon, Jun 25, 2018 at 11:55 PM Farhad via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Thanks Ian for your answer; but my main question still remains unanswered
> which is why with different wire
Without looking at the schematic, I'd guess that the difference is in the
implementation of the PLLs for tracking.
On Mon, Jun 25, 2018 at 11:21 AM Chintan Patel via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi Marcus,
>
> Two follow-up questions related to B205/B210 synchronization.
>
>
Thanks Ian for your answer; but my main question still remains unanswered which
is why with different wire format sc8 and sc16 the spectrum is different? How
may I interpret this?
Thanks,
> On Jun 25, 2018, at 9:44 PM, Ian Buckley wrote:
>
> On a USRP2 thats a harmonic of the on-board
On a USRP2 thats a harmonic of the on-board 100MHz clock. One excellent way to
deduce when you are dealing with a spur thats LO related is to use offset
tuning to move the LO relative to the center of your band of interest.
See: https://files.ettus.com/manual/structuhd_1_1tune__request__t.html
Can you try recv_frame_size=1024 as part of the device args?
-- M
On 06/13/2018 03:23 PM, Ayaz Mahmud wrote:
> Hi,
>
>
>
> Yes, Its B210 and works with other example like tx_ofdm.
>
>
>
> Ayaz
>
>
>
>
> *From:*
On 06/21/2018 10:57 AM, Ayaz Mahmud via USRP-users wrote:
> Hello All,
>
>
>
> I am trying to build OFDM_MIMO (2 x 2). I have used the blocks from OFDM
> example folders and joined tx & rx together and transmitting/receiving
> over USRP B210.
>
>
>
> My aim is to get a channel state
Hi Nives,
The warning can be ignored. It is a known issue that I believe was
recently fixed.
Regards,
Michael
On Mon, Jun 18, 2018 at 2:10 AM, Nives Novković
wrote:
> Hi everyone,
>
> Thank you for all your help. I followed EJ's advice on adding the 2nd FIFO
> block, also Michael's for
Dear Fernaz,
you can't cheat 10Gig bandwidth! If you time-share any medium, then
it's bandwidth must be shared. Since ethernet is de facto a timesharing
thing, anyway, no, this won't work:
Since you need to push through all the data through a single 10GigE
connection, your 10 gigabits per second
Dear all,
I want to connect multiple USRP X310 to one host PC and control them all
from that Pc, using one 10Gigabit Ethernet switch. My question is that if
it is possible to stream from each USRP in a different time slot using the
full bandwidth and 200MS/s in a setup similar to the picture
What is the behavior of the lights on the front panel?
On Mon, Jun 25, 2018, 12:31 AM Pol Henarejos via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Dear Derek,
>
> I tried the link that you gave but no luck.
> 1) I disabled the use of timestamp and, dissecting the packets with
> wireshark,
Hi Marcus,
Two follow-up questions related to B205/B210 synchronization.
1. What is the fundamental reason why B210 supports phase coherent sync
across multiple devices and B205 does not. The reference manuals on the
AD9364/AD9361 does not point to any clues, and neither does the schematic.
2.
Hi everyone,
I am still having problems with the "late command" errors.
Is it possible to increase the number of commands an X310 can buffer? I
need 5 commands to set a new frequency and start the stream, which means
that I can only plan 3 commands ahead. This seems be be insufficient as
some
Hello,
we are currently working with a USRP X310 with a Twin RX daughter board. We are
interested on more information about the CHDR protocol.
The documentation on https://files.ettus.com/manual/page_rtp.html seems to be
not enough. The concrete questions are as follows:
- What does the
uhd_usrp_probe seems to come back fine. It sees the 205. I'm seeing it on
another separate Pi with a different LTE adapter too so I think it rules
out the instance of both I have being the culprit.
I'll have some time tomorrow night to do some more debugging. I'll take a
look at the lsusb
Hello,
has anyone been successful reflashing the x3xx using xc3sprog or any other
command-line tool that is at least two orders of magnitude smaller than
Vivado Lab? :) When I'm trying to program the current (2017.4-generated)
images using xc3sprog, the usrp probe complains about unknown hardware
Can also try exactly the same test, but with a standard PC / laptop and the
same OS, to isolate the rPi/host hardware parameter
On Mon, Jun 25, 2018 at 7:30 AM Ian Buckley via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Perhaps try 'sudo lsusb -v' with and without the LTE modem plugged in
Dear Derek,
I tried the link that you gave but no luck.
1) I disabled the use of timestamp and, dissecting the packets with
wireshark, I cross-checked that the use_timestamp bit is 0.
2) I added the set_rx_streamer and issue_cmd to my flograph but nothing
happens. I am not sure if both
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