On 07/22/2018 10:04 PM, Yeats Luo via USRP-users wrote:
Ubuntu 16.04.04 TLS/Kernel 4.8.17 Lowlatency
Thank you for the tips.
The USB3 problem was solved by flashing the image into default
settings. (reset)
uhd_image_loader --args="type=b200,addr=192.168.100.2,reset"
However, I bumped into
Ubuntu 16.04.04 TLS/Kernel 4.8.17 Lowlatency
Thank you for the tips.
The USB3 problem was solved by flashing the image into default settings. (reset)
uhd_image_loader --args="type=b200,addr=192.168.100.2,reset"
However, I bumped into new problems.
All my settings worked, EPC online, eNB
Hi Dario,
On Sun, Jul 22, 2018 at 1:57 PM Dario Pennisi wrote:
> Hi Brian,
> I think I understand where you're going but I still think you may have
> more trouble than solutions. One for all is bandwidth. 10g Ethernet is just
> able to support one channel at 200 msps. Unless you're downsampling
Hi ishai,
Although a block with different number of inputs and outputs is feasible in
rfnoc, uhd won't work well with it so I would suggest you define it with the
same number of inputs and outputs and then just connect the unused into to a
null source/sink
For a complete example on how to
On 07/22/2018 01:07 PM, Kirthana Rao wrote:
No the usrps are connected to two different hosts.When I entered the
other usrp's address in the uhd:usrp source block in gnuradio,I got an
error saying that the address was not found.
Well, that makes sense, because said USRP is on another computer.
Hi Brian,
I think I understand where you're going but I still think you may have more
trouble than solutions. One for all is bandwidth. 10g Ethernet is just able to
support one channel at 200 msps. Unless you're downsampling somewhere you won't
be able to pass all that bandwidth across the
Hey Dario,
On Sun, Jul 22, 2018 at 11:20 AM Dario Pennisi wrote:
> Hi Brian,
> It really depends on what you want to achieve. If you just want to perform
> validation then you can use simulation which is already set up and
> straightforward if you follow the examples. Also it would allow you to
Hi Brian,
It really depends on what you want to achieve. If you just want to perform
validation then you can use simulation which is already set up and
straightforward if you follow the examples. Also it would allow you to verify
even hls code and make sure it does what you expect in a cycle
Hey Dario,
On Sun, Jul 22, 2018 at 3:55 AM Dario Pennisi wrote:
> Hi Brian,
> Don't think what you want to do is feasible. While the streaming data part
> is easy as it's basically just an oot block, emulating register writes is
> not possible because they go through APIs that send commands
Hi,
list,
I want the usrp e310 run only one tx path and one rx path (to save some fpag
resource)
how can I modify the host code and fpga code ?
I use the uhd version: ca09fd2bea0128c18eac4b0ff8a9b30fccdf7698
fpga version: 63e630a13fde1735b98eab1f401f60f0b354cafb
Thanks.
Hi Brian,
Don't think what you want to do is feasible. While the streaming data part is
easy as it's basically just an oot block, emulating register writes is not
possible because they go through APIs that send commands over the network. The
only reasonable option I see to do what you want is
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