Hi Brian, It really depends on what you want to achieve. If you just want to perform validation then you can use simulation which is already set up and straightforward if you follow the examples. Also it would allow you to verify even hls code and make sure it does what you expect in a cycle accurate way. If you follow your idea you will get only a model which may not be so accurate because there is a lot going on in the hw that is difficult to model such as the interaction between internal fifos. Also even assuming your model of the sdr is accurate you'll still have to ensure that model of your IP is also accurate...
In my experience we just needed to prove algorithms with SW oot blocks that were simulating the behaviour by using integer math and then we rewrote the core in RTL and simulated it... This workflow proved to be the most reliable and straightforward... I may be wrong or misunderstanding your end goal but these are my 50 cents... Dario Pennisi On Sun, Jul 22, 2018 at 5:13 PM +0200, "Brian Padalino" <bpadal...@gmail.com<mailto:bpadal...@gmail.com>> wrote: Hey Dario, On Sun, Jul 22, 2018 at 3:55 AM Dario Pennisi <da...@iptronix.com<mailto:da...@iptronix.com>> wrote: Hi Brian, Don't think what you want to do is feasible. While the streaming data part is easy as it's basically just an oot block, emulating register writes is not possible because they go through APIs that send commands over the network. The only reasonable option I see to do what you want is to create a complete model of a uhd device that basically talks through sockets but seems a big task to undergo... This is actually what I was thinking about doing, but I don't want to re-create the CHDR/UDP portion of everything going on under the hood and I want to produce this model out-of-tree. I want to create a standalone executable which will listen on a UDP socket and interact with my normal UHD application through UDP. I realize this may be a large task, but it also sounds like an extremely useful one. Do you agree? Brian
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