I run into the same issue while reading from the file. Even if I put in a
higher sample rate while inputting to the File Sink (so I get the
frequencies that I want), the device hits underflows while reading from the
File Source because it can't sustain that sample rate. Are there any other
ways to
screamingly efficient, so it
>>> may be that they just aren't keeping up, although at 4Msps, you wouldn't
>>> expect them to be too stressed.
>>>
>>>
>>>
>>>
>>>
>>>
>>> On 2017-10-24 15:12, Oliver Wayne via USRP
Apologies for not forwarding to the full list. I'm attempting to run the
attached flowgraph with the following hardware, but getting underflows.
I have 8 GB of RAM, so don't think that's a problem. Running lspci | grep
-i usb, I get the following output
00:1a.0 USB controller: Intel Corporation
How would I then include negative numbers on the Verilog side to kill the
offset? I'm a bit more comfortable with fpga design than with SDR, so for
testing purposes I'd prefer to do it that way.
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>
> This is the domain of software systems like Gnu Radio, or if you're doing
> this in FPGA-land (not really recommended for B2xx, since the FPGAs aren't
> big enough), coding in Verilog with ISE, using whatever DSP libraries you
> can integrate into the FPGA.
>
>
>
>
>
&
ne_frequency).
>
> If there's still a LO leakage on the output, you can manually fiddle with
> the IQ corrections inside the AD9361.
>
> Best regards,
>
> Marcus
>
> On 12.10.2017 02:23, Oliver Wayne via USRP-users wrote:
>
> Hello,
>
> I've implemented a DDS sign
Hello,
I've implemented a DDS signal on the USRP device. In radio_legacy.v, I
input get_tx_I and get_tx_Q as my I and Q channels.
always @(posedge radio_clk) begin tx[31:16] <= (run_tx) ?
get_tx_I[31:16] : tx_idle[31:16]; // I channel tx[15:0] <= (run_tx) ?
get_tx_Q[31:16] : tx_idle[15:0]; //
