Re: [USRP-users] Removing DC offset on USRP B200

2017-10-21 Thread Marcus Müller via USRP-users
Hi Oliver, yep, GNU Radio is just discrete signals, just like in an FPGA – but with software buffers between software functions :) That especially means that this is all complex baseband – so, to represent 20 MHz (= 0.5 MHz · 40), i.e. -10 to +10 MHz, you just need a sample rate of 20 MS/s. 6MS/

Re: [USRP-users] Removing DC offset on USRP B200

2017-10-19 Thread Oliver Wayne via USRP-users
Hi Marcus, On your advice I went through the first few chapters of the gnuradio tutorial, and started experimenting again with my device. as best I understand (please correct me if this is wrong), my signal sources must be less than half the sample rate for the signals to be well-resolved. The tro

Re: [USRP-users] Removing DC offset on USRP B200

2017-10-17 Thread Marcus Müller via USRP-users
Hi Oliver, even just considering the time it takes to synthesize a single image for the B200's FPGA, not counting time needed to learn where to put your Verilog: Avoid doing things in the FPGA as far as possible. The 20 minutes it costs to go through the first two or three chapters of the GNU Radi

Re: [USRP-users] Removing DC offset on USRP B200

2017-10-16 Thread Oliver Wayne via USRP-users
How would I then include negative numbers on the Verilog side to kill the offset? I'm a bit more comfortable with fpga design than with SDR, so for testing purposes I'd prefer to do it that way. ___ USRP-users mailing list USRP-users@lists.ettus.com http:

Re: [USRP-users] Removing DC offset on USRP B200

2017-10-16 Thread Marcus D. Leech via USRP-users
Never use a throttle in a flow that includes actual hardware. You're probably connecting via USB-2.0, which wont' support two channels at 5Msps. The tuned center frequency has nothing to do with the sample rate. The sample rate determines the bandwidth centered around your center frequency th

Re: [USRP-users] Removing DC offset on USRP B200

2017-10-16 Thread Oliver Wayne via USRP-users
So as far as using Verilog goes, how would I remove the offset (as described in the original post)? I don't think I can use gnuradio because the sample rate maxes out at around 5 Msps (if I try to push past this, I get "The total sum of rates exceeds the maximum capacity of the connection), so for

Re: [USRP-users] Removing DC offset on USRP B200

2017-10-16 Thread Marcus D. Leech via USRP-users
A quick note from the other Marcus. The UHD library is NOT a DSP library. If you need to "do things to my signal", you'll need to do that outside of UHD itself, which is really just a driver API for the hardware. This is the domain of software systems like Gnu Radio, or if you're doing this in

Re: [USRP-users] Removing DC offset on USRP B200

2017-10-16 Thread Oliver Wayne via USRP-users
Hi Marcus, How do i produce a sum of multiple tones using the uhd libraries? tx_waveforms.cpp lets me set a center frequency with uhd::tune_request_t tune_request(LO_freq), but what I want is to see an output A1*sin(f1*t + phi1) + A2 * sin(f2*t + phi2) + ... Along similar lines, how do I change t

Re: [USRP-users] Removing DC offset on USRP B200

2017-10-14 Thread Marcus Müller via USRP-users
Hi Oliver, haven't quite thought through an understanding of what you're currently doing, but: Since the FPGA image already comes with a convenient-to-use DUC – why not just produce a constant, and tune digitally to a non-zero frequency? That way, the CORDICs inside the duc_chain will simply gene

[USRP-users] Removing DC offset on USRP B200

2017-10-11 Thread Oliver Wayne via USRP-users
Hello, I've implemented a DDS signal on the USRP device. In radio_legacy.v, I input get_tx_I and get_tx_Q as my I and Q channels. always @(posedge radio_clk) begin tx[31:16] <= (run_tx) ? get_tx_I[31:16] : tx_idle[31:16]; // I channel tx[15:0] <= (run_tx) ? get_tx_Q[31:16] : tx_idle[15:0]; //