Hi Dario,
The generation of the IP should be the same in tree and out of tree, so it
is strange that the netlist simulation file isn't generated for you. I'd
like to try it to see if I get that behavior, but I'm currently traveling
so it might be a while before I am able to.
I wanted to let you k
i did some step forward. it looks like in the build directory there's a
file called complex_multiplier_sim_netlist.v that allows simulation however
when calling the simulation from an OOT directory the IP is rebuilt under
that directory and that file is not created.
unfortunately the sim/complex_mu
Hi Jonathon,
thanks for your reply. unfortunately the issue seems to be with
complex_multiplier ip generated by vivado. if i bypass that (my
instantiating wires that connect input to output instead of the IP)
everything works. i noticed the IP generates a vhdl file and the aggregate
association er
Hi Dario,
Unfortunately, Vivado's xsim simulator sometimes crashes when it runs into
syntax and elaboration errors. Make sure you don't have issues like signals
with multiple drivers, undriven signals, missing reset logic, typos, etc.
Note that these issues may be in code that is/seems unrelated t
Hi,
i'm trying to simulate a block where i'm using cmul. in order to have that
compiled in i am including the following in my Makefile under rfnoc/fpga in
my OOT directory:
include $(BASE_DIR)/../lib/ip/Makefile.inc
SIM_SRCS = $(abspath rfnoc_block_demod_tb.sv) \
$(LIB_IP_COMPLEX_MULTIPLIER_OUTS)
