I think I can explain why K6s and K6-2s could get slower after adding RAM:
it's because the L2 cache they use is direct-mapped. I won't go into a full
discussion of the various caching methods, but I'll need to explain some
basics. Note that I'm not an expert on this caching stuff so I may be in
error on some things, but generally this explanation should be right.
Direct mapping is simple to understand, but not easy to explain.
Essentially, a given cache line can only cache data from a certain block of
main memory. So, for example, let's say you have a K6-2 with 128MB of main
RAM and 512K of 64-bit-per-line (I'm not sure if that's how it's done for
not, as that's one of the things I'm rusty on, but I'll use this possibly
unrealistic example as a basis for explanation) L2 cache. That means that
each line of cache stores 8 bytes (8 bits per byte, 64/8=8). 512K is equal
to 524,288 bytes, or 65,536 cache lines in this example. Thus, the main
memory would be effectively broken up into 65,536 segments, and each of
those segments has one specific cache line it can use. Now, 128MB is
134,217,728 bytes. That divided by 65,536 gives 2048, or 2 kilobytes,
meaning that, in this case, each 2-kilobyte chunk of main memory has 8
bytes of cache associated with it. If the main memory size were increased
to 256MB, each 16K of main memory would have 8 bytes of cache. So, as you
can see, direct-cache mapping is not very effective with large amounts of
RAM, because it's a very inelegant method of caching; if you have a
gigabyte of main memory, and only use the first 128MB, 7/8ths of your cache
will be wasted caching nothing because its associated memory blocks are
unused.
Now, there's a more intelligent method of caching called associative
caching. Fully associative caching, which is rather rare, means that any
data anywhere in main memory can be stored anywhere in the cache. There's
also set associative caching, which I'm more unclear on. The Pentium !!!
"Coppermine" processor uses 8-way set associative caching with its L2
cache. At this point, I'm going to cheat and copy a URL to explain things:
http://www.instantweb.com/D/dictionary/foldoc.cgi?query=set+associative+cache
Basically, fully-associative cache is difficult to implement, and as that
entry explains, 2-, 4-, 8-, and 16-way set associativity (in order of
increasing performance but also increasing complexity of implementation)
allow for almost the same performance as full associativity, but are not
that much harder to implement than a direct mapping method.
Anyway, this should all help explain why processors with on-cartridge or
on-chip caches are not likely to suffer performance reductions when main
memory is added, whereas processors with direct-mapped cache on the
motherboard are.

Evan

Broc Olson writes:

> 
> Agreed.  My landlord is on a p3 450.  When she had 32 megs she was hitting
> about 30 hrs a WU.  She added another 64 megs and is now doing a WU in about
> 15 hrs. Given what I've seen....p2's and p 3's benefit from the additions of
> ram while the AMD K6/2's loose.  I don't know about the Celerons or the p4's
> 
> Broc Olson < Byark!>
> 
> ----- Original Message -----
> From: Jeff Gerst <[EMAIL PROTECTED]>
> To: <[EMAIL PROTECTED]>
> Sent: Tuesday, September 25, 2001 10:13 PM
> Subject: Re: RAM, etc.
> 
> 
> >
> > well that may be about right, it was frustrating discovering the time went
> down
> > as i removed ram from the computer, i started with 128, added another 128
> times
> > went up so i subtracted down to 64 and it was even better than when it had
> 128,
> > i do not remember the relative times now, but what i noticed was a K6/2
> 400 was
> > maybe 18 hours on the old version and a PII 400 was 10-11 hours, both
> running
> > same bus speed and more ram in the PII etc. that was frustrating since
> then i
> > donated the PII to my mom and built others to take its place...
> 
> 
> 
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