Data should not be shifted upon transition from CAPTURE-* to SHIFT-*. TDI is shifted into a register only if the state at the rising egde of TCK is already SHIFT-*.
I stumbled upon this while implementing a EJTAG decoder for MIPS and have tested it with some debugging hardware. Relevant stackoverflow post: https://electronics.stackexchange.com/questions/342258/is-tdi-shifted-on-move-from-shift-ir-to-exit2-ir-in-jtag v2 fixes tabs/spaces mixup Apologies if someone gets this message for the second time but I think sourceforge was down when I sent it before, and I can't find the message in the archives. --- decoders/jtag/pd.py | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/decoders/jtag/pd.py b/decoders/jtag/pd.py index 7f784eb..08d0ea8 100644 --- a/decoders/jtag/pd.py +++ b/decoders/jtag/pd.py @@ -180,6 +180,12 @@ def handle_rising_tck_edge(self, pins): # Upon SHIFT-IR/SHIFT-DR collect the current TDI/TDO values. if self.state.startswith('SHIFT-'): + # TDI shouldn't be shifted in on transition + # from CAPTURE-* to SHIFT-* + if not self.first_bit: + self.bits_tdi.insert(0, tdi) + self.bits_tdo.insert(0, tdo) + if self.first_bit: self.ss_bitstring = self.samplenum self.first_bit = False @@ -190,9 +196,6 @@ def handle_rising_tck_edge(self, pins): self.bits_samplenums_tdi[0][1] = self.samplenum self.bits_samplenums_tdo[0][1] = self.samplenum - self.bits_tdi.insert(0, tdi) - self.bits_tdo.insert(0, tdo) - # Use self.samplenum as SS of the current bit. self.bits_samplenums_tdi.insert(0, [self.samplenum, -1]) self.bits_samplenums_tdo.insert(0, [self.samplenum, -1]) @@ -203,6 +206,8 @@ def handle_rising_tck_edge(self, pins): self.es_bitstring = self.samplenum + # Shift in last TDI bit + self.bits_tdi.insert(0, tdi) t = self.state[-2:] + ' TDI' b = ''.join(map(str, self.bits_tdi)) h = ' (0x%x' % int('0b' + b, 2) + ')' @@ -210,10 +215,11 @@ def handle_rising_tck_edge(self, pins): self.putx_bs([18, [s]]) self.bits_samplenums_tdi[0][1] = self.samplenum # ES of last bit. self.putp_bs([t, [b, self.bits_samplenums_tdi]]) - self.putx([16, [str(self.bits_tdi[0])]]) # Last bit. + self.putx([16, [str(tdi)]]) # Last bit. self.bits_tdi = [] self.bits_samplenums_tdi = [] + self.bits_tdo.insert(0, tdo) t = self.state[-2:] + ' TDO' b = ''.join(map(str, self.bits_tdo)) h = ' (0x%x' % int('0b' + b, 2) + ')' @@ -221,7 +227,7 @@ def handle_rising_tck_edge(self, pins): self.putx_bs([19, [s]]) self.bits_samplenums_tdo[0][1] = self.samplenum # ES of last bit. self.putp_bs([t, [b, self.bits_samplenums_tdo]]) - self.putx([17, [str(self.bits_tdo[0])]]) # Last bit. + self.putx([17, [str(tdo)]]) # Last bit. self.bits_tdo = [] self.bits_samplenums_tdo = [] -- 2.16.1 ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ sigrok-devel mailing list sigrok-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/sigrok-devel
