On 08/08/2011 01:31 PM, Robin Holt wrote: > OK. Dug a bit more. The p1010 built-in clocksource seems to be the > periphereal clock frequency which is system bus frequency divided > by 2. The clock source can not be changed, but the clock divider can
On arm the clock source is selected by bit 13 of CTRL: > This bit selects the clock source to the CAN protocol interface (CPI) > to be either the peripheral clock (driven by the PLL) or the crystal > oscillator clock. The selected clock is the one fed to the prescaler > to generate the SCLK (SCLK). In order to guarantee reliable > operation, this bit must only be changed while the module is in > disable mode. See Section 24.4.8.4, “Protocol Timing,” for more > information. > 0 The CAN engine clock source is the oscillator clock (24.576 MHz) > 1 The CAN engine clock source is the bus clock (66.5 MHz) cheers, Marc -- Pengutronix e.K. | Marc Kleine-Budde | Industrial Linux Solutions | Phone: +49-231-2826-924 | Vertretung West/Dortmund | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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