As the frequency increases the control signal I.E. address inputs could couple 
to the output showing up as additional noise. ??? gfz

KY1K <[EMAIL PROTECTED]> wrote:  Oh my gosh NO!!!!!!!!! I do not suggest to 
ignore or set aside Bob's 
real life measurements taken on actual hardware-quite the contrary in 
fact! I find it very interesting, although I am at a loss as to WHY 
the real life hardwares degradation manifests itself as a worsening 
MDS and the Spice losses show up as decreasing amplitudes.

I am wondering if the magnitude of my conversion gain degradation 
tracks closely with Bob's degradation MDS numbers?

I should also say I did a full model with 4 imperfect switches (4 
ohms R(on), 10 Meg ohms R(off), 50 ohm source impedance and a fixed 4 
nS overlap between adjacent switches) and measured the output voltage 
only. I did not add switch input or output C, which could be significant?

I did a large signal analysis, so noise is ignored. My simulations 
address raw voltage due to switch conduction overlap. Bob's readings 
are the result of ALL factors, not just one.

Dan Tayloe mentioned increasing noise as the switching frequency is 
increased, which the switch resistance contributes to. Perhaps a 
small signal analysis with noise added would be more revealing?

I'm open to suggestions.

Regards,

Art



At 01:32 AM 3/26/2006, you wrote:
>Agreed.
>
>Also, if there were so much loss as previously suggested, the inevitable
>variation in relative phase error between switches would have to be so
>bad that the unwanted sideband performance would be very poor indeed -
>even at quite a low frequency, and this is not seen as being anything
>like that bad.
>
>As Bob says, you simply cannot ignore what is actually observed.
>
>Bernard
>G4HJW
>
>
>Robert McGwier wrote:
> > Art:
> >
> > Let me reiterate what it is we OBSERVE and can measure with the QSD in
> > the SDR-1000.
> >
> > We do /***NOT***/ see conversion loss increase as the frequency gets
> > higher.  We see a nearly flat 1 dB insertion loss (to withing reason but
> > so close,  just fogettaboutit).
> >
> > What we do see is a steady rise it the noise floor.  If you put in a -70
> > dBm signal at 14 MHz,  you got approximately the same converted voltage
> > as you do at 54 MHz with -70 dBm signal.    The MDS gets worse,  the
> > loss does NOT.
> >
> > Bob
> > N4HY
> >
> >
> >
> >
> > KY1K wrote:
> >
> >> Below is a copy of a message I posted to the softrock-40 group. Some
> >> who monitor here might be interested as well.
> >>
> >> Message follows:
> >>
> >>
> >> -------------------------------------------------------------
> >>
> >> Greetings all,
> >>
> >> I simulated (Spice) the sluggish turn off times of the FST3125 cmos
> >> switch. Due to the slower turn off time, there is overlap in the
> >> conduction of adjacent switches...meaning that 2 switches are
> >> momentarily conducting at the same time. I found the conversion gain
> >> drops very quickly once the 25 percent duty cycle is exceeded and
> >> that this condition should be avoided for good results.
> >>
> >> I had hoped to release the data in a more polished form, but here is
> >> the summary of the losses for each HF band.
> >>
> >> These are relative conversion gains and were obtained by applying 4
> >> nS overalp on each analog switch. Note that ~4 ns overlap is the
> >> actual overlap that exists in the FST3125 and similar technology cmos
> >> analog switches we use in softrock's/QSD's today.
> >>
> >> On 50* Mhz, the conversion gain is down 20.3 db (relative to a
> >> perfect 25-25-25-25 duty cycle).
> >>
> >> On 28* Mhz, the conversion gain is down 14.2 db (relative to a
> >> perfect 25-25-25-25 duty cycle).
> >>
> >> On 14* Mhz, the conversion gain is down 8.7 db (relative to a perfect
> >> 25-25-25-25 duty cycle).
> >>
> >> On 7* Mhz, the conversion gain is down 7.6 db (relative to a perfect
> >> 25-25-25-25 duty cycle).
> >>
> >> On 3.5* Mhz, the conversion gain is down 4.6 db (relative to a
> >> perfect 25-25-25-25 duty cycle).
> >>
> >> *4 ohm R(on), a 10 Megohm R(off), with 4 nS overlap, .01 uF 
> integrating caps.
> >>
> >> I also have the Spice model(s) used, and a graph showing relative
> >> conversion gain vs the switch duty cycle for ranges between 5 and 45
> >> percent. The graph is a crude gif file, but is legible. Email me OFF
> >> LIST if you would like any of the data.
> >>
> >> Regards,
> >>
> >> Art
> >>
> >>
> >>
> >>
> >>
> >>
> >> Yahoo! Groups Links
> >>
> >>
> >>
> >>
> >>
> >>
> >>
> >>
> >>
> >>
> >
> >
> >
>
>
>
>
>
>
>
>Yahoo! Groups Links
>
>
>
>
>
>
>
>
>
>
>--
>No virus found in this incoming message.
>Checked by AVG Free Edition.
>Version: 7.1.385 / Virus Database: 268.3.1/292 - Release Date: 3/24/2006




    
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