Module Name: src
Committed By: matt
Date: Sat Jan 16 20:56:33 UTC 2010
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: asm.h
src/sys/arch/mips/mips [matt-nb5-mips64]: genassym.cf locore_mips1.S
mips32_subr.S mips3_subr.S mips5900_subr.S mips64_subr.S
mipsX_subr.S mips_machdep.c
Log Message:
Rework the exception code. All the exceptions (except for mips3_5900) are
now padded to 128 bytes each and placed in the right order so they can be
copied with one memcpy. This also allows us to branch to unused space space
since the relative locations will remain the same.
When leaving the exception vectors, k1 will now always contain the address
of CURLWP for that CPU. The rest of the exception code no longer needs (and
is not allowed to) to access CPUVAR(CURLWP).
kill outofworld and just let trap panic, if it can. Allow for sb1_subr.S
or rmixl_subr.S in the future. Fix TLB read/write code.
To generate a diff of this commit:
cvs rdiff -u -r1.40.38.10 -r1.40.38.11 src/sys/arch/mips/include/asm.h
cvs rdiff -u -r1.44.12.8 -r1.44.12.9 src/sys/arch/mips/mips/genassym.cf
cvs rdiff -u -r1.64.26.1.2.3 -r1.64.26.1.2.4 \
src/sys/arch/mips/mips/locore_mips1.S
cvs rdiff -u -r1.3 -r1.3.96.1 src/sys/arch/mips/mips/mips32_subr.S \
src/sys/arch/mips/mips/mips3_subr.S src/sys/arch/mips/mips/mips64_subr.S
cvs rdiff -u -r1.4 -r1.4.96.1 src/sys/arch/mips/mips/mips5900_subr.S
cvs rdiff -u -r1.26.36.1.2.17 -r1.26.36.1.2.18 \
src/sys/arch/mips/mips/mipsX_subr.S
cvs rdiff -u -r1.205.4.1.2.1.2.25 -r1.205.4.1.2.1.2.26 \
src/sys/arch/mips/mips/mips_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.40.38.10 src/sys/arch/mips/include/asm.h:1.40.38.11
--- src/sys/arch/mips/include/asm.h:1.40.38.10 Fri Jan 15 06:46:58 2010
+++ src/sys/arch/mips/include/asm.h Sat Jan 16 20:56:33 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: asm.h,v 1.40.38.10 2010/01/15 06:46:58 matt Exp $ */
+/* $NetBSD: asm.h,v 1.40.38.11 2010/01/16 20:56:33 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -240,11 +240,13 @@
#ifdef __STDC__
#define VECTOR_END(x) \
EXPORT(x ## _end); \
- END(x)
+ END(x); \
+ .org _C_LABEL(x) + 0x80
#else
#define VECTOR_END(x) \
EXPORT(x/**/_end); \
- END(x)
+ END(x); \
+ .org _C_LABEL(x) + 0x80
#endif
/*
Index: src/sys/arch/mips/mips/genassym.cf
diff -u src/sys/arch/mips/mips/genassym.cf:1.44.12.8 src/sys/arch/mips/mips/genassym.cf:1.44.12.9
--- src/sys/arch/mips/mips/genassym.cf:1.44.12.8 Fri Jan 15 06:46:59 2010
+++ src/sys/arch/mips/mips/genassym.cf Sat Jan 16 20:56:33 2010
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.44.12.8 2010/01/15 06:46:59 matt Exp $
+# $NetBSD: genassym.cf,v 1.44.12.9 2010/01/16 20:56:33 matt Exp $
#
# Copyright (c) 1992, 1993
# The Regents of the University of California. All rights reserved.
@@ -318,3 +318,8 @@
define CPU_INFO_CURLWP offsetof(struct cpu_info, ci_curlwp)
define CPU_INFO_FPCURLWP offsetof(struct cpu_info, ci_fpcurlwp)
define CPU_INFO_PMAP_SEGBASE offsetof(struct cpu_info, ci_pmap_segbase)
+
+define TLBMASK_HI offsetof(struct tlbmask, tlb_hi)
+define TLBMASK_LO0 offsetof(struct tlbmask, tlb_lo0)
+define TLBMASK_LO1 offsetof(struct tlbmask, tlb_lo1)
+define TLBMASK_MASK offsetof(struct tlbmask, tlb_mask)
Index: src/sys/arch/mips/mips/locore_mips1.S
diff -u src/sys/arch/mips/mips/locore_mips1.S:1.64.26.1.2.3 src/sys/arch/mips/mips/locore_mips1.S:1.64.26.1.2.4
--- src/sys/arch/mips/mips/locore_mips1.S:1.64.26.1.2.3 Fri Jan 15 06:46:59 2010
+++ src/sys/arch/mips/mips/locore_mips1.S Sat Jan 16 20:56:33 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips1.S,v 1.64.26.1.2.3 2010/01/15 06:46:59 matt Exp $ */
+/* $NetBSD: locore_mips1.S,v 1.64.26.1.2.4 2010/01/16 20:56:33 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -132,6 +132,7 @@
# we dont have to shift
lw k0, 0(k0) # get the function address
nop
+ lw k1, CPUVAR(CURLWP) # get the current lwp
j k0 # jump to the function
nop
.set at
@@ -921,10 +922,10 @@
tlbr # Read from the TLB
mfc0 t2, MIPS_COP_0_TLB_HI # fetch the hi entry
mfc0 t3, MIPS_COP_0_TLB_LOW # fetch the low entry
- sw zero, 0(a1)
- sw t2, 4(a1)
- sw t3, 8(a1)
- sw zero, 12(a1)
+ sw t2, TLBMASK_HI(a1)
+ sw t3, TLBMASK_LO0(a1)
+ sw zero, TLBMASK_LO1(a1)
+ sw zero, TLBMASK_MASK(a1)
mtc0 t0, MIPS_COP_0_TLB_HI # restore PID
j ra
Index: src/sys/arch/mips/mips/mips32_subr.S
diff -u src/sys/arch/mips/mips/mips32_subr.S:1.3 src/sys/arch/mips/mips/mips32_subr.S:1.3.96.1
--- src/sys/arch/mips/mips/mips32_subr.S:1.3 Sun Dec 11 12:18:09 2005
+++ src/sys/arch/mips/mips/mips32_subr.S Sat Jan 16 20:56:33 2010
@@ -1,9 +1,13 @@
-/* $NetBSD: mips32_subr.S,v 1.3 2005/12/11 12:18:09 christos Exp $ */
+/* $NetBSD: mips32_subr.S,v 1.3.96.1 2010/01/16 20:56:33 matt Exp $ */
#undef MIPS1
#undef MIPS3
/* #undef MIPS32 */
#undef MIPS64
+#undef MIPS64_SB1
+#undef MIPS64_XLP
+#undef MIPS64_XLR
+#undef MIPS64_XLS
#undef MIPS3_5900
Index: src/sys/arch/mips/mips/mips3_subr.S
diff -u src/sys/arch/mips/mips/mips3_subr.S:1.3 src/sys/arch/mips/mips/mips3_subr.S:1.3.96.1
--- src/sys/arch/mips/mips/mips3_subr.S:1.3 Sun Dec 11 12:18:09 2005
+++ src/sys/arch/mips/mips/mips3_subr.S Sat Jan 16 20:56:33 2010
@@ -1,9 +1,13 @@
-/* $NetBSD: mips3_subr.S,v 1.3 2005/12/11 12:18:09 christos Exp $ */
+/* $NetBSD: mips3_subr.S,v 1.3.96.1 2010/01/16 20:56:33 matt Exp $ */
#undef MIPS1
/* #undef MIPS3 */
#undef MIPS32
#undef MIPS64
+#undef MIPS64_SB1
+#undef MIPS64_XLP
+#undef MIPS64_XLR
+#undef MIPS64_XLS
#undef MIPS3_5900
Index: src/sys/arch/mips/mips/mips64_subr.S
diff -u src/sys/arch/mips/mips/mips64_subr.S:1.3 src/sys/arch/mips/mips/mips64_subr.S:1.3.96.1
--- src/sys/arch/mips/mips/mips64_subr.S:1.3 Sun Dec 11 12:18:09 2005
+++ src/sys/arch/mips/mips/mips64_subr.S Sat Jan 16 20:56:33 2010
@@ -1,9 +1,13 @@
-/* $NetBSD: mips64_subr.S,v 1.3 2005/12/11 12:18:09 christos Exp $ */
+/* $NetBSD: mips64_subr.S,v 1.3.96.1 2010/01/16 20:56:33 matt Exp $ */
#undef MIPS1
#undef MIPS3
#undef MIPS32
/* #undef MIPS64 */
+#undef MIPS64_SB1
+#undef MIPS64_XLP
+#undef MIPS64_XLR
+#undef MIPS64_XLS
#undef MIPS3_5900
Index: src/sys/arch/mips/mips/mips5900_subr.S
diff -u src/sys/arch/mips/mips/mips5900_subr.S:1.4 src/sys/arch/mips/mips/mips5900_subr.S:1.4.96.1
--- src/sys/arch/mips/mips/mips5900_subr.S:1.4 Sun Dec 11 12:18:09 2005
+++ src/sys/arch/mips/mips/mips5900_subr.S Sat Jan 16 20:56:33 2010
@@ -1,9 +1,13 @@
-/* $NetBSD: mips5900_subr.S,v 1.4 2005/12/11 12:18:09 christos Exp $ */
+/* $NetBSD: mips5900_subr.S,v 1.4.96.1 2010/01/16 20:56:33 matt Exp $ */
#undef MIPS1
/* #undef MIPS3 */
#undef MIPS32
#undef MIPS64
+#undef MIPS64_SB1
+#undef MIPS64_XLP
+#undef MIPS64_XLR
+#undef MIPS64_XLS
/* #undef MIPS3_5900 */
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.17 src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.18
--- src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.17 Fri Jan 15 06:46:59 2010
+++ src/sys/arch/mips/mips/mipsX_subr.S Sat Jan 16 20:56:33 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.17 2010/01/15 06:46:59 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.18 2010/01/16 20:56:33 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -341,14 +341,14 @@
.set noat
_MFC0 k0, MIPS_COP_0_BAD_VADDR #00: k0=bad address
lui k1, %hi(CPUVAR(PMAP_SEGBASE)) #01: k1=hi of segbase
- bltz k0, 4f #02: k0<0 -> 4f (kernel fault)
+ bltz k0, MIPSX(kernelfault) #02: k0<0 -> 4f (kernel fault)
PTR_SRL k0, (2*PGSHIFT-2-PTR_SCALESHIFT)#03: k0=seg offset (almost)
PTR_L k1, %lo(CPUVAR(PMAP_SEGBASE))(k1)#04: k1=segment tab base
andi k0, k0, (NBPG-(1<<PTR_SCALESHIFT))#05: k0=seg offset (mask 0x3)
PTR_ADDU k1, k0, k1 #06: k1=seg entry address
PTR_L k1, 0(k1) #07: k1=seg entry
_MFC0 k0, MIPS_COP_0_BAD_VADDR #08: k0=bad address (again)
- beq k1, zero, 5f #09: ==0 -- no page table
+ beq k1, zero, MIPSX(nopagetable) #09: ==0 -- no page table
PTR_SRL k0, (PGSHIFT-2) #0a: k0=VPN (aka va>>10)
andi k0, k0, (NBPG-8) #0b: k0=page tab offset
PTR_ADDU k1, k1, k0 #0c: k1=pte address
@@ -376,10 +376,6 @@
nop #19: needed by R4000/4400
nop #1a: needed by R4000/4400
eret #1b: return from exception
-4: j _C_LABEL(MIPSX(tlb_miss_exception)) #1c: kernel exception
- nop #1d: branch delay slot
-5: j MIPSX(slowfault) #1e: no page table present
- nop #1f: branch delay slot
.set at
_VECTOR_END(MIPSX(tlb_miss))
@@ -403,14 +399,14 @@
.set noat
dmfc0 k0, MIPS_COP_0_BAD_VADDR #00: k0=bad address
lui k1, %hi(CPUVAR(PMAP_SEGBASE)) #01: k1=hi of segbase
- bltz k0, 4f #02: k0<0 -> 4f (kernel fault)
+ bltz k0, MIPSX(kernelfault) #02: k0<0 -> 4f (kernel fault)
PTR_SRL k0, 2*PGSHIFT-2-PTR_SCALESHIFT #03: k0=seg offset (almost)
PTR_L k1, %lo(CPUVAR(PMAP_SEGBASE))(k1)#04: k1=segment tab base
andi k0, NBPG-(1<<PTR_SCALESHIFT) #05: k0=seg offset (mask 0x3)
PTR_ADDU k1, k0, k1 #06: k1=seg entry address
PTR_L k1, 0(k1) #07: k1=seg entry
dmfc0 k0, MIPS_COP_0_BAD_VADDR #08: k0=bad address (again)
- beq k1, zero, 5f #09: ==0 -- no page table
+ beq k1, zero, MIPSX(nopagetable) #09: ==0 -- no page table
PTR_SRL k0, (PGSHIFT-2) #0a: k0=VPN (aka va>>10)
andi k0, k0, (NBPG-8) #0b: k0=page tab offset
PTR_ADDU k1, k1, k0 #0c: k1=pte address
@@ -429,37 +425,27 @@
nop #19: needed by R4000/4400
nop #1a: needed by R4000/4400
eret #1b: return from exception
-4: j _C_LABEL(MIPSX(tlb_miss_exception)) #1c: kernel exception
- nop #1d: branch delay slot
-5: j MIPSX(slowfault) #1e: no page table present
- nop #1f: branch delay slot
.set at
_VECTOR_END(MIPSX(xtlb_miss))
+#else
+ .space 128
#endif /* USE_64BIT_CP0_FUNCTIONS */
/*
* Vector to real handler in KSEG1.
*/
VECTOR(MIPSX(cache), unknown)
- PTR_LA k0, _C_LABEL(MIPSX(cache_exception))
- li k1, MIPS_PHYS_MASK
- and k0, k1
- li k1, MIPS_KSEG1_START
- or k0, k1
- j k0
- nop
+ PTR_LA k0, _C_LABEL(MIPSX(cache_exception)) #00
+ li k1, MIPS_PHYS_MASK #02
+ and k0, k1 #03
+ li k1, MIPS_KSEG1_START #04
+ or k0, k1 #05
+ lui k1, %hi(CPUVAR(CURLWP)) #06: k1=hi of curlwp
+ j k0 #07
+ PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #08: k1=lo of curlwp
_VECTOR_END(MIPSX(cache))
/*
- * Handle MIPS32/MIPS64 style interrupt exception vector.
- */
-VECTOR(MIPSX(intr), unknown)
- PTR_LA k0, MIPSX(kern_intr)
- j k0
- nop
-_VECTOR_END(MIPSX(intr))
-
-/*
*----------------------------------------------------------------------------
*
* mipsN_exception --
@@ -497,11 +483,45 @@
# we dont have to shift.
PTR_L k0, 0(k0) #09: get the function address
#nop # -slip-
+ lui k1, %hi(CPUVAR(CURLWP)) #0a: k1=hi of curlwp
+ j k0 #0b: jump to the function
+ PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #0c: k1=lo of curlwp
+ nop #0d
+ nop #0e
+#ifndef _LP64
+ nop #0f
+#endif
+MIPSX(kernelfault):
+ lui k1, %hi(CPUVAR(CURLWP)) #10: k1=hi of curlwp
+ j _C_LABEL(MIPSX(kernel_tlb_miss)) #11: kernel exception
+ PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #12: k1=lo of curlwp
+ nop #13: branch delay slot
+MIPSX(nopagetable):
+ lui k1, %hi(CPUVAR(CURLWP)) #14: k1=hi of curlwp
+ j MIPSX(slowfault) #15: no page table present
+ PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #16: k1=lo of curlwp
+ nop #17: branch delay slot
+ .set at
+_VECTOR_END(MIPSX(exception))
+/*
+ * Handle MIPS32/MIPS64 style interrupt exception vector.
+ */
+VECTOR(MIPSX(intr), unknown)
+ .set noat
+ mfc0 k1, MIPS_COP_0_STATUS #00: get the status register
+ nop #01: stall
+ and k1, k1, MIPS3_SR_KSU_USER #02: test for user mode
+ PTR_LA k0, MIPSX(user_intr) #03: assume user mode
+ bne k1, zero, 1f #05: yep, do it
+ nop #06: branch deay
+ PTR_LA k0, MIPSX(kern_intr) #07: nope, kernel intr
+1:
+ lui k1, %hi(CPUVAR(CURLWP)) #09: k1=hi of curlwp
j k0 #0a: jump to the function
- nop #0b: branch delay slot
+ PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #0b: k1=lo of curlwp
.set at
-_VECTOR_END(MIPSX(exception))
+_VECTOR_END(MIPSX(intr))
/*----------------------------------------------------------------------------
*
@@ -520,6 +540,7 @@
* We couldn't find a TLB entry.
* Find out what mode we came from and call the appropriate handler.
*/
+ .org ((. + 31) & ~31) + 12
MIPSX(slowfault):
.set noat
mfc0 k0, MIPS_COP_0_STATUS
@@ -716,61 +737,62 @@
* the condition. The context can be manipulated alternatively via
* curlwp->l_md.md_regs.
*/
+ .p2align 5
NESTED_NOPROFILE(MIPSX(user_gen_exception), CALLFRAME_SIZ, ra)
.set noat
.mask 0x80000000, -4
/*
* Save all of the registers except for the kernel temporaries in u_pcb.
*/
- PTR_L k1, CPUVAR(CURLWP)
- PTR_L k1, L_ADDR(k1)
- PTR_ADDU k1, k1, USPACE - FRAME_SIZ
- REG_S AT, FRAME_AST(k1)
- REG_S v0, FRAME_V0(k1)
- REG_S v1, FRAME_V1(k1)
+ /* K1 already has CURLWP */
+ PTR_L k0, L_ADDR(k1)
+ PTR_ADDU k0, k0, USPACE - FRAME_SIZ
+ REG_S AT, FRAME_AST(k0)
+ REG_S v0, FRAME_V0(k0)
+ REG_S v1, FRAME_V1(k0)
mflo v0
- REG_S a0, FRAME_A0(k1)
- REG_S a1, FRAME_A1(k1)
- REG_S a2, FRAME_A2(k1)
- REG_S a3, FRAME_A3(k1)
+ REG_S a0, FRAME_A0(k0)
+ REG_S a1, FRAME_A1(k0)
+ REG_S a2, FRAME_A2(k0)
+ REG_S a3, FRAME_A3(k0)
mfhi v1
- REG_S t0, FRAME_T0(k1)
- REG_S t1, FRAME_T1(k1)
- REG_S t2, FRAME_T2(k1)
- REG_S t3, FRAME_T3(k1)
+ REG_S t0, FRAME_T0(k0)
+ REG_S t1, FRAME_T1(k0)
+ REG_S t2, FRAME_T2(k0)
+ REG_S t3, FRAME_T3(k0)
mfc0 a0, MIPS_COP_0_STATUS # 1st arg is STATUS
- REG_S ta0, FRAME_TA0(k1)
- REG_S ta1, FRAME_TA1(k1)
- REG_S ta2, FRAME_TA2(k1)
- REG_S ta3, FRAME_TA3(k1)
+ REG_S ta0, FRAME_TA0(k0)
+ REG_S ta1, FRAME_TA1(k0)
+ REG_S ta2, FRAME_TA2(k0)
+ REG_S ta3, FRAME_TA3(k0)
mfc0 a1, MIPS_COP_0_CAUSE # 2nd arg is CAUSE
- REG_S s0, FRAME_S0(k1)
- REG_S s1, FRAME_S1(k1)
- REG_S s2, FRAME_S2(k1)
- REG_S s3, FRAME_S3(k1)
+ REG_S s0, FRAME_S0(k0)
+ REG_S s1, FRAME_S1(k0)
+ REG_S s2, FRAME_S2(k0)
+ REG_S s3, FRAME_S3(k0)
_MFC0 a2, MIPS_COP_0_BAD_VADDR # 3rd arg is fault address
- REG_S s4, FRAME_S4(k1)
- REG_S s5, FRAME_S5(k1)
- REG_S s6, FRAME_S6(k1)
- REG_S s7, FRAME_S7(k1)
+ REG_S s4, FRAME_S4(k0)
+ REG_S s5, FRAME_S5(k0)
+ REG_S s6, FRAME_S6(k0)
+ REG_S s7, FRAME_S7(k0)
_MFC0 a3, MIPS_COP_0_EXC_PC # 4th arg is exception PC
- REG_S t8, FRAME_T8(k1)
- REG_S t9, FRAME_T9(k1)
- REG_S gp, FRAME_GP(k1)
- REG_S sp, FRAME_SP(k1)
- REG_S s8, FRAME_S8(k1)
- REG_S ra, FRAME_RA(k1)
- REG_S a0, FRAME_SR(k1)
- REG_S v0, FRAME_MULLO(k1)
- REG_S v1, FRAME_MULHI(k1)
- REG_S a3, FRAME_EPC(k1)
+ REG_S t8, FRAME_T8(k0)
+ REG_S t9, FRAME_T9(k0)
+ REG_S gp, FRAME_GP(k0)
+ REG_S sp, FRAME_SP(k0)
+ REG_S s8, FRAME_S8(k0)
+ REG_S ra, FRAME_RA(k0)
+ REG_S a0, FRAME_SR(k0)
+ REG_S v0, FRAME_MULLO(k0)
+ REG_S v1, FRAME_MULHI(k0)
+ REG_S a3, FRAME_EPC(k0)
#ifdef IPL_ICU_MASK
.set at
INT_L t0, _C_LABEL(md_imask)
- INT_S t0, FRAME_PPL(k1)
+ INT_S t0, FRAME_PPL(k0)
.set noat
#endif
- PTR_ADDU sp, k1, -CALLFRAME_SIZ # switch to kernel SP
+ PTR_ADDU sp, k0, -CALLFRAME_SIZ # switch to kernel SP
#ifdef __GP_SUPPORT__
PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
#endif
@@ -783,7 +805,7 @@
/*
* Call the trap handler.
*/
- PTR_L MIPS_CURLWP, CPUVAR(CURLWP)
+ move MIPS_CURLWP, k1
mtc0 t0, MIPS_COP_0_STATUS
COP0_SYNC
jal _C_LABEL(trap)
@@ -879,68 +901,69 @@
* Save user context in u_pcb, then call syscall() to process a system call.
* The context can be manipulated alternatively via curlwp->p_md.md_regs;
*/
+ .p2align 5
NESTED_NOPROFILE(MIPSX(systemcall), CALLFRAME_SIZ, ra)
.set noat
.mask 0x80000000, -4
- PTR_L k1, CPUVAR(CURLWP)
- PTR_L k1, L_ADDR(k1)
+ /* k1 already cpulwp */
+ PTR_L k0, L_ADDR(k1)
#nop # -slip-
- PTR_ADDU k1, k1, USPACE - FRAME_SIZ
- #REG_S AT, FRAME_AST(k1)
- REG_S v0, FRAME_V0(k1) # syscall #
- REG_S v1, FRAME_V1(k1) # used by syscall()
+ PTR_ADDU k0, k0, USPACE - FRAME_SIZ
+ #REG_S AT, FRAME_AST(k0)
+ REG_S v0, FRAME_V0(k0) # syscall #
+ REG_S v1, FRAME_V1(k0) # used by syscall()
mflo v0
- REG_S a0, FRAME_A0(k1)
- REG_S a1, FRAME_A1(k1)
- REG_S a2, FRAME_A2(k1)
- REG_S a3, FRAME_A3(k1)
- PTR_L a0, CPUVAR(CURLWP) # 1st arg is curlwp
+ REG_S a0, FRAME_A0(k0)
+ REG_S a1, FRAME_A1(k0)
+ REG_S a2, FRAME_A2(k0)
+ REG_S a3, FRAME_A3(k0)
+ move a0, k1 # 1st arg is curlwp
mfhi v1
mfc0 a2, MIPS_COP_0_CAUSE # 3rd arg is CAUSE
- REG_S s0, FRAME_S0(k1)
- REG_S s1, FRAME_S1(k1)
- REG_S s2, FRAME_S2(k1)
- REG_S s3, FRAME_S3(k1)
+ REG_S s0, FRAME_S0(k0)
+ REG_S s1, FRAME_S1(k0)
+ REG_S s2, FRAME_S2(k0)
+ REG_S s3, FRAME_S3(k0)
_MFC0 a3, MIPS_COP_0_EXC_PC # 4th arg is PC
- REG_S s4, FRAME_S4(k1)
- REG_S s5, FRAME_S5(k1)
- REG_S s6, FRAME_S6(k1)
- REG_S s7, FRAME_S7(k1)
+ REG_S s4, FRAME_S4(k0)
+ REG_S s5, FRAME_S5(k0)
+ REG_S s6, FRAME_S6(k0)
+ REG_S s7, FRAME_S7(k0)
move s0, t0 # since the saved registers have
move s1, t1 # been saved we can use them to
move s2, t2 # stash most of temporary regs
- REG_S t3, FRAME_T3(k1) # syscall saved gp for fork
+ REG_S t3, FRAME_T3(k0) # syscall saved gp for fork
mfc0 a1, MIPS_COP_0_STATUS # 2nd arg is STATUS
#if defined(__mips_n32) || defined(__mips_n64)
- REG_S a4, FRAME_A4(k1)
- REG_S a5, FRAME_A5(k1)
- REG_S a6, FRAME_A6(k1)
- REG_S a7, FRAME_A7(k1)
+ REG_S a4, FRAME_A4(k0)
+ REG_S a5, FRAME_A5(k0)
+ REG_S a6, FRAME_A6(k0)
+ REG_S a7, FRAME_A7(k0)
#else
move s4, ta0
move s5, ta1
move s6, ta2
move s7, ta3
#endif
- #REG_S t8, FRAME_T8(k1)
- #REG_S t9, FRAME_T9(k1)
- REG_S gp, FRAME_GP(k1)
- REG_S sp, FRAME_SP(k1)
- REG_S s8, FRAME_S8(k1)
- REG_S ra, FRAME_RA(k1)
- REG_S a1, FRAME_SR(k1)
- REG_S v0, FRAME_MULLO(k1)
- REG_S v1, FRAME_MULHI(k1)
- REG_S a3, FRAME_EPC(k1)
+ #REG_S t8, FRAME_T8(k0)
+ #REG_S t9, FRAME_T9(k0)
+ REG_S gp, FRAME_GP(k0)
+ REG_S sp, FRAME_SP(k0)
+ REG_S s8, FRAME_S8(k0)
+ REG_S ra, FRAME_RA(k0)
+ REG_S a1, FRAME_SR(k0)
+ REG_S v0, FRAME_MULLO(k0)
+ REG_S v1, FRAME_MULHI(k0)
+ REG_S a3, FRAME_EPC(k0)
#ifdef IPL_ICU_MASK
.set at
INT_L t0, _C_LABEL(md_imask)
- INT_S t0, FRAME_PPL(k1)
+ INT_S t0, FRAME_PPL(k0)
.set noat
#endif
PTR_L t0, L_PROC(a0) # curlwp->l_proc (used below)
move MIPS_CURLWP, a0 # set curlwp reg
- PTR_ADDU sp, k1, -CALLFRAME_SIZ
+ PTR_ADDU sp, k0, -CALLFRAME_SIZ
#ifdef __GP_SUPPORT__
PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
#endif
@@ -1064,6 +1087,7 @@
* Panic on cache errors. A lot more could be done to recover
* from some types of errors but it is tricky.
*/
+ .p2align 5
NESTED_NOPROFILE(MIPSX(cache_exception), KERNFRAME_SIZ, ra)
.set noat
.mask 0x80000000, -4
@@ -1119,9 +1143,13 @@
* call cpu_intr() to process it.
*
*/
+ .p2align 5
NESTED_NOPROFILE(MIPSX(kern_intr), KERNFRAME_SIZ, ra)
.set noat
.mask 0x80000000, -4
+ /*
+ * curlwp is in k1
+ */
PTR_SUBU sp, sp, KERNFRAME_SIZ
/*
* Save the relevant kernel registers onto the stack.
@@ -1171,7 +1199,7 @@
#endif
RESET_EXCEPTION_LEVEL_DISABLE_INTERRUPTS(v0)
COP0_SYNC
- PTR_L MIPS_CURLWP, CPUVAR(CURLWP) # XXX Atheros HAL
+ move MIPS_CURLWP, k1 # XXX Atheros HAL
jal _C_LABEL(cpu_intr)
and a3, a0, a1 # 4th is STATUS & CAUSE
/*
@@ -1259,6 +1287,7 @@
*
*----------------------------------------------------------------------------
*/
+ .p2align 5
NESTED_NOPROFILE(MIPSX(user_intr), CALLFRAME_SIZ, ra)
.set noat
.mask 0x80000000, -4
@@ -1266,50 +1295,50 @@
* Save the relevant user registers into the u_pcb.
* We don't need to save s0 - s8 because the compiler does it for us.
*/
- PTR_L k1, CPUVAR(CURLWP)
- PTR_L k1, L_ADDR(k1)
- PTR_ADDU k1, k1, USPACE - FRAME_SIZ
- REG_S AT, FRAME_AST(k1)
- REG_S v0, FRAME_V0(k1)
- REG_S v1, FRAME_V1(k1)
+ /* k1 contains curlwp */
+ PTR_L k0, L_ADDR(k1)
+ PTR_ADDU k0, k0, USPACE - FRAME_SIZ
+ REG_S AT, FRAME_AST(k0)
+ REG_S v0, FRAME_V0(k0)
+ REG_S v1, FRAME_V1(k0)
mflo v0
- REG_S a0, FRAME_A0(k1)
- REG_S a1, FRAME_A1(k1)
- REG_S a2, FRAME_A2(k1)
- REG_S a3, FRAME_A3(k1)
+ REG_S a0, FRAME_A0(k0)
+ REG_S a1, FRAME_A1(k0)
+ REG_S a2, FRAME_A2(k0)
+ REG_S a3, FRAME_A3(k0)
mfhi v1
- REG_S t0, FRAME_T0(k1)
- REG_S t1, FRAME_T1(k1)
- REG_S t2, FRAME_T2(k1)
- REG_S t3, FRAME_T3(k1)
+ REG_S t0, FRAME_T0(k0)
+ REG_S t1, FRAME_T1(k0)
+ REG_S t2, FRAME_T2(k0)
+ REG_S t3, FRAME_T3(k0)
mfc0 a0, MIPS_COP_0_STATUS # 1st arg is STATUS
- REG_S ta0, FRAME_TA0(k1)
- REG_S ta1, FRAME_TA1(k1)
- REG_S ta2, FRAME_TA2(k1)
- REG_S ta3, FRAME_TA3(k1)
+ REG_S ta0, FRAME_TA0(k0)
+ REG_S ta1, FRAME_TA1(k0)
+ REG_S ta2, FRAME_TA2(k0)
+ REG_S ta3, FRAME_TA3(k0)
mfc0 a1, MIPS_COP_0_CAUSE # 2nd arg is CAUSE
- REG_S t8, FRAME_T8(k1)
- REG_S t9, FRAME_T9(k1)
- REG_S gp, FRAME_GP(k1)
- REG_S sp, FRAME_SP(k1)
+ REG_S t8, FRAME_T8(k0)
+ REG_S t9, FRAME_T9(k0)
+ REG_S gp, FRAME_GP(k0)
+ REG_S sp, FRAME_SP(k0)
_MFC0 a2, MIPS_COP_0_EXC_PC # 3rd arg is PC
- REG_S ra, FRAME_RA(k1)
- REG_S a0, FRAME_SR(k1)
- REG_S v0, FRAME_MULLO(k1)
- REG_S v1, FRAME_MULHI(k1)
- REG_S a2, FRAME_EPC(k1)
+ REG_S ra, FRAME_RA(k0)
+ REG_S a0, FRAME_SR(k0)
+ REG_S v0, FRAME_MULLO(k0)
+ REG_S v1, FRAME_MULHI(k0)
+ REG_S a2, FRAME_EPC(k0)
#ifdef IPL_ICU_MASK
.set at
INT_L t0, _C_LABEL(md_imask)
- INT_S t0, FRAME_PPL(k1)
+ INT_S t0, FRAME_PPL(k0)
.set noat
#endif
- PTR_ADDU sp, k1, -CALLFRAME_SIZ # switch to kernel SP
+ PTR_ADDU sp, k0, -CALLFRAME_SIZ # switch to kernel SP
#ifdef __GP_SUPPORT__
PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
#endif
- PTR_S MIPS_CURLWP, MIPS_CURLWP_FRAME(k1)# save curlwp reg
- PTR_L MIPS_CURLWP, CPUVAR(CURLWP) # set curlwp reg
+ PTR_S MIPS_CURLWP, MIPS_CURLWP_FRAME(k0)# save curlwp reg (s7)
+ move MIPS_CURLWP, k1 # set curlwp reg (s7)
/*
* Turn off fpu and enter kernel mode
*/
@@ -1350,7 +1379,7 @@
* Check pending asynchronous traps.
*/
beq v0, zero, 1f # if no, skip ast processing
- PTR_L MIPS_CURLWP, MIPS_CURLWP_FRAME(a1)# restore curlwp reg
+ nop
/*
* We have pending asynchronous traps; save remaining user state in u_pcb.
*/
@@ -1361,10 +1390,9 @@
REG_S s4, FRAME_S4(a1)
REG_S s5, FRAME_S5(a1)
REG_S s6, FRAME_S6(a1)
- REG_S s7, FRAME_S7(a1)
+ #REG_S s7, FRAME_S7(a1) # MIPS_CURLWP_FRAME
REG_S s8, FRAME_S8(a1)
REG_L a0, FRAME_EPC(a1) # argument is interrupted PC
- PTR_L MIPS_CURLWP, CPUVAR(CURLWP) # set curlwp reg
#ifdef IPL_ICU_MASK
jal _C_LABEL(spllowersofthigh);
nop
@@ -1403,11 +1431,12 @@
REG_L s4, FRAME_S4(a1)
REG_L s5, FRAME_S5(a1)
REG_L s6, FRAME_S6(a1)
- REG_L s7, FRAME_S7(a1)
+ #REG_L s7, FRAME_S7(a1) # MIPS_CURLWP_FRAME
REG_L s8, FRAME_S8(a1)
# mtc0 a0, MIPS_COP_0_STATUS # this should disable interrupts
1:
+ PTR_L MIPS_CURLWP, MIPS_CURLWP_FRAME(a1)# restore curlwp reg
REG_L t0, FRAME_MULLO(a1)
REG_L t1, FRAME_MULHI(a1)
REG_L v0, FRAME_EPC(a1)
@@ -1500,12 +1529,13 @@
dsll32 k1, k1, 0
#endif
bgez k0, _C_LABEL(MIPSX(kern_gen_exception)) # full trap processing
+ move k1, MIPS_CURLWP
PTR_SUBU k0, k0, k1
INT_L k1, _C_LABEL(Sysmapsize) # index within range?
PTR_SRL k0, k0, PGSHIFT
sltu k1, k0, k1
- beq k1, zero, MIPSX(outofworld) # No. Failing beyond. . .
- nop # - delay slot -
+ beq k1, zero, _C_LABEL(MIPSX(kern_gen_exception)) # No. Failing beyond. . .
+ move k1, MIPS_CURLWP # - delay slot -
PTR_L k1, _C_LABEL(Sysmap)
PTR_SLL k0, k0, 2 # compute offset from index
@@ -1519,7 +1549,8 @@
mfc0 k0, MIPS_COP_0_TLB_INDEX
nop
- bltz k0, MIPSX(outofworld) # ASSERT(TLB entry exists)
+ bltz k0, _C_LABEL(MIPSX(kern_gen_exception)) # ASSERT(TLB entry exists)
+ move k1, MIPS_CURLWP
INT_L k0, 0(k1) # get PTE entry
_SLL k0, k0, WIRED_SHIFT # get rid of "wired" bit
@@ -1529,6 +1560,7 @@
and k0, k0, MIPS3_PG_V # check for valid entry
nop # required for QED5230
beq k0, zero, _C_LABEL(MIPSX(kern_gen_exception)) # PTE invalid
+ move k1, MIPS_CURLWP
INT_L k0, 4(k1) # get odd PTE entry
_SLL k0, k0, WIRED_SHIFT
mfc0 k1, MIPS_COP_0_TLB_INDEX
@@ -1551,7 +1583,8 @@
KernTLBIOdd:
mfc0 k0, MIPS_COP_0_TLB_INDEX
nop
- bltz k0, MIPSX(outofworld) # assert(TLB Entry exists)
+ bltz k0, _C_LABEL(MIPSX(kern_gen_exception)) # assert(TLB Entry exists)
+ move k1, MIPS_CURLWP
INT_L k0, 0(k1) # get PTE entry
_SLL k0, k0, WIRED_SHIFT # get rid of wired bit
@@ -1561,6 +1594,7 @@
and k0, k0, MIPS3_PG_V # check for valid entry
nop # required for QED5230
beq k0, zero, _C_LABEL(MIPSX(kern_gen_exception)) # PTE invalid
+ move k1, MIPS_CURLWP
INT_L k0, -4(k1) # get even PTE entry
_SLL k0, k0, WIRED_SHIFT
mfc0 k1, MIPS_COP_0_TLB_INDEX
@@ -1583,7 +1617,7 @@
/*----------------------------------------------------------------------------
*
- * mipsN_tlb_miss_exception --
+ * mipsN_kernel_tlb_miss --
*
* Handle a TLB miss exception from kernel mode in kernel space.
* The BaddVAddr, Context, and EntryHi registers contain the failed
@@ -1597,7 +1631,7 @@
*
*----------------------------------------------------------------------------
*/
-LEAF_NOPROFILE(MIPSX(tlb_miss_exception))
+LEAF_NOPROFILE(MIPSX(kernel_tlb_miss))
.set noat
_MFC0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
#if VM_MIN_KERNEL_ADDRESS == MIPS_KSEG2_START
@@ -1613,13 +1647,16 @@
#ifdef newsmips
/* news5000 has ROM work area at 0xfff00000. */
bne k1, zero, 1f
- nop
+ nop
j checkromwork
- nop # - delay slot -
+ nop # - delay slot -
1:
#else
- beq k1, zero, MIPSX(outofworld) # No. Failing beyond. . .
- nop # - delay slot -
+ /*
+ * If we are beyond the bounds of Sysmap, let trap panic for us.
+ */
+ beq k1, zero, _C_LABEL(MIPSX(kern_gen_exception)) # No. Failing beyond. . .
+ move k1, MIPS_CURLWP # - delay slot -
#endif
PTR_L k1, _C_LABEL(Sysmap)
PTR_SRL k0, k0, 1
@@ -1646,6 +1683,7 @@
nop
eret
+#if 0
MIPSX(outofworld):
/* eret to panic so shutdown can use K2. Try to ensure valid $sp. */
PTR_LA a0, _C_LABEL(panic)
@@ -1668,9 +1706,10 @@
PTR_LA sp, start # set sp to a valid place
1: PTR_LA a0, 9f # string
eret
+#endif
.set at
-END(MIPSX(tlb_miss_exception))
+END(MIPSX(kernel_tlb_miss))
MSG("TLB out of universe: ksp %p epc %p vaddr %p")
@@ -1684,11 +1723,11 @@
/*--------------------------------------------------------------------------
*
- * mipsN_SetPID --
+ * mipsN_tlb_set_asid --
*
* Write the given pid into the TLB pid reg.
*
- * mips3_SetPID(pid)
+ * mips3_tlb_set_asid(uint32_t pid)
* int pid;
*
* Results:
@@ -1732,8 +1771,8 @@
RESET_EXCEPTION_LEVEL_DISABLE_INTERRUPTS(v0)
COP0_SYNC
nop
- lw a2, 8(a1) # fetch tlb->tlb_lo0
- lw a3, 12(a1) # fetch tlb->tlb_lo1
+ INT_L a2, TLBMASK_LO0(a1) # fetch tlb->tlb_lo0
+ INT_L a3, TLBMASK_LO1(a1) # fetch tlb->tlb_lo1
mfc0 v0, MIPS_COP_0_TLB_PG_MASK # Save current page mask.
_MFC0 t0, MIPS_COP_0_TLB_HI # Save the current PID.
@@ -1742,8 +1781,8 @@
_MTC0 a3, MIPS_COP_0_TLB_LO1 # Set up entry low1.
COP0_SYNC
nop
- lw a2, 0(a1) # fetch tlb->tlb_mask
- lw a3, 4(a1) # fetch tlb->tlb_hi
+ INT_L a2, TLBMASK_MASK(a1) # fetch tlb->tlb_mask
+ PTR_L a3, TLBMASK_HI(a1) # fetch tlb->tlb_hi
nop
mtc0 a0, MIPS_COP_0_TLB_INDEX # Set the index.
COP0_SYNC
@@ -1864,7 +1903,7 @@
/*--------------------------------------------------------------------------
*
- * mipsN_TLBRead --
+ * mipsN_tlb_read_indexed --
*
* Read the TLB entry.
*
@@ -1910,11 +1949,11 @@
mtc0 v1, MIPS_COP_0_STATUS # Restore the status register
COP0_SYNC
nop
- sw t2, 0(a1)
- sw t3, 4(a1)
- sw ta0, 8(a1)
+ PTR_S t3, TLBMASK_HI(a1)
+ INT_S ta0, TLBMASK_LO0(a1)
+ INT_S ta1, TLBMASK_LO1(a1)
j ra
- sw ta1, 12(a1)
+ INT_S t2, TLBMASK_MASK(a1)
END(MIPSX(tlb_read_indexed))
#if defined(MIPS3) && !defined(MIPS3_5900)
Index: src/sys/arch/mips/mips/mips_machdep.c
diff -u src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.25 src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.26
--- src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.25 Fri Jan 15 06:46:59 2010
+++ src/sys/arch/mips/mips/mips_machdep.c Sat Jan 16 20:56:33 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.25 2010/01/15 06:46:59 matt Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.26 2010/01/16 20:56:33 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -112,7 +112,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.25 2010/01/15 06:46:59 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.26 2010/01/16 20:56:33 matt Exp $");
#include "opt_cputype.h"
#include "opt_compat_netbsd32.h"
@@ -595,35 +595,31 @@
extern char mips3_exception[], mips3_exception_end[];
/* TLB miss handler address and end */
- extern char mips3_tlb_miss[], mips3_tlb_miss_end[];
- extern char mips3_xtlb_miss[], mips3_xtlb_miss_end[];
+ extern char mips3_tlb_miss[];
+ extern char mips3_xtlb_miss[];
/* Cache error handler */
- extern char mips3_cache[], mips3_cache_end[];
+ extern char mips3_cache[];
/*
* Copy down exception vector code.
*/
- if (mips3_tlb_miss_end - mips3_tlb_miss > 0x80)
- panic("startup: UTLB vector code too large");
- memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips3_tlb_miss,
- mips3_tlb_miss_end - mips3_tlb_miss);
-
- if (mips3_xtlb_miss_end - mips3_xtlb_miss > 0x80)
- panic("startup: XTLB vector code too large");
- memcpy((void *)MIPS3_XTLB_MISS_EXC_VEC, mips3_xtlb_miss,
- mips3_xtlb_miss_end - mips3_xtlb_miss);
-
- if (mips3_cache_end - mips3_cache > 0x80)
- panic("startup: Cache error vector code too large");
- memcpy((void *)MIPS3_CACHE_ERR_EXC_VEC, mips3_cache,
- mips3_cache_end - mips3_cache);
-
+ if (mips3_xtlb_miss - mips3_tlb_miss != 0x80)
+ panic("startup: %s vector code not 128 bytes in length",
+ "UTLB");
+ if (mips3_cache - mips3_xtlb_miss != 0x80)
+ panic("startup: %s vector code not 128 bytes in length",
+ "XTLB");
+ if (mips3_exception - mips3_cache != 0x80)
+ panic("startup: %s vector code not 128 bytes in length",
+ "Cache error");
if (mips3_exception_end - mips3_exception > 0x80)
- panic("startup: General exception vector code too large");
- memcpy((void *)MIPS3_GEN_EXC_VEC, mips3_exception,
- mips3_exception_end - mips3_exception);
+ panic("startup: %s vector code too large",
+ "General exception");
+
+ memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips3_tlb_miss,
+ mips3_exception_end - mips3_tlb_miss);
/*
* Copy locore-function vector.
@@ -703,46 +699,37 @@
static void
mips32_vector_init(void)
{
- /* r4000 exception handler address and end */
- extern char mips32_exception[], mips32_exception_end[];
+ /* r4000 exception handler address */
+ extern char mips32_exception[];
- /* TLB miss handler address and end */
- extern char mips32_tlb_miss[], mips32_tlb_miss_end[];
+ /* TLB miss handler addresses */
+ extern char mips32_tlb_miss[];
/* Cache error handler */
- extern char mips32_cache[], mips32_cache_end[];
+ extern char mips32_cache[];
- /* MIPS32/MIPS64 interrupt exception handler */
+ /* MIPS32 interrupt exception handler */
extern char mips32_intr[], mips32_intr_end[];
/*
* Copy down exception vector code.
*/
- if (mips32_tlb_miss_end - mips32_tlb_miss > 0x80)
- panic("startup: UTLB vector code too large");
- memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips32_tlb_miss,
- mips32_tlb_miss_end - mips32_tlb_miss);
-
- if (mips32_cache_end - mips32_cache > 0x80)
- panic("startup: Cache error vector code too large");
- memcpy((void *)MIPS3_CACHE_ERR_EXC_VEC, mips32_cache,
- mips32_cache_end - mips32_cache);
-
- if (mips32_exception_end - mips32_exception > 0x80)
- panic("startup: General exception vector code too large");
- memcpy((void *)MIPS3_GEN_EXC_VEC, mips32_exception,
- mips32_exception_end - mips32_exception);
-
+ if (mips32_cache - mips32_tlb_miss != 0x100)
+ panic("startup: %s vector code not 128 bytes in length",
+ "UTLB");
+ if (mips32_exception - mips32_cache != 0x80)
+ panic("startup: %s vector code not 128 bytes in length",
+ "Cache error");
+ if (mips32_intr - mips32_exception != 0x80)
+ panic("startup: %s vector code not 128 bytes in length",
+ "General exception");
if (mips32_intr_end - mips32_intr > 0x80)
- panic("startup: interrupt exception vector code too large");
-#if 0 /* XXX - why doesn't mipsNN_intr() work? */
- memcpy((void *)MIPS3_INTR_EXC_VEC, mips32_intr,
- mips32_intr_end - mips32_intr);
-#else
- memcpy((void *)MIPS3_INTR_EXC_VEC, mips32_exception,
- mips32_exception_end - mips32_exception);
-#endif
+ panic("startup: %s vector code too large",
+ "interrupt exception");
+
+ memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips32_tlb_miss,
+ mips32_intr_end - mips32_tlb_miss);
/*
* Copy locore-function vector.
@@ -773,52 +760,41 @@
static void
mips64_vector_init(void)
{
- /* r4000 exception handler address and end */
- extern char mips64_exception[], mips64_exception_end[];
+ /* r4000 exception handler address */
+ extern char mips64_exception[];
- /* TLB miss handler address and end */
- extern char mips64_tlb_miss[], mips64_tlb_miss_end[];
- extern char mips64_xtlb_miss[], mips64_xtlb_miss_end[];
+ /* TLB miss handler addresses */
+ extern char mips64_tlb_miss[];
+ extern char mips64_xtlb_miss[];
/* Cache error handler */
- extern char mips64_cache[], mips64_cache_end[];
+ extern char mips64_cache[];
- /* MIPS32/MIPS64 interrupt exception handler */
+ /* MIPS64 interrupt exception handler */
extern char mips64_intr[], mips64_intr_end[];
/*
* Copy down exception vector code.
*/
- if (mips64_tlb_miss_end - mips64_tlb_miss > 0x80)
- panic("startup: UTLB vector code too large");
- memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips64_tlb_miss,
- mips64_tlb_miss_end - mips64_tlb_miss);
-
- if (mips64_xtlb_miss_end - mips64_xtlb_miss > 0x80)
- panic("startup: XTLB vector code too large");
- memcpy((void *)MIPS3_XTLB_MISS_EXC_VEC, mips64_xtlb_miss,
- mips64_xtlb_miss_end - mips64_xtlb_miss);
-
- if (mips64_cache_end - mips64_cache > 0x80)
- panic("startup: Cache error vector code too large");
- memcpy((void *)MIPS3_CACHE_ERR_EXC_VEC, mips64_cache,
- mips64_cache_end - mips64_cache);
-
- if (mips64_exception_end - mips64_exception > 0x80)
- panic("startup: General exception vector code too large");
- memcpy((void *)MIPS3_GEN_EXC_VEC, mips64_exception,
- mips64_exception_end - mips64_exception);
-
+ if (mips64_xtlb_miss - mips64_tlb_miss != 0x80)
+ panic("startup: %s vector code not 128 bytes in length",
+ "UTLB");
+ if (mips64_cache - mips64_xtlb_miss != 0x80)
+ panic("startup: %s vector code not 128 bytes in length",
+ "XTLB");
+ if (mips64_exception - mips64_cache != 0x80)
+ panic("startup: %s vector code not 128 bytes in length",
+ "Cache error");
+ if (mips64_intr - mips64_exception != 0x80)
+ panic("startup: %s vector code not 128 bytes in length",
+ "General exception");
if (mips64_intr_end - mips64_intr > 0x80)
- panic("startup: interrupt exception vector code too large");
-#if 0 /* XXX - why doesn't mipsNN_intr() work? */
- memcpy((void *)MIPS3_INTR_EXC_VEC, mips64_intr,
- mips64_intr_end - mips64_intr);
-#else
- memcpy((void *)MIPS3_INTR_EXC_VEC, mips64_exception,
- mips64_exception_end - mips64_exception);
-#endif
+ panic("startup: %s vector code too large",
+ "interrupt exception");
+
+ memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips64_tlb_miss,
+ mips64_intr_end - mips64_tlb_miss);
/*
* Copy locore-function vector.
