Module Name: src
Committed By: matt
Date: Sat Feb 6 14:43:15 UTC 2010
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: locore.S
Added Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: spl.S
Log Message:
Split spl functions into their own sources.
Make sure fast softints clear l_ctxswtch in the softint thread, not their own.
To generate a diff of this commit:
cvs rdiff -u -r1.167.38.11 -r1.167.38.12 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/mips/mips/spl.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/locore.S
diff -u src/sys/arch/mips/mips/locore.S:1.167.38.11 src/sys/arch/mips/mips/locore.S:1.167.38.12
--- src/sys/arch/mips/mips/locore.S:1.167.38.11 Sat Feb 6 02:56:23 2010
+++ src/sys/arch/mips/mips/locore.S Sat Feb 6 14:43:15 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.167.38.11 2010/02/06 02:56:23 matt Exp $ */
+/* $NetBSD: locore.S,v 1.167.38.12 2010/02/06 14:43:15 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -264,7 +264,7 @@
#ifdef __HAVE_FAST_SOFTINTS
/*
- * void softint_fast_dispatch(struct lwp *l, int s, void *new_sp);
+ * void softint_fast_dispatch(struct lwp *l, int s);
*
* called at IPL_HIGH
*
@@ -275,17 +275,18 @@
INT_ADDU t1, 1
INT_S t1, CPU_INFO_MTX_COUNT(t0)
REG_L ra, CALLFRAME_RA(sp)
- PTR_S zero, L_CTXSWITCH(MIPS_CURLWP)
+ REG_L v0, CALLFRAME_S0(sp) # get softint lwp
+ PTR_S zero, L_CTXSWITCH(v0) # clear l_ctxswtch
j ra
PTR_ADDU sp, CALLFRAME_SIZ
/*
* Arguments:
* a0 the LWP to switch to
* a1 IPL to execute at
- * a2 the new stack.
*/
NESTED(softint_fast_dispatch, CALLFRAME_SIZ, ra)
PTR_SUBU sp, CALLFRAME_SIZ
+ REG_S a0, CALLFRAME_S0(sp) # save softint lwp
REG_S ra, CALLFRAME_RA(sp) # save return address
.mask 0x80000000, -4
PTR_L t0, L_ADDR(MIPS_CURLWP) # t0 = curlwp->l_addr
@@ -437,139 +438,6 @@
END(longjmp)
#endif
-
-/*
- * MIPS processor interrupt control
- *
- * Used as building blocks for spl(9) kernel interface.
- */
-LEAF(_splraise)
-XLEAF(_splraise_noprof) # does not get mcount hooks
- mfc0 v0, MIPS_COP_0_STATUS # fetch status register
- and a0, a0, MIPS_INT_MASK # extract INT bits
- nor a0, zero, a0 # bitwise inverse of A0
- and a0, a0, v0 # disable retaining other bits
- DYNAMIC_STATUS_MASK(a0,t0) # machine dependent masking
- mtc0 a0, MIPS_COP_0_STATUS # store back
- COP0_SYNC
- and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
- j ra
- nop
-END(_splraise)
-
-LEAF(_spllower)
- mfc0 v0, MIPS_COP_0_STATUS # fetch status register
- li v1, ~MIPS_INT_MASK
- and v1, v0, v1 # turn off INT bit
- nor a0, zero, a0 # bitwise inverse of A0
- and a0, a0, MIPS_INT_MASK # extract INT bits
- or a0, a0, v1 # disable making other bits on
- DYNAMIC_STATUS_MASK(a0,t0) # machine dependent masking
- mtc0 a0, MIPS_COP_0_STATUS # store back
- COP0_SYNC
- and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
- j ra
- nop
-END(_spllower)
-
-LEAF(_splrestore)
- mfc0 v0, MIPS_COP_0_STATUS # fetch status register
- and a0, a0, MIPS_INT_MASK
- li v1, ~MIPS_INT_MASK
- and v1, v1, v0 # turn off every INT bit
- or v1, v1, a0 # set old INT bits
- DYNAMIC_STATUS_MASK(v1,t0) # machine dependent masking
- mtc0 v1, MIPS_COP_0_STATUS # store back
- COP0_SYNC
- and v0, v0, MIPS_INT_MASK
- j ra
- nop
-END(_splrestore)
-
-LEAF(_splset)
-XLEAF(_splset_noprof) # does not get mcount hooks
- mfc0 v0, MIPS_COP_0_STATUS # fetch status register
- and a0, a0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
- li v1, ~(MIPS_INT_MASK | MIPS_SR_INT_IE)
- and v1, v1, v0 # turn off every INT bit
- or v1, v1, a0 # set old INT bits
- DYNAMIC_STATUS_MASK(v1,t0) # machine dependent masking
- mtc0 v1, MIPS_COP_0_STATUS # store back
- COP0_SYNC
- and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
- j ra
- nop
-END(_splset)
-
-LEAF(_splget)
- mfc0 v0, MIPS_COP_0_STATUS # fetch status register
- and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
- j ra
- nop
-END(_splget)
-
-LEAF(_setsoftintr)
- mfc0 v1, MIPS_COP_0_STATUS # save status register
-#if 0
- li a3, ~MIPS_SR_INT_IE
- and a3, v1
- mtc0 a3, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
-#else
- mtc0 zero, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
-#endif
- COP0_SYNC
- nop
- nop
- mfc0 v0, MIPS_COP_0_CAUSE # fetch cause register
- nop
- or v0, v0, a0 # set soft intr. bits
- mtc0 v0, MIPS_COP_0_CAUSE # store back
- COP0_SYNC
- mtc0 v1, MIPS_COP_0_STATUS # enable interrupts
- COP0_SYNC
- j ra
- nop
-END(_setsoftintr)
-
-LEAF(_clrsoftintr)
- mfc0 v1, MIPS_COP_0_STATUS # save status register
-#if 0
- li a3, ~MIPS_SR_INT_IE
- and a3, v1
- mtc0 a3, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
-#else
- mtc0 zero, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
-#endif
- COP0_SYNC
- nop
- nop
- mfc0 v0, MIPS_COP_0_CAUSE # fetch cause register
- nor a0, zero, a0 # bitwise inverse of A0
- and v0, v0, a0 # clear soft intr. bits
- mtc0 v0, MIPS_COP_0_CAUSE # store back
- COP0_SYNC
- mtc0 v1, MIPS_COP_0_STATUS # enable interrupts
- COP0_SYNC
- j ra
- nop
-END(_clrsoftintr)
-
-LEAF(_splnone)
- mtc0 zero, MIPS_COP_0_CAUSE # clear SOFT_INT bits
- COP0_SYNC
-#ifdef _LP64
- li v0, (MIPS_INT_MASK | MIPS_SR_INT_IE | MIPS_SR_KX)
-#else
- li v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
-#endif
- DYNAMIC_STATUS_MASK(v0,t0) # machine dependent masking
- mtc0 v0, MIPS_COP_0_STATUS # enable all sources
- COP0_SYNC
- nop
- j ra
- nop
-END(_splnone)
-
/*
* u_int32_t mips_cp0_cause_read(void)
*
Added files:
Index: src/sys/arch/mips/mips/spl.S
diff -u /dev/null src/sys/arch/mips/mips/spl.S:1.1.2.1
--- /dev/null Sat Feb 6 14:43:15 2010
+++ src/sys/arch/mips/mips/spl.S Sat Feb 6 14:43:15 2010
@@ -0,0 +1,207 @@
+/* $NetBSD: spl.S,v 1.1.2.1 2010/02/06 14:43:15 matt Exp $ */
+
+/*
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Digital Equipment Corporation and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (C) 1989 Digital Equipment Corporation.
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby granted,
+ * provided that the above copyright notice appears in all copies.
+ * Digital Equipment Corporation makes no representations about the
+ * suitability of this software for any purpose. It is provided "as is"
+ * without express or implied warranty.
+ *
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
+ * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
+ * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
+ * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
+ *
+ * @(#)locore.s 8.5 (Berkeley) 1/4/94
+ */
+
+#include "opt_cputype.h" /* which mips CPU levels do we support? */
+
+#include <sys/cdefs.h>
+
+#include <machine/param.h>
+#include <mips/asm.h>
+#include <mips/cpuregs.h>
+
+RCSID("$NetBSD: spl.S,v 1.1.2.1 2010/02/06 14:43:15 matt Exp $")
+
+#include "assym.h"
+
+/*
+ * MIPS processor interrupt control
+ *
+ * Used as building blocks for spl(9) kernel interface.
+ */
+LEAF(_splraise)
+XLEAF(_splraise_noprof) # does not get mcount hooks
+ mfc0 v0, MIPS_COP_0_STATUS # fetch status register
+ and a0, a0, MIPS_INT_MASK # extract INT bits
+ nor a0, zero, a0 # bitwise inverse of A0
+ and a0, a0, v0 # disable retaining other bits
+ DYNAMIC_STATUS_MASK(a0,t0) # machine dependent masking
+ mtc0 a0, MIPS_COP_0_STATUS # store back
+ COP0_SYNC
+ and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+ j ra
+ nop
+END(_splraise)
+
+LEAF(_spllower)
+ mfc0 v0, MIPS_COP_0_STATUS # fetch status register
+ li v1, ~MIPS_INT_MASK
+ and v1, v0, v1 # turn off INT bit
+ nor a0, zero, a0 # bitwise inverse of A0
+ and a0, a0, MIPS_INT_MASK # extract INT bits
+ or a0, a0, v1 # disable making other bits on
+ DYNAMIC_STATUS_MASK(a0,t0) # machine dependent masking
+ mtc0 a0, MIPS_COP_0_STATUS # store back
+ COP0_SYNC
+ and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+ j ra
+ nop
+END(_spllower)
+
+LEAF(_splrestore)
+ mfc0 v0, MIPS_COP_0_STATUS # fetch status register
+ and a0, a0, MIPS_INT_MASK
+ li v1, ~MIPS_INT_MASK
+ and v1, v1, v0 # turn off every INT bit
+ or v1, v1, a0 # set old INT bits
+ DYNAMIC_STATUS_MASK(v1,t0) # machine dependent masking
+ mtc0 v1, MIPS_COP_0_STATUS # store back
+ COP0_SYNC
+ and v0, v0, MIPS_INT_MASK
+ j ra
+ nop
+END(_splrestore)
+
+LEAF(_splset)
+XLEAF(_splset_noprof) # does not get mcount hooks
+ mfc0 v0, MIPS_COP_0_STATUS # fetch status register
+ and a0, a0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+ li v1, ~(MIPS_INT_MASK | MIPS_SR_INT_IE)
+ and v1, v1, v0 # turn off every INT bit
+ or v1, v1, a0 # set old INT bits
+ DYNAMIC_STATUS_MASK(v1,t0) # machine dependent masking
+ mtc0 v1, MIPS_COP_0_STATUS # store back
+ COP0_SYNC
+ and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+ j ra
+ nop
+END(_splset)
+
+LEAF(_splget)
+ mfc0 v0, MIPS_COP_0_STATUS # fetch status register
+ and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+ j ra
+ nop
+END(_splget)
+
+LEAF(_setsoftintr)
+ mfc0 v1, MIPS_COP_0_STATUS # save status register
+#if 0
+ li a3, ~MIPS_SR_INT_IE
+ and a3, v1
+ mtc0 a3, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
+#else
+ mtc0 zero, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
+#endif
+ COP0_SYNC
+ nop
+ nop
+ mfc0 v0, MIPS_COP_0_CAUSE # fetch cause register
+ nop
+ or v0, v0, a0 # set soft intr. bits
+ mtc0 v0, MIPS_COP_0_CAUSE # store back
+ COP0_SYNC
+ mtc0 v1, MIPS_COP_0_STATUS # enable interrupts
+ COP0_SYNC
+ j ra
+ nop
+END(_setsoftintr)
+
+LEAF(_clrsoftintr)
+ mfc0 v1, MIPS_COP_0_STATUS # save status register
+#if 0
+ li a3, ~MIPS_SR_INT_IE
+ and a3, v1
+ mtc0 a3, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
+#else
+ mtc0 zero, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
+#endif
+ COP0_SYNC
+ nop
+ nop
+ mfc0 v0, MIPS_COP_0_CAUSE # fetch cause register
+ nor a0, zero, a0 # bitwise inverse of A0
+ and v0, v0, a0 # clear soft intr. bits
+ mtc0 v0, MIPS_COP_0_CAUSE # store back
+ COP0_SYNC
+ mtc0 v1, MIPS_COP_0_STATUS # enable interrupts
+ COP0_SYNC
+ j ra
+ nop
+END(_clrsoftintr)
+
+LEAF(_splnone)
+ mtc0 zero, MIPS_COP_0_CAUSE # clear SOFT_INT bits
+ COP0_SYNC
+#ifdef _LP64
+ li v0, (MIPS_INT_MASK | MIPS_SR_INT_IE | MIPS_SR_KX)
+#else
+ li v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+#endif
+ DYNAMIC_STATUS_MASK(v0,t0) # machine dependent masking
+ mtc0 v0, MIPS_COP_0_STATUS # enable all sources
+ COP0_SYNC
+ nop
+ j ra
+ nop
+END(_splnone)
+
+ .rdata
+ .globl _C_LABEL(stdsplsw)
+_C_LABEL(splsw):
+ PTR_WORD _C_LABEL(_splraise)
+ PTR_WORD _C_LABEL(_splset)
+ PTR_WORD _C_LABEL(_splget)
+ PTR_WORD _C_LABEL(_spllower)
+ PTR_WORD _C_LABEL(_splnone)
+ PTR_WORD _C_LABEL(_splraise_noprof)
+ PTR_WORD _C_LABEL(_splset_noprof)
+ PTR_WORD _C_LABEL(_setsoftintr)
+ PTR_WORD _C_LABEL(_clrsoftintr)
