Module Name: src
Committed By: cliff
Date: Sun Mar 21 18:43:28 UTC 2010
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: cpu_subr.c
Log Message:
- in cpu_info_alloc, move calling pmap_tlb_info_attach() to
after called mi_cpu_attach(), so we dont trigger assert on
(ci->ci_data.cpu_idlelwp != NULL) in pmap_tlb_info_attach()
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.5 -r1.1.2.6 src/sys/arch/mips/mips/cpu_subr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/cpu_subr.c
diff -u src/sys/arch/mips/mips/cpu_subr.c:1.1.2.5 src/sys/arch/mips/mips/cpu_subr.c:1.1.2.6
--- src/sys/arch/mips/mips/cpu_subr.c:1.1.2.5 Fri Mar 19 23:16:47 2010
+++ src/sys/arch/mips/mips/cpu_subr.c Sun Mar 21 18:43:28 2010
@@ -32,7 +32,7 @@
#include "opt_multiprocessor.h"
#include "opt_sa.h"
-__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.1.2.5 2010/03/19 23:16:47 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.1.2.6 2010/03/21 18:43:28 cliff Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -137,7 +137,6 @@
#else
KASSERT(MIPS_KSEG0_P(ti));
#endif
- pmap_tlb_info_attach(ti, ci);
#ifndef _LP64
/*
@@ -157,6 +156,8 @@
mi_cpu_attach(ci);
+ pmap_tlb_info_attach(ti, ci);
+
/*
* Switch the idle lwp to a direct mapped stack since we use its
* stack and we won't have a TLB entry for it.
@@ -175,6 +176,14 @@
*/
ci->ci_dev = self;
self->dv_private = ci;
+ KASSERT(ci->ci_idepth == 0);
+
+ evcnt_attach_dynamic(&ci->ci_count_compare_evcnt,
+ EVCNT_TYPE_INTR, NULL, device_xname(self),
+ "int 5 (clock)");
+ evcnt_attach_dynamic(&ci->ci_count_compare_missed_evcnt,
+ EVCNT_TYPE_INTR, NULL, device_xname(self),
+ "int 5 (clock) missed");
#ifdef MULTIPROCESSOR
if (ci != &cpu_info_store) {
@@ -628,8 +637,14 @@
while ((cpus_running & cpu_mask) == 0) {
/* spin, spin, spin */
}
+
+ /*
+ * initialize the MIPS count/compare clock
+ */
mips3_cp0_count_write(ci->ci_data.cpu_cc_skew);
- mips3_cp0_compare_write(ci->ci_data.cpu_cc_skew + ci->ci_cycles_per_hz);
+ KASSERT(ci->ci_cycles_per_hz != 0);
+ ci->ci_next_cp0_clk_intr = ci->ci_data.cpu_cc_skew + ci->ci_cycles_per_hz;
+ mips3_cp0_compare_write(ci->ci_next_cp0_clk_intr);
ci->ci_data.cpu_cc_skew = 0;
/*
@@ -662,6 +677,9 @@
ci->ci_data.cpu_cc_skew = mips3_cp0_count_read();
atomic_or_ulong(&ci->ci_flags, CPUF_RUNNING);
atomic_or_ulong(&cpus_running, cpu_mask);
+#if 1 /* XXX TMP */
+ cpu_send_ipi(ci, IPI_NOP);
+#endif
}
}
#endif /* MULTIPROCESSOR */
