Module Name: src
Committed By: matt
Date: Mon Feb 15 07:37:37 UTC 2010
Modified Files:
src/sys/arch/evbmips/alchemy [matt-nb5-mips64]: mach_intr.c
src/sys/arch/evbmips/atheros [matt-nb5-mips64]: mach_intr.c
src/sys/arch/evbmips/evbmips [matt-nb5-mips64]: interrupt.c
src/sys/arch/evbmips/include [matt-nb5-mips64]: intr.h
src/sys/arch/evbmips/malta [matt-nb5-mips64]: malta_intr.c
src/sys/arch/mips/adm5120 [matt-nb5-mips64]: adm5120_intr.c
src/sys/arch/mips/alchemy [matt-nb5-mips64]: au_icu.c
src/sys/arch/mips/alchemy/include [matt-nb5-mips64]: auvar.h
src/sys/arch/mips/atheros [matt-nb5-mips64]: ar5312_intr.c
ar5315_intr.c
src/sys/arch/mips/atheros/include [matt-nb5-mips64]: ar531xvar.h
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c
Log Message:
Adapt to the new interrupt framework for NetBSD/mips.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.3.18.1 src/sys/arch/evbmips/alchemy/mach_intr.c
cvs rdiff -u -r1.2 -r1.2.18.1 src/sys/arch/evbmips/atheros/mach_intr.c
cvs rdiff -u -r1.11.18.2 -r1.11.18.3 src/sys/arch/evbmips/evbmips/interrupt.c
cvs rdiff -u -r1.16.18.2 -r1.16.18.3 src/sys/arch/evbmips/include/intr.h
cvs rdiff -u -r1.19.16.2 -r1.19.16.3 src/sys/arch/evbmips/malta/malta_intr.c
cvs rdiff -u -r1.3 -r1.3.18.1 src/sys/arch/mips/adm5120/adm5120_intr.c
cvs rdiff -u -r1.23 -r1.23.18.1 src/sys/arch/mips/alchemy/au_icu.c
cvs rdiff -u -r1.9 -r1.9.64.1 src/sys/arch/mips/alchemy/include/auvar.h
cvs rdiff -u -r1.6 -r1.6.28.1 src/sys/arch/mips/atheros/ar5312_intr.c
cvs rdiff -u -r1.5 -r1.5.28.1 src/sys/arch/mips/atheros/ar5315_intr.c
cvs rdiff -u -r1.5 -r1.5.74.1 src/sys/arch/mips/atheros/include/ar531xvar.h
cvs rdiff -u -r1.1.2.10 -r1.1.2.11 src/sys/arch/mips/rmi/rmixl_intr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/alchemy/mach_intr.c
diff -u src/sys/arch/evbmips/alchemy/mach_intr.c:1.3 src/sys/arch/evbmips/alchemy/mach_intr.c:1.3.18.1
--- src/sys/arch/evbmips/alchemy/mach_intr.c:1.3 Mon Apr 28 20:23:17 2008
+++ src/sys/arch/evbmips/alchemy/mach_intr.c Mon Feb 15 07:37:35 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mach_intr.c,v 1.3 2008/04/28 20:23:17 martin Exp $ */
+/* $NetBSD: mach_intr.c,v 1.3.18.1 2010/02/15 07:37:35 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mach_intr.c,v 1.3 2008/04/28 20:23:17 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mach_intr.c,v 1.3.18.1 2010/02/15 07:37:35 matt Exp $");
#include "opt_ddb.h"
@@ -63,8 +63,8 @@
}
void
-evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, uint32_t pc, uint32_t ipending)
{
- au_iointr(status, cause, pc, ipending);
+ au_iointr(ipl, pc, ipending);
}
Index: src/sys/arch/evbmips/atheros/mach_intr.c
diff -u src/sys/arch/evbmips/atheros/mach_intr.c:1.2 src/sys/arch/evbmips/atheros/mach_intr.c:1.2.18.1
--- src/sys/arch/evbmips/atheros/mach_intr.c:1.2 Mon Apr 28 20:23:17 2008
+++ src/sys/arch/evbmips/atheros/mach_intr.c Mon Feb 15 07:37:35 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mach_intr.c,v 1.2 2008/04/28 20:23:17 martin Exp $ */
+/* $NetBSD: mach_intr.c,v 1.2.18.1 2010/02/15 07:37:35 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mach_intr.c,v 1.2 2008/04/28 20:23:17 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mach_intr.c,v 1.2.18.1 2010/02/15 07:37:35 matt Exp $");
#include "opt_ddb.h"
@@ -57,8 +57,8 @@
}
void
-evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
{
- ar531x_cpuintr(status, cause, pc, ipending);
+ ar531x_cpuintr(ipl, pc, ipending);
}
Index: src/sys/arch/evbmips/evbmips/interrupt.c
diff -u src/sys/arch/evbmips/evbmips/interrupt.c:1.11.18.2 src/sys/arch/evbmips/evbmips/interrupt.c:1.11.18.3
--- src/sys/arch/evbmips/evbmips/interrupt.c:1.11.18.2 Fri Feb 5 07:39:52 2010
+++ src/sys/arch/evbmips/evbmips/interrupt.c Mon Feb 15 07:37:36 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.11.18.2 2010/02/05 07:39:52 matt Exp $ */
+/* $NetBSD: interrupt.c,v 1.11.18.3 2010/02/15 07:37:36 matt Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.11.18.2 2010/02/05 07:39:52 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.11.18.3 2010/02/15 07:37:36 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -50,38 +50,39 @@
}
void
-cpu_intr(u_int32_t status, u_int32_t cause, vaddr_t pc, u_int32_t ipending)
+cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
- struct clockframe cf;
- struct cpu_info *ci;
+ struct cpu_info * const ci = curcpu();
+ uint32_t pending;
+ int ipl;
+
+ KASSERT(ci->ci_cpl == IPL_HIGH);
- ci = curcpu();
- ci->ci_idepth++;
uvmexp.intrs++;
- if (ipending & MIPS_INT_MASK_5) {
- /* call the common MIPS3 clock interrupt handler */
- cf.pc = pc;
- cf.sr = status;
- mips3_clockintr(&cf);
-
- /* Re-enable clock interrupts. */
- cause &= ~MIPS_INT_MASK_5;
- _splset(MIPS_SR_INT_IE |
- ((status & ~cause) & MIPS_HARD_INT_MASK));
- }
+ while (ppl < (ipl = splintr(&pending))) {
+ splx(ipl); /* lower to interrupt level */
+
+ KASSERT(pending != 0);
- if (ipending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
- MIPS_INT_MASK_3|MIPS_INT_MASK_4)) {
- /* Process I/O and error interrupts. */
- evbmips_iointr(status, cause, pc, ipending);
+ if (pending & MIPS_INT_MASK_5) {
+ struct clockframe cf;
+ KASSERT(ipl == IPL_SCHED);
+ /* call the common MIPS3 clock interrupt handler */
+ cf.pc = pc;
+ cf.sr = status;
+ cf.intr = (ci->ci_idepth > 1);
+ mips3_clockintr(&cf);
+ }
+
+ if (pending & (MIPS_INT_MASK_0|MIPS_INT_MASK_1|MIPS_INT_MASK_2|
+ MIPS_INT_MASK_3|MIPS_INT_MASK_4)) {
+ KASSERT(ipl == IPL_VM);
+ /* Process I/O and error interrupts. */
+ evbmips_iointr(ipl, pc, pending);
+ }
+ (void)splhigh(); /* disable interrupts */
}
- ci->ci_idepth--;
-#ifdef __HAVE_FAST_SOFTINTS
- ipending &= (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0);
- if (ipending == 0)
- return;
- softint_process(ipending);
-#endif
+ KASSERT(ci->ci_cpl == IPL_HIGH);
}
Index: src/sys/arch/evbmips/include/intr.h
diff -u src/sys/arch/evbmips/include/intr.h:1.16.18.2 src/sys/arch/evbmips/include/intr.h:1.16.18.3
--- src/sys/arch/evbmips/include/intr.h:1.16.18.2 Sat Feb 6 02:57:43 2010
+++ src/sys/arch/evbmips/include/intr.h Mon Feb 15 07:37:36 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.16.18.2 2010/02/06 02:57:43 matt Exp $ */
+/* $NetBSD: intr.h,v 1.16.18.3 2010/02/15 07:37:36 matt Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@@ -33,64 +33,10 @@
#define _EVBMIPS_INTR_H_
#include <sys/queue.h>
-
-#define IPL_NONE 0 /* disable only this interrupt */
-#define IPL_SOFTCLOCK 1 /* software interrupts */
-#define IPL_SOFTBIO 1 /* software interrupts */
-#define IPL_SOFTNET 2 /* software interrupts */
-#define IPL_SOFTSERIAL 2 /* software interrupts */
-#define IPL_VM 3
-#define IPL_SCHED 4
-#define IPL_HIGH 4
-
-#define _IPL_N 5 /* max IPL + 1 */
-
-#define _IPL_SI0_FIRST IPL_SOFTCLOCK
-#define _IPL_SI0_LAST IPL_SOFTBIO
-
-#define _IPL_SI1_FIRST IPL_SOFTNET
-#define _IPL_SI1_LAST IPL_SOFTSERIAL
-
-#define IST_UNUSABLE -1 /* interrupt cannot be used */
-#define IST_NONE 0 /* none (dummy) */
-#define IST_PULSE 1 /* pulsed */
-#define IST_EDGE 2 /* edge-triggered */
-#define IST_LEVEL 3 /* level-triggered */
-#define IST_LEVEL_HIGH 4 /* level triggered, active high */
-#define IST_LEVEL_LOW 5 /* level triggered, active low */
+#include <mips/intr.h>
#ifdef _KERNEL
-#include <mips/locore.h>
-
-extern const uint32_t ipl_sr_bits[_IPL_N];
-
-#define spl0() (void) _spllower(0)
-#define splx(s) (void) _splset(s)
-
-#define splsoft() _splraise(ipl_sr_bits[IPL_SOFT])
-
-typedef int ipl_t;
-typedef struct {
- ipl_t _sr;
-} ipl_cookie_t;
-
-static inline ipl_cookie_t
-makeiplcookie(ipl_t ipl)
-{
-
- return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
-}
-
-static inline int
-splraiseipl(ipl_cookie_t icookie)
-{
-
- return _splraise(icookie._sr);
-}
-
-#include <sys/spl.h>
-
struct evbmips_intrhand {
LIST_ENTRY(evbmips_intrhand) ih_q;
int (*ih_func)(void *);
@@ -99,10 +45,11 @@
int ih_ipl;
};
-void evbmips_intr_init(void);
void intr_init(void);
-void evbmips_iointr(uint32_t, uint32_t, uint32_t, uint32_t);
+void evbmips_intr_init(void);
+void evbmips_iointr(int, vaddr_t, uint32_t);
void *evbmips_intr_establish(int, int (*)(void *), void *);
void evbmips_intr_disestablish(void *);
+
#endif /* _KERNEL */
#endif /* ! _EVBMIPS_INTR_H_ */
Index: src/sys/arch/evbmips/malta/malta_intr.c
diff -u src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.2 src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.3
--- src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.2 Sat Feb 6 02:59:04 2010
+++ src/sys/arch/evbmips/malta/malta_intr.c Mon Feb 15 07:37:36 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: malta_intr.c,v 1.19.16.2 2010/02/06 02:59:04 matt Exp $ */
+/* $NetBSD: malta_intr.c,v 1.19.16.3 2010/02/15 07:37:36 matt Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.19.16.2 2010/02/06 02:59:04 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.19.16.3 2010/02/15 07:37:36 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -65,15 +65,28 @@
*/
const uint32_t ipl_sr_bits[_IPL_N] = {
[IPL_NONE] = 0,
+ [IPL_PREEMPT] = 0,
[IPL_SOFTCLOCK] =
MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
+ MIPS_SOFT_INT_MASK_0 |
+ MIPS_SOFT_INT_MASK_1,
[IPL_VM] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
+ MIPS_SOFT_INT_MASK_0 |
+ MIPS_SOFT_INT_MASK_1 |
MIPS_INT_MASK_0,
[IPL_SCHED] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
+ MIPS_SOFT_INT_MASK_0 |
+ MIPS_SOFT_INT_MASK_1 |
+ MIPS_INT_MASK_0 |
+ MIPS_INT_MASK_1 |
+ MIPS_INT_MASK_2 |
+ MIPS_INT_MASK_3 |
+ MIPS_INT_MASK_4 |
+ MIPS_INT_MASK_5,
+ [IPL_HIGH] =
+ MIPS_SOFT_INT_MASK_0 |
+ MIPS_SOFT_INT_MASK_1 |
MIPS_INT_MASK_0 |
MIPS_INT_MASK_1 |
MIPS_INT_MASK_2 |
@@ -249,9 +262,8 @@
}
void
-evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
{
- struct evbmips_intrhand *ih;
/* Check for error interrupts (SMI, GT64120) */
if (ipending & (MIPS_INT_MASK_1 | MIPS_INT_MASK_3)) {
@@ -267,15 +279,12 @@
* priority.
*/
if (ipending & MIPS_INT_MASK_0) {
+ struct evbmips_intrhand *ih;
/* All interrupts are gated through MIPS HW interrupt 0 */
malta_cpuintrs[0].cintr_count.ev_count++;
LIST_FOREACH(ih, &malta_cpuintrs[0].cintr_list, ih_q)
(*ih->ih_func)(ih->ih_arg);
- cause &= ~MIPS_INT_MASK_0;
}
-
- /* Re-enable anything that we have processed. */
- _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
}
/*
Index: src/sys/arch/mips/adm5120/adm5120_intr.c
diff -u src/sys/arch/mips/adm5120/adm5120_intr.c:1.3 src/sys/arch/mips/adm5120/adm5120_intr.c:1.3.18.1
--- src/sys/arch/mips/adm5120/adm5120_intr.c:1.3 Mon Apr 28 20:23:27 2008
+++ src/sys/arch/mips/adm5120/adm5120_intr.c Mon Feb 15 07:37:36 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: adm5120_intr.c,v 1.3 2008/04/28 20:23:27 martin Exp $ */
+/* $NetBSD: adm5120_intr.c,v 1.3.18.1 2010/02/15 07:37:36 matt Exp $ */
/*-
* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
@@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: adm5120_intr.c,v 1.3 2008/04/28 20:23:27 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: adm5120_intr.c,v 1.3.18.1 2010/02/15 07:37:36 matt Exp $");
#include "opt_ddb.h"
@@ -93,26 +93,19 @@
* given hardware interrupt priority level.
*/
const uint32_t ipl_sr_bits[_IPL_N] = {
- 0, /* 0: IPL_NONE */
- MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFTCLOCK */
- MIPS_SOFT_INT_MASK_0, /* 2: IPL_SOFTNET */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_0, /* 3: IPL_VM */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_0|
- MIPS_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_3|
- MIPS_INT_MASK_4|
- MIPS_INT_MASK_5, /* 4: IPL_{SCHED,HIGH} */
+ [IPL_NONE] = 0,
+ [IPL_PREEMPT] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK|MIPS_INT_MASK_0,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
};
#define NIRQS 32
-const char *adm5120_intrnames[NIRQS] = {
+const char * const adm5120_intrnames[NIRQS] = {
"timer", /* 0 */
"uart0", /* 1 */
"uart1", /* 2 */
@@ -161,7 +154,7 @@
};
struct adm5120_cpuintr adm5120_cpuintrs[NINTRS];
-const char *adm5120_cpuintrnames[NINTRS] = {
+const char * const adm5120_cpuintrnames[NINTRS] = {
"int 0 (irq)",
"int 1 (fiq)",
};
@@ -276,13 +269,12 @@
free(ih, M_DEVBUF);
}
void
-evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, uint32_t pc, uint32_t ipending)
{
struct evbmips_intrhand *ih;
- int level;
uint32_t irqmask, irqstat;
- for (level = NINTRS - 1; level >= 0; level--) {
+ for (int level = NINTRS - 1; level >= 0; level--) {
if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
continue;
@@ -299,11 +291,5 @@
(*ih->ih_func)(ih->ih_arg);
}
}
- cause &= ~(MIPS_INT_MASK_0 << level);
}
-
- /* Re-enable anything that we have processed. */
- _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
-
- return;
}
Index: src/sys/arch/mips/alchemy/au_icu.c
diff -u src/sys/arch/mips/alchemy/au_icu.c:1.23 src/sys/arch/mips/alchemy/au_icu.c:1.23.18.1
--- src/sys/arch/mips/alchemy/au_icu.c:1.23 Mon Apr 28 20:23:27 2008
+++ src/sys/arch/mips/alchemy/au_icu.c Mon Feb 15 07:37:36 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: au_icu.c,v 1.23 2008/04/28 20:23:27 martin Exp $ */
+/* $NetBSD: au_icu.c,v 1.23.18.1 2010/02/15 07:37:36 matt Exp $ */
/*-
* Copyright (c) 2006 Itronix Inc.
@@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.23 2008/04/28 20:23:27 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.23.18.1 2010/02/15 07:37:36 matt Exp $");
#include "opt_ddb.h"
@@ -313,7 +313,7 @@
}
void
-au_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+au_iointr(int ipl, vaddr_t pc, uint32_t ipending)
{
struct au_intrhand *ih;
int level;
@@ -372,11 +372,7 @@
}
}
}
- cause &= ~(MIPS_INT_MASK_0 << level);
}
-
- /* Re-enable anything that we have processed. */
- _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
}
/*
Index: src/sys/arch/mips/alchemy/include/auvar.h
diff -u src/sys/arch/mips/alchemy/include/auvar.h:1.9 src/sys/arch/mips/alchemy/include/auvar.h:1.9.64.1
--- src/sys/arch/mips/alchemy/include/auvar.h:1.9 Wed Feb 21 22:59:47 2007
+++ src/sys/arch/mips/alchemy/include/auvar.h Mon Feb 15 07:37:36 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: auvar.h,v 1.9 2007/02/21 22:59:47 thorpej Exp $ */
+/* $NetBSD: auvar.h,v 1.9.64.1 2010/02/15 07:37:36 matt Exp $ */
/*-
* Copyright (c) 2006 Itronix Inc.
@@ -104,7 +104,7 @@
void au_intr_disestablish(void *);
void au_intr_enable(int);
void au_intr_disable(int);
-void au_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
+void au_iointr(int, vaddr_t, uint32_t);
void au_cpureg_bus_mem_init(bus_space_tag_t, void *);
Index: src/sys/arch/mips/atheros/ar5312_intr.c
diff -u src/sys/arch/mips/atheros/ar5312_intr.c:1.6 src/sys/arch/mips/atheros/ar5312_intr.c:1.6.28.1
--- src/sys/arch/mips/atheros/ar5312_intr.c:1.6 Mon Jan 7 07:28:14 2008
+++ src/sys/arch/mips/atheros/ar5312_intr.c Mon Feb 15 07:37:36 2010
@@ -1,4 +1,4 @@
-/* $Id: ar5312_intr.c,v 1.6 2008/01/07 07:28:14 dyoung Exp $ */
+/* $Id: ar5312_intr.c,v 1.6.28.1 2010/02/15 07:37:36 matt Exp $ */
/*
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
* Copyright (c) 2006 Garrett D'Amore.
@@ -41,7 +41,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ar5312_intr.c,v 1.6 2008/01/07 07:28:14 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ar5312_intr.c,v 1.6.28.1 2010/02/15 07:37:36 matt Exp $");
#include <sys/param.h>
#include <sys/queue.h>
@@ -91,21 +91,19 @@
};
const uint32_t ipl_sr_bits[_IPL_N] = {
- 0, /* 0: IPL_NONE */
- MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFTCLOCK */
- MIPS_SOFT_INT_MASK_0, /* 2: IPL_SOFTNET */
-
- MIPS_SOFT_INT_MASK_0 |
- MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3, /* 3: IPL_VM */
-
- MIPS_INT_MASK, /* 4: IPL_{SCHED,HIGH} */
+ [IPL_NONE] = 0,
+ [IPL_PREEMPT] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
+ | MIPS_INT_MASK_1 | MIPS_INT_MASK_2 | MIPS_INT_MASK_3,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
};
-static const char *ar5312_cpuintrnames[NINTRS] = {
+static const char * const ar5312_cpuintrnames[NINTRS] = {
"int 2 (wlan0)",
"int 3 (enet0)",
"int 4 (enet1)",
@@ -113,7 +111,7 @@
"int 6 (misc)",
};
-static const char *ar5312_miscintrnames[NIRQS] = {
+static const char * const ar5312_miscintrnames[NIRQS] = {
"misc 0 (timer)",
"misc 1 (AHBproc error)",
"misc 2 (AHBdma error)",
@@ -280,24 +278,18 @@
}
void
-ar531x_cpuintr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+ar531x_cpuintr(int ipl, vaddr_t pc, uint32_t ipending)
{
- uint32_t mask;
- int index;
struct ar531x_intrhand *ih;
/* all others get normal handling */
- for (index = NINTRS - 1; index >= 0; index--) {
- mask = MIPS_INT_MASK_0 << index;
+ for (int index = NINTRS - 1; index >= 0; index--) {
+ uint32_t mask = MIPS_INT_MASK_0 << index;
if (ipending & mask) {
ar5312_cpuintrs[index].intr_count.ev_count++;
LIST_FOREACH(ih, &ar5312_cpuintrs[index].intr_l, ih_q)
(*ih->ih_func)(ih->ih_arg);
- cause &= ~mask;
}
}
-
- /* re-enable the stuff we processed */
- _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
}
Index: src/sys/arch/mips/atheros/ar5315_intr.c
diff -u src/sys/arch/mips/atheros/ar5315_intr.c:1.5 src/sys/arch/mips/atheros/ar5315_intr.c:1.5.28.1
--- src/sys/arch/mips/atheros/ar5315_intr.c:1.5 Mon Jan 7 07:12:06 2008
+++ src/sys/arch/mips/atheros/ar5315_intr.c Mon Feb 15 07:37:36 2010
@@ -1,4 +1,4 @@
-/* $Id: ar5315_intr.c,v 1.5 2008/01/07 07:12:06 dyoung Exp $ */
+/* $Id: ar5315_intr.c,v 1.5.28.1 2010/02/15 07:37:36 matt Exp $ */
/*
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
* Copyright (c) 2006 Garrett D'Amore.
@@ -41,7 +41,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ar5315_intr.c,v 1.5 2008/01/07 07:12:06 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ar5315_intr.c,v 1.5.28.1 2010/02/15 07:37:36 matt Exp $");
#include <sys/param.h>
#include <sys/queue.h>
@@ -89,26 +89,25 @@
};
const uint32_t ipl_sr_bits[_IPL_N] = {
- 0, /* 0: IPL_NONE */
- MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFTCLOCK */
- MIPS_SOFT_INT_MASK_0, /* 2: IPL_SOFTNET */
-
- MIPS_SOFT_INT_MASK_0 |
- MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2, /* 3: IPL_VM */
-
- MIPS_INT_MASK, /* 4: IPL_{SCHED,HIGH} */
+ [IPL_NONE] = 0,
+ [IPL_PREEMPT] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
+ | MIPS_INT_MASK_1 | MIPS_INT_MASK_2,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
};
-static const char *ar5315_cpuintrnames[NINTRS] = {
+static const char * const ar5315_cpuintrnames[NINTRS] = {
"int 2 (misc)",
"int 3 (wlan)",
"int 4 (enet)",
};
-static const char *ar5315_miscintrnames[NIRQS] = {
+static const char * const ar5315_miscintrnames[NIRQS] = {
"misc 0 (uart)",
"misc 1 (i2c)",
"misc 2 (spi)",
@@ -277,24 +276,18 @@
}
void
-ar531x_cpuintr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+ar531x_cpuintr(int ipl, vaddr_t pc, uint32_t ipending)
{
- uint32_t mask;
- int index;
struct ar531x_intrhand *ih;
/* all others get normal handling */
- for (index = NINTRS - 1; index >= 0; index--) {
- mask = MIPS_INT_MASK_0 << index;
+ for (int index = NINTRS - 1; index >= 0; index--) {
+ uint32_t mask = MIPS_INT_MASK_0 << index;
if (ipending & mask) {
ar5315_cpuintrs[index].intr_count.ev_count++;
LIST_FOREACH(ih, &ar5315_cpuintrs[index].intr_l, ih_q)
(*ih->ih_func)(ih->ih_arg);
- cause &= ~mask;
}
}
-
- /* re-enable the stuff we processed */
- _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
}
Index: src/sys/arch/mips/atheros/include/ar531xvar.h
diff -u src/sys/arch/mips/atheros/include/ar531xvar.h:1.5 src/sys/arch/mips/atheros/include/ar531xvar.h:1.5.74.1
--- src/sys/arch/mips/atheros/include/ar531xvar.h:1.5 Tue Sep 26 06:37:32 2006
+++ src/sys/arch/mips/atheros/include/ar531xvar.h Mon Feb 15 07:37:36 2010
@@ -1,4 +1,4 @@
-/* $Id: ar531xvar.h,v 1.5 2006/09/26 06:37:32 gdamore Exp $ */
+/* $Id: ar531xvar.h,v 1.5.74.1 2010/02/15 07:37:36 matt Exp $ */
/*
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
* Copyright (c) 2006 Garrett D'Amore.
@@ -66,7 +66,7 @@
void *ar531x_misc_intr_establish(int, int (*)(void *), void *);
void ar531x_misc_intr_disestablish(void *);
-void ar531x_cpuintr(uint32_t, uint32_t, uint32_t, uint32_t);
+void ar531x_cpuintr(int, vaddr_t, uint32_t);
/*
Index: src/sys/arch/mips/rmi/rmixl_intr.c
diff -u src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.10 src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.11
--- src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.10 Sat Feb 6 03:10:14 2010
+++ src/sys/arch/mips/rmi/rmixl_intr.c Mon Feb 15 07:37:36 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_intr.c,v 1.1.2.10 2010/02/06 03:10:14 cliff Exp $ */
+/* $NetBSD: rmixl_intr.c,v 1.1.2.11 2010/02/15 07:37:36 matt Exp $ */
/*-
* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
@@ -64,7 +64,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.10 2010/02/06 03:10:14 cliff Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.11 2010/02/15 07:37:36 matt Exp $");
#include "opt_ddb.h"
@@ -105,21 +105,13 @@
*/
#define _SR_BITS_DFLT (MIPS_INT_MASK_2|MIPS_INT_MASK_3|MIPS_INT_MASK_4)
const uint32_t ipl_sr_bits[_IPL_N] = {
- [IPL_NONE] = _SR_BITS_DFLT,
- [IPL_SOFTCLOCK] =
- _SR_BITS_DFLT
- | MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- _SR_BITS_DFLT
- | MIPS_SOFT_INT_MASK_0
- | MIPS_SOFT_INT_MASK_1,
- [IPL_VM] =
- _SR_BITS_DFLT
- | MIPS_SOFT_INT_MASK_0
- | MIPS_SOFT_INT_MASK_1
- | MIPS_INT_MASK_0,
- [IPL_SCHED] =
- MIPS_INT_MASK,
+ [IPL_NONE] = _SR_BITS_DFLT,
+ [IPL_PREEMPT] = _SR_BITS_DFLT,
+ [IPL_SOFTCLOCK] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK,
+ [IPL_VM] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
};
/*
@@ -650,7 +642,7 @@
}
void
-evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
{
struct evbmips_intrhand *ih;
struct rmixl_intrvec *ivp;
@@ -659,8 +651,8 @@
#ifdef IOINTR_DEBUG
uint64_t eimr;
- printf("%s: status %#x, cause %#x, pc %#x, ipending %#x\n",
- __func__, status, cause, pc, ipending);
+ printf("%s: ipl %d, pc %#x, ipending %#x\n",
+ __func__, ipl, pc, ipending);
asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr));
asm volatile("dmfc0 %0, $9, 7;" : "=r"(eimr));
@@ -693,13 +685,7 @@
rmixl_irqtab[ih->ih_irq].irq_count.ev_count++;
}
}
-
- cause &= ~(MIPS_SOFT_INT_MASK_0 << vec);
}
-
-
- /* Re-enable anything that we have processed. */
- _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
}
#ifdef DEBUG
