Module Name: src Committed By: matt Date: Tue Feb 23 20:24:37 UTC 2010
Modified Files: src/sys/arch/evbmips/malta [matt-nb5-mips64]: malta_intr.c src/sys/arch/mips/include [matt-nb5-mips64]: intr.h src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c src/sys/arch/sbmips/include [matt-nb5-mips64]: intr.h systemsw.h src/sys/arch/sbmips/sbmips [matt-nb5-mips64]: autoconf.c sb1250_icu.c systemsw.c Log Message: Instead of a read-only ipl_sr_bits, define a ipl_sr_map struct and fill that in the interrupt init routine. There's a default ipl_sr_map will operate correctly, but isn't performant. To generate a diff of this commit: cvs rdiff -u -r1.19.16.4 -r1.19.16.5 src/sys/arch/evbmips/malta/malta_intr.c cvs rdiff -u -r1.3.96.4 -r1.3.96.5 src/sys/arch/mips/include/intr.h cvs rdiff -u -r1.1.2.12 -r1.1.2.13 src/sys/arch/mips/rmi/rmixl_intr.c cvs rdiff -u -r1.9 -r1.9.36.1 src/sys/arch/sbmips/include/intr.h cvs rdiff -u -r1.7.28.2 -r1.7.28.3 src/sys/arch/sbmips/include/systemsw.h cvs rdiff -u -r1.6 -r1.6.96.1 src/sys/arch/sbmips/sbmips/autoconf.c cvs rdiff -u -r1.9.36.3 -r1.9.36.4 src/sys/arch/sbmips/sbmips/sb1250_icu.c cvs rdiff -u -r1.14.28.3 -r1.14.28.4 src/sys/arch/sbmips/sbmips/systemsw.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/evbmips/malta/malta_intr.c diff -u src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.4 src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.5 --- src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.4 Tue Feb 16 08:13:57 2010 +++ src/sys/arch/evbmips/malta/malta_intr.c Tue Feb 23 20:24:37 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: malta_intr.c,v 1.19.16.4 2010/02/16 08:13:57 matt Exp $ */ +/* $NetBSD: malta_intr.c,v 1.19.16.5 2010/02/23 20:24:37 matt Exp $ */ /* * Copyright 2001, 2002 Wasabi Systems, Inc. @@ -40,7 +40,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.19.16.4 2010/02/16 08:13:57 matt Exp $"); +__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.19.16.5 2010/02/23 20:24:37 matt Exp $"); #include <sys/param.h> #include <sys/device.h> @@ -63,13 +63,15 @@ * This is a mask of bits to clear in the SR when we go to a * given hardware interrupt priority level. */ -const uint32_t ipl_sr_bits[_IPL_N] = { +static const struct ipl_sr_map malta_ipl_sr_map = { + .sr_bits = { [IPL_NONE] = 0, [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, [IPL_SOFTNET] = MIPS_SOFT_INT_MASK, [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0, [IPL_SCHED] = MIPS_INT_MASK, [IPL_HIGH] = MIPS_INT_MASK, + }, }; struct malta_cpuintr { @@ -102,10 +104,11 @@ void evbmips_intr_init(void) { - struct malta_config *mcp = &malta_configuration; - int i; + struct malta_config * const mcp = &malta_configuration; + + ipl_sr_map = malta_ipl_sr_map; - for (i = 0; i < NINTRS; i++) { + for (size_t i = 0; i < NINTRS; i++) { LIST_INIT(&malta_cpuintrs[i].cintr_list); evcnt_attach_dynamic(&malta_cpuintrs[i].cintr_count, EVCNT_TYPE_INTR, NULL, "mips", malta_cpuintrnames[i]); Index: src/sys/arch/mips/include/intr.h diff -u src/sys/arch/mips/include/intr.h:1.3.96.4 src/sys/arch/mips/include/intr.h:1.3.96.5 --- src/sys/arch/mips/include/intr.h:1.3.96.4 Mon Feb 22 20:08:58 2010 +++ src/sys/arch/mips/include/intr.h Tue Feb 23 20:24:36 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: intr.h,v 1.3.96.4 2010/02/22 20:08:58 matt Exp $ */ +/* $NetBSD: intr.h,v 1.3.96.5 2010/02/23 20:24:36 matt Exp $ */ /*- * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc. * All rights reserved. @@ -85,6 +85,10 @@ ipl_t _spl; } ipl_cookie_t; +struct ipl_sr_map { + uint32_t sr_bits[_IPL_N]; +}; + #ifdef _KERNEL #ifdef MULTIPROCESSOR #define __HAVE_PREEMPTION @@ -92,7 +96,7 @@ #endif extern struct splsw mips_splsw; -extern const uint32_t ipl_sr_bits[_IPL_N]; +extern struct ipl_sr_map ipl_sr_map; static inline int splhigh(void) Index: src/sys/arch/mips/rmi/rmixl_intr.c diff -u src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.12 src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.13 --- src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.12 Tue Feb 16 08:13:57 2010 +++ src/sys/arch/mips/rmi/rmixl_intr.c Tue Feb 23 20:24:37 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: rmixl_intr.c,v 1.1.2.12 2010/02/16 08:13:57 matt Exp $ */ +/* $NetBSD: rmixl_intr.c,v 1.1.2.13 2010/02/23 20:24:37 matt Exp $ */ /*- * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. @@ -64,7 +64,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.12 2010/02/16 08:13:57 matt Exp $"); +__KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.13 2010/02/23 20:24:37 matt Exp $"); #include "opt_ddb.h" @@ -104,13 +104,15 @@ * _SR_BITS_DFLT bits are to be always clear (disabled) */ #define _SR_BITS_DFLT (MIPS_INT_MASK_2|MIPS_INT_MASK_3|MIPS_INT_MASK_4) -const uint32_t ipl_sr_bits[_IPL_N] = { - [IPL_NONE] = _SR_BITS_DFLT, - [IPL_SOFTCLOCK] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK_0, - [IPL_SOFTNET] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK, - [IPL_VM] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0, - [IPL_SCHED] = MIPS_INT_MASK, - [IPL_HIGH] = MIPS_INT_MASK, +static const struct ipl_sr_map rmixl_ipl_sr_map = { + .sr_bits = { + [IPL_NONE] = _SR_BITS_DFLT, + [IPL_SOFTCLOCK] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK_0, + [IPL_SOFTNET] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK, + [IPL_VM] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0, + [IPL_SCHED] = MIPS_INT_MASK, + [IPL_HIGH] = MIPS_INT_MASK, + }, }; /* @@ -320,6 +322,7 @@ int i; KASSERT(cpu_rmixls(mips_options.mips_cpu)); + ipl_sr_map = rmixl_ipl_sr_map; #ifdef DIAGNOSTIC if (evbmips_intr_init_done != 0) Index: src/sys/arch/sbmips/include/intr.h diff -u src/sys/arch/sbmips/include/intr.h:1.9 src/sys/arch/sbmips/include/intr.h:1.9.36.1 --- src/sys/arch/sbmips/include/intr.h:1.9 Mon Dec 3 15:34:16 2007 +++ src/sys/arch/sbmips/include/intr.h Tue Feb 23 20:24:37 2010 @@ -1,83 +1,38 @@ -/* $NetBSD: intr.h,v 1.9 2007/12/03 15:34:16 ad Exp $ */ +/* $NetBSD: intr.h,v 1.9.36.1 2010/02/23 20:24:37 matt Exp $ */ -/* - * Copyright 2000, 2001 - * Broadcom Corporation. All rights reserved. +/*- + * Copyright (c) 2010 The NetBSD Foundation, Inc. + * All rights reserved. * - * This software is furnished under license and may be used and copied only - * in accordance with the following terms and conditions. Subject to these - * conditions, you may download, copy, install, use, modify and distribute - * modified or unmodified copies of this software in source and/or binary - * form. No title or ownership is transferred hereby. + * This code is derived from software contributed to The NetBSD Foundation + * by Matt Thomas <m...@3am-software.com>. * - * 1) Any source code used, modified or distributed must reproduce and - * retain this copyright notice and list of conditions as they appear in - * the source file. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 2) No right is granted to use any trade name, trademark, or logo of - * Broadcom Corporation. The "Broadcom Corporation" name may not be - * used to endorse or promote products derived from this software - * without the prior written permission of Broadcom Corporation. - * - * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR - * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE - * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE - * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _SBMIPS_INTR_H_ #define _SBMIPS_INTR_H_ +#include <mips/intr.h> #include <machine/systemsw.h> -#include <mips/locore.h> - -/* Interrupt levels */ -#define IPL_NONE 0 -#define IPL_SOFTCLOCK 1 /* clock software interrupts */ -#define IPL_SOFTBIO 1 /* bio software interrupts */ -#define IPL_SOFTNET 2 /* network software interrupts */ -#define IPL_SOFTSERIAL 2 /* serial software interrupts */ -#define IPL_VM 3 -#define IPL_SCHED 4 -#define IPL_HIGH 5 - -#define _NIPL 6 - -#define _IMR_SOFT (MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1) -#define _IMR_VM (_IMR_SOFT | MIPS_INT_MASK_0) -#define _IMR_SCHED (_IMR_VM | MIPS_INT_MASK_1 | MIPS_INT_MASK_5) -#define _IMR_HIGH (MIPS_INT_MASK) - -#define splsoftclock() _splraise(MIPS_SOFT_INT_MASK_0) -#define splsoftbio() _splraise(MIPS_SOFT_INT_MASK_0) -#define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_1) -#define splsoftserial() _splraise(MIPS_SOFT_INT_MASK_1) -#define splvm() _splraise(_IMR_VM) -#define splsched() _splraise(_IMR_SCHED) -#define splhigh() _splraise(_IMR_HIGH) - -#define spl0() _spllower(0) -#define splx(s) _splset(s) - -typedef int ipl_t; -typedef struct { - ipl_t _spl; -} ipl_cookie_t; - -ipl_cookie_t makeiplcookie(ipl_t); - -static inline int -splraiseipl(ipl_cookie_t icookie) -{ - - return _splraise(icookie._spl); -} #endif /* _SBMIPS_INTR_H_ */ Index: src/sys/arch/sbmips/include/systemsw.h diff -u src/sys/arch/sbmips/include/systemsw.h:1.7.28.2 src/sys/arch/sbmips/include/systemsw.h:1.7.28.3 --- src/sys/arch/sbmips/include/systemsw.h:1.7.28.2 Thu Jan 21 04:09:18 2010 +++ src/sys/arch/sbmips/include/systemsw.h Tue Feb 23 20:24:37 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: systemsw.h,v 1.7.28.2 2010/01/21 04:09:18 matt Exp $ */ +/* $NetBSD: systemsw.h,v 1.7.28.3 2010/02/23 20:24:37 matt Exp $ */ /* * Copyright 2000, 2001 @@ -39,7 +39,7 @@ struct systemsw { /* ordered to match likely locality. */ - void (*s_cpu_intr)(uint32_t, uint32_t, vaddr_t, uint32_t); + void (*s_cpu_intr)(int, vaddr_t, uint32_t); void *s_clock_arg; void (*s_clock_init)(void *); Index: src/sys/arch/sbmips/sbmips/autoconf.c diff -u src/sys/arch/sbmips/sbmips/autoconf.c:1.6 src/sys/arch/sbmips/sbmips/autoconf.c:1.6.96.1 --- src/sys/arch/sbmips/sbmips/autoconf.c:1.6 Sun Dec 11 12:18:51 2005 +++ src/sys/arch/sbmips/sbmips/autoconf.c Tue Feb 23 20:24:37 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: autoconf.c,v 1.6 2005/12/11 12:18:51 christos Exp $ */ +/* $NetBSD: autoconf.c,v 1.6.96.1 2010/02/23 20:24:37 matt Exp $ */ /* * Copyright 2000, 2001 @@ -33,7 +33,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.6 2005/12/11 12:18:51 christos Exp $"); +__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.6.96.1 2010/02/23 20:24:37 matt Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -51,7 +51,7 @@ if (config_rootfound("zbbus", NULL) == NULL) panic("no zbbus found"); - _splnone(); + spl0(); } void Index: src/sys/arch/sbmips/sbmips/sb1250_icu.c diff -u src/sys/arch/sbmips/sbmips/sb1250_icu.c:1.9.36.3 src/sys/arch/sbmips/sbmips/sb1250_icu.c:1.9.36.4 --- src/sys/arch/sbmips/sbmips/sb1250_icu.c:1.9.36.3 Fri Feb 5 07:39:53 2010 +++ src/sys/arch/sbmips/sbmips/sb1250_icu.c Tue Feb 23 20:24:37 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: sb1250_icu.c,v 1.9.36.3 2010/02/05 07:39:53 matt Exp $ */ +/* $NetBSD: sb1250_icu.c,v 1.9.36.4 2010/02/23 20:24:37 matt Exp $ */ /* * Copyright 2000, 2001 @@ -33,7 +33,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: sb1250_icu.c,v 1.9.36.3 2010/02/05 07:39:53 matt Exp $"); +__KERNEL_RCSID(0, "$NetBSD: sb1250_icu.c,v 1.9.36.4 2010/02/23 20:24:37 matt Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -48,6 +48,24 @@ /* XXX for now, this copes with one cpu only, and assumes it's CPU 0 */ +static const struct ipl_sr_map sb1250_ipl_sr_map = { + .sr_bits = { + [IPL_NONE] = 0, + [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, + [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0, + [IPL_SOFTNET] = MIPS_SOFT_INT_MASK, + [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK, + [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0, +#if IPL_SCHED == IPL_HIGH + [IPL_SCHED] = MIPS_INT_MASK, +#else + [IPL_SCHED] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0 + | MIPS_INT_MASK_1 | MIPS_INT_MASK_5, +#endif + [IPL_HIGH] = MIPS_INT_MASK, + }, +}; + /* imr values corresponding to each pin */ uint64_t ints_for_line[6]; uint64_t imr_all; @@ -72,7 +90,7 @@ #define READ_REG(rp) (mips3_ld((volatile uint64_t *)(rp))) #define WRITE_REG(rp, val) (mips3_sd((volatile uint64_t *)(rp), (val))) -static void sb1250_cpu_intr(uint32_t, uint32_t, vaddr_t, uint32_t); +static void sb1250_cpu_intr(int, vaddr_t, uint32_t); static void *sb1250_intr_establish(u_int, u_int, void (*fun)(void *, uint32_t, vaddr_t), void *); @@ -82,6 +100,8 @@ int i; char *name; + ipl_sr_map = sb1250_ipl_sr_map; + /* zero out the list of used interrupts/lines */ memset(ints_for_line, 0, sizeof ints_for_line); imr_all = 0xffffffffffffffffULL; @@ -103,52 +123,43 @@ } static void -sb1250_cpu_intr(uint32_t status, uint32_t cause, vaddr_t pc, uint32_t ipending) +sb1250_cpu_intr(int ppl, vaddr_t pc, uint32_t status) { int i, j; + int ipl; uint64_t sstatus; uint32_t cycles; - struct cpu_info *ci; + uint32_t pending; - ci = curcpu(); - ci->ci_idepth++; uvmexp.intrs++; - /* XXX do something if 5? */ - if (ipending & (MIPS_INT_MASK_0 << 5)) { - cycles = mips3_cp0_count_read(); - mips3_cp0_compare_write(cycles - 1); - /* just leave the bugger disabled */ - } + while (ppl < (ipl = splintr(&pending))) { + splx(ipl); - for (i = 4; i >= 0; i--) { - if (ipending & (MIPS_INT_MASK_0 << i)) { + /* XXX do something if 5? */ + if (pending & MIPS_INT_MASK_5) { + cycles = mips3_cp0_count_read(); + mips3_cp0_compare_write(cycles - 1); + /* just leave the bugger disabled */ + } - sstatus = READ_REG(SB1250_I_IMR_SSTATUS); - sstatus &= ints_for_line[i]; - for (j = 0; sstatus != 0 && j < 64; j++) { - if (sstatus & ((uint64_t)1 << j)) { - struct sb1250_ihand *ihp = - &sb1250_ihands[j]; - (*ihp->fun)(ihp->arg, status, pc); - sstatus &= ~((uint64_t)1 << j); - ihp->count.ev_count++; + for (i = 4; i >= 0; i--) { + if (pending & (MIPS_INT_MASK_0 << i)) { + sstatus = READ_REG(SB1250_I_IMR_SSTATUS); + sstatus &= ints_for_line[i]; + for (j = 0; sstatus != 0 && j < 64; j++) { + if (sstatus & ((uint64_t)1 << j)) { + struct sb1250_ihand *ihp = + &sb1250_ihands[j]; + (*ihp->fun)(ihp->arg, status, pc); + sstatus &= ~((uint64_t)1 << j); + ihp->count.ev_count++; + } } } } - cause &= ~(MIPS_INT_MASK_0 << i); + (void) splhigh(); } - ci->ci_idepth--; - - /* Re-enable anything that we have processed. */ - _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK)); - -#ifdef __HAVE_FAST_SOFTINTS - ipending &= MIPS_SOFT_INT_MASK; - if (ipending == 0) - return; - softint_process(ipending); -#endif } static void * @@ -161,7 +172,7 @@ if (num >= 64) /* XXX */ panic("invalid interrupt number (0x%x)", num); - if (ipl >= _NIPL) + if (ipl >= _IPL_N) panic("invalid ipl (0x%x)", ipl); if (sb1250_ihands[num].fun != NULL) @@ -200,19 +211,3 @@ return (&sb1250_ihands[num]); } - -static const int ipl2spl_table[] = { - [IPL_NONE] = 0, - [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, - [IPL_SOFTNET] = MIPS_SOFT_INT_MASK_1, - [IPL_VM] = _IMR_VM, - [IPL_SCHED] = _IMR_SCHED, - [IPL_HIGH] = _IMR_HIGH, -}; - -ipl_cookie_t -makeiplcookie(ipl_t ipl) -{ - - return (ipl_cookie_t){._spl = ipl2spl_table[ipl]}; -} Index: src/sys/arch/sbmips/sbmips/systemsw.c diff -u src/sys/arch/sbmips/sbmips/systemsw.c:1.14.28.3 src/sys/arch/sbmips/sbmips/systemsw.c:1.14.28.4 --- src/sys/arch/sbmips/sbmips/systemsw.c:1.14.28.3 Thu Jan 21 04:09:59 2010 +++ src/sys/arch/sbmips/sbmips/systemsw.c Tue Feb 23 20:24:37 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: systemsw.c,v 1.14.28.3 2010/01/21 04:09:59 matt Exp $ */ +/* $NetBSD: systemsw.c,v 1.14.28.4 2010/02/23 20:24:37 matt Exp $ */ /* * Copyright 2000, 2001 @@ -33,7 +33,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: systemsw.c,v 1.14.28.3 2010/01/21 04:09:59 matt Exp $"); +__KERNEL_RCSID(0, "$NetBSD: systemsw.c,v 1.14.28.4 2010/02/23 20:24:37 matt Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -49,7 +49,7 @@ /* trivial functions for function switch */ static void clock_init_triv(void *); -static void cpu_intr_triv(uint32_t, uint32_t, vaddr_t, uint32_t); +static void cpu_intr_triv(int, vaddr_t, uint32_t); /* system function switch */ struct systemsw systemsw = { @@ -77,17 +77,17 @@ } static void -cpu_intr_triv(uint32_t status, uint32_t cause, vaddr_t pc, uint32_t ipending) +cpu_intr_triv(int ppl, vaddr_t pc, uint32_t status) { panic("cpu_intr_triv"); } void -cpu_intr(uint32_t status, uint32_t cause, vaddr_t pc, uint32_t ipending) +cpu_intr(int ppl, vaddr_t pc, uint32_t status) { - (*systemsw.s_cpu_intr)(status, cause, pc, ipending); + (*systemsw.s_cpu_intr)(ppl, pc, status); } static void @@ -119,7 +119,7 @@ /* * Now we can enable all interrupts including hardclock(9). */ - _splnone(); + spl0(); } void