Module Name: src
Committed By: matt
Date: Tue Feb 16 08:13:58 UTC 2010
Modified Files:
src/sys/arch/evbmips/malta [matt-nb5-mips64]: malta_intr.c
src/sys/arch/mips/adm5120 [matt-nb5-mips64]: adm5120_intr.c
src/sys/arch/mips/atheros [matt-nb5-mips64]: ar5312_intr.c
ar5315_intr.c
src/sys/arch/mips/include [matt-nb5-mips64]: cpu.h intr.h
src/sys/arch/mips/mips [matt-nb5-mips64]: genassym.cf mipsX_subr.S
mips_machdep.c mips_softint.c
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c
Log Message:
Add __HAVE_PREEMPTION support for NetBSD/mips. Kill IPL_PREEMPT since it
isn't needed.
To generate a diff of this commit:
cvs rdiff -u -r1.19.16.3 -r1.19.16.4 src/sys/arch/evbmips/malta/malta_intr.c
cvs rdiff -u -r1.3.18.1 -r1.3.18.2 src/sys/arch/mips/adm5120/adm5120_intr.c
cvs rdiff -u -r1.6.28.1 -r1.6.28.2 src/sys/arch/mips/atheros/ar5312_intr.c
cvs rdiff -u -r1.5.28.1 -r1.5.28.2 src/sys/arch/mips/atheros/ar5315_intr.c
cvs rdiff -u -r1.90.16.19 -r1.90.16.20 src/sys/arch/mips/include/cpu.h
cvs rdiff -u -r1.3.96.2 -r1.3.96.3 src/sys/arch/mips/include/intr.h
cvs rdiff -u -r1.44.12.16 -r1.44.12.17 src/sys/arch/mips/mips/genassym.cf
cvs rdiff -u -r1.26.36.1.2.23 -r1.26.36.1.2.24 \
src/sys/arch/mips/mips/mipsX_subr.S
cvs rdiff -u -r1.205.4.1.2.1.2.33 -r1.205.4.1.2.1.2.34 \
src/sys/arch/mips/mips/mips_machdep.c
cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/mips/mips_softint.c
cvs rdiff -u -r1.1.2.11 -r1.1.2.12 src/sys/arch/mips/rmi/rmixl_intr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/malta/malta_intr.c
diff -u src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.3 src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.4
--- src/sys/arch/evbmips/malta/malta_intr.c:1.19.16.3 Mon Feb 15 07:37:36 2010
+++ src/sys/arch/evbmips/malta/malta_intr.c Tue Feb 16 08:13:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: malta_intr.c,v 1.19.16.3 2010/02/15 07:37:36 matt Exp $ */
+/* $NetBSD: malta_intr.c,v 1.19.16.4 2010/02/16 08:13:57 matt Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.19.16.3 2010/02/15 07:37:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.19.16.4 2010/02/16 08:13:57 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -64,35 +64,12 @@
* given hardware interrupt priority level.
*/
const uint32_t ipl_sr_bits[_IPL_N] = {
- [IPL_NONE] = 0,
- [IPL_PREEMPT] = 0,
- [IPL_SOFTCLOCK] =
- MIPS_SOFT_INT_MASK_0,
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 |
- MIPS_SOFT_INT_MASK_1,
- [IPL_VM] =
- MIPS_SOFT_INT_MASK_0 |
- MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0,
- [IPL_SCHED] =
- MIPS_SOFT_INT_MASK_0 |
- MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3 |
- MIPS_INT_MASK_4 |
- MIPS_INT_MASK_5,
- [IPL_HIGH] =
- MIPS_SOFT_INT_MASK_0 |
- MIPS_SOFT_INT_MASK_1 |
- MIPS_INT_MASK_0 |
- MIPS_INT_MASK_1 |
- MIPS_INT_MASK_2 |
- MIPS_INT_MASK_3 |
- MIPS_INT_MASK_4 |
- MIPS_INT_MASK_5,
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
};
struct malta_cpuintr {
Index: src/sys/arch/mips/adm5120/adm5120_intr.c
diff -u src/sys/arch/mips/adm5120/adm5120_intr.c:1.3.18.1 src/sys/arch/mips/adm5120/adm5120_intr.c:1.3.18.2
--- src/sys/arch/mips/adm5120/adm5120_intr.c:1.3.18.1 Mon Feb 15 07:37:36 2010
+++ src/sys/arch/mips/adm5120/adm5120_intr.c Tue Feb 16 08:13:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: adm5120_intr.c,v 1.3.18.1 2010/02/15 07:37:36 matt Exp $ */
+/* $NetBSD: adm5120_intr.c,v 1.3.18.2 2010/02/16 08:13:57 matt Exp $ */
/*-
* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
@@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: adm5120_intr.c,v 1.3.18.1 2010/02/15 07:37:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: adm5120_intr.c,v 1.3.18.2 2010/02/16 08:13:57 matt Exp $");
#include "opt_ddb.h"
@@ -94,7 +94,6 @@
*/
const uint32_t ipl_sr_bits[_IPL_N] = {
[IPL_NONE] = 0,
- [IPL_PREEMPT] = 0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
Index: src/sys/arch/mips/atheros/ar5312_intr.c
diff -u src/sys/arch/mips/atheros/ar5312_intr.c:1.6.28.1 src/sys/arch/mips/atheros/ar5312_intr.c:1.6.28.2
--- src/sys/arch/mips/atheros/ar5312_intr.c:1.6.28.1 Mon Feb 15 07:37:36 2010
+++ src/sys/arch/mips/atheros/ar5312_intr.c Tue Feb 16 08:13:57 2010
@@ -1,4 +1,4 @@
-/* $Id: ar5312_intr.c,v 1.6.28.1 2010/02/15 07:37:36 matt Exp $ */
+/* $Id: ar5312_intr.c,v 1.6.28.2 2010/02/16 08:13:57 matt Exp $ */
/*
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
* Copyright (c) 2006 Garrett D'Amore.
@@ -41,7 +41,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ar5312_intr.c,v 1.6.28.1 2010/02/15 07:37:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ar5312_intr.c,v 1.6.28.2 2010/02/16 08:13:57 matt Exp $");
#include <sys/param.h>
#include <sys/queue.h>
@@ -92,7 +92,6 @@
const uint32_t ipl_sr_bits[_IPL_N] = {
[IPL_NONE] = 0,
- [IPL_PREEMPT] = 0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
Index: src/sys/arch/mips/atheros/ar5315_intr.c
diff -u src/sys/arch/mips/atheros/ar5315_intr.c:1.5.28.1 src/sys/arch/mips/atheros/ar5315_intr.c:1.5.28.2
--- src/sys/arch/mips/atheros/ar5315_intr.c:1.5.28.1 Mon Feb 15 07:37:36 2010
+++ src/sys/arch/mips/atheros/ar5315_intr.c Tue Feb 16 08:13:57 2010
@@ -1,4 +1,4 @@
-/* $Id: ar5315_intr.c,v 1.5.28.1 2010/02/15 07:37:36 matt Exp $ */
+/* $Id: ar5315_intr.c,v 1.5.28.2 2010/02/16 08:13:57 matt Exp $ */
/*
* Copyright (c) 2006 Urbana-Champaign Independent Media Center.
* Copyright (c) 2006 Garrett D'Amore.
@@ -41,7 +41,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ar5315_intr.c,v 1.5.28.1 2010/02/15 07:37:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ar5315_intr.c,v 1.5.28.2 2010/02/16 08:13:57 matt Exp $");
#include <sys/param.h>
#include <sys/queue.h>
@@ -90,7 +90,6 @@
const uint32_t ipl_sr_bits[_IPL_N] = {
[IPL_NONE] = 0,
- [IPL_PREEMPT] = 0,
[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
Index: src/sys/arch/mips/include/cpu.h
diff -u src/sys/arch/mips/include/cpu.h:1.90.16.19 src/sys/arch/mips/include/cpu.h:1.90.16.20
--- src/sys/arch/mips/include/cpu.h:1.90.16.19 Mon Feb 15 07:36:03 2010
+++ src/sys/arch/mips/include/cpu.h Tue Feb 16 08:13:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.90.16.19 2010/02/15 07:36:03 matt Exp $ */
+/* $NetBSD: cpu.h,v 1.90.16.20 2010/02/16 08:13:57 matt Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -429,44 +429,30 @@
#endif
/*
- * This is used during profiling to integrate system time. It can safely
- * assume that the process is resident.
+ * Misc prototypes and variable declarations.
*/
-#define PROC_PC(p) \
- (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */
+struct lwp;
+struct user;
/*
* Preempt the current process if in interrupt from user mode,
* or after the current trap/syscall if in system mode.
*/
void cpu_need_resched(struct cpu_info *, int);
-
-/*
- * Give a profiling tick to the current process when the user profiling
- * buffer pages are invalid. On the MIPS, request an ast to send us
- * through trap, marking the proc as needing a profiling tick.
- */
-#define cpu_need_proftick(l) \
-do { \
- (l)->l_pflag |= LP_OWEUPC; \
- aston(l); \
-} while (/*CONSTCOND*/0)
-
/*
* Notify the current lwp (l) that it has a signal pending,
* process as soon as possible.
*/
-#define cpu_signotify(l) aston(l)
-
-#define aston(l) ((l)->l_md.md_astpending = 1)
+void cpu_signotify(struct lwp *);
/*
- * Misc prototypes and variable declarations.
+ * Give a profiling tick to the current process when the user profiling
+ * buffer pages are invalid. On the MIPS, request an ast to send us
+ * through trap, marking the proc as needing a profiling tick.
*/
-struct lwp;
-struct user;
+void cpu_need_proftick(struct lwp *);
+void cpu_set_curpri(int);
-extern struct segtab *segbase; /* current segtab base */
extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */
/* copy.S */
Index: src/sys/arch/mips/include/intr.h
diff -u src/sys/arch/mips/include/intr.h:1.3.96.2 src/sys/arch/mips/include/intr.h:1.3.96.3
--- src/sys/arch/mips/include/intr.h:1.3.96.2 Mon Feb 15 07:36:03 2010
+++ src/sys/arch/mips/include/intr.h Tue Feb 16 08:13:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.3.96.2 2010/02/15 07:36:03 matt Exp $ */
+/* $NetBSD: intr.h,v 1.3.96.3 2010/02/16 08:13:57 matt Exp $ */
/*-
* Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -36,12 +36,7 @@
*/
#define IPL_NONE 0
-#ifdef __HAVE_PREEMPTION
-#define IPL_PREEMPT (IPL_NONE+1)
-#else
-#define IPL_PREEMPT IPL_NONE
-#endif
-#define IPL_SOFTCLOCK (IPL_PREEMPT+1)
+#define IPL_SOFTCLOCK (IPL_NONE+1)
#define IPL_SOFTBIO (IPL_SOFTCLOCK) /* shares SWINT with softclock */
#define IPL_SOFTNET (IPL_SOFTBIO+1)
#define IPL_SOFTSERIAL (IPL_SOFTNET) /* shares SWINT with softnet */
@@ -84,6 +79,11 @@
} ipl_cookie_t;
#ifdef _KERNEL
+#ifdef MULTIPROCESSOR
+#define __HAVE_PREEMPTION
+#define SOFTINT_KPREEMPT (SOFTINT_COUNT+0)
+#endif
+
extern struct splsw mips_splsw;
extern const uint32_t ipl_sr_bits[_IPL_N];
Index: src/sys/arch/mips/mips/genassym.cf
diff -u src/sys/arch/mips/mips/genassym.cf:1.44.12.16 src/sys/arch/mips/mips/genassym.cf:1.44.12.17
--- src/sys/arch/mips/mips/genassym.cf:1.44.12.16 Mon Feb 15 07:36:03 2010
+++ src/sys/arch/mips/mips/genassym.cf Tue Feb 16 08:13:57 2010
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.44.12.16 2010/02/15 07:36:03 matt Exp $
+# $NetBSD: genassym.cf,v 1.44.12.17 2010/02/16 08:13:57 matt Exp $
#
# Copyright (c) 1992, 1993
# The Regents of the University of California. All rights reserved.
@@ -79,10 +79,10 @@
include <sys/mbuf.h>
include <sys/user.h>
include <sys/mutex.h>
+include <sys/cpu.h>
include <uvm/uvm.h>
-include <mips/cpu.h>
include <mips/cache.h>
include <mips/regnum.h>
include <mips/vmparam.h>
@@ -290,10 +290,6 @@
define CPU_INFO_MTX_OLDSPL offsetof(struct cpu_info, ci_mtx_oldspl)
define IPL_NONE IPL_NONE
-ifdef __HAVE_PREEMPTION
-define __HAVE_PREEMPTION 1
-define IPL_PREEMPT IPL_PREEMPT
-endif
define IPL_SOFTCLOCK IPL_SOFTCLOCK
define IPL_SOFTBIO IPL_SOFTBIO
define IPL_SOFTNET IPL_SOFTNET
@@ -302,6 +298,12 @@
define IPL_SCHED IPL_SCHED
define IPL_HIGH IPL_HIGH
+ifdef __HAVE_PREEMPTION
+define __HAVE_PREEMPTION 1
+define CPU_INFO_SOFTINTS offsetof(struct cpu_info, ci_softints)
+define RESCHED_KPREEMPT RESCHED_KPREEMPT
+define SOFTINT_KPREEMPT SOFTINT_KPREEMPT
+endif
define TLBMASK_HI offsetof(struct tlbmask, tlb_hi)
define TLBMASK_LO0 offsetof(struct tlbmask, tlb_lo0)
define TLBMASK_LO1 offsetof(struct tlbmask, tlb_lo1)
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.23 src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.24
--- src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.23 Mon Feb 15 07:36:04 2010
+++ src/sys/arch/mips/mips/mipsX_subr.S Tue Feb 16 08:13:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.23 2010/02/15 07:36:04 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.24 2010/02/16 08:13:57 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -1074,6 +1074,7 @@
REG_S s0, TF_BASE+TF_REG_S0(sp) # s0 is used for saved ipl
REG_S s1, TF_BASE+TF_REG_S1(sp) # s1 is used for initial status
mfc0 s1, MIPS_COP_0_STATUS
+ REG_S s2, TF_BASE+TF_REG_S2(sp) # s2 is used for cpu_info
REG_S t8, TF_BASE+TF_REG_T8(sp)
REG_S t9, TF_BASE+TF_REG_T9(sp)
REG_S ra, TF_BASE+TF_REG_RA(sp)
@@ -1094,9 +1095,9 @@
#endif
move MIPS_CURLWP, k1 # XXX Atheros HAL
+ PTR_L s2, L_CPU(MIPS_CURLWP)
#ifdef PARANOIA
- PTR_L t0, L_CPU(MIPS_CURLWP)
- INT_L s0, CPU_INFO_CPL(t0)
+ INT_L s0, CPU_INFO_CPL(s2)
INT_S s0, TF_BASE+TF_PPL(sp) # save priority level
/*
@@ -1132,11 +1133,10 @@
nop
#endif /* PARANOIA */
- PTR_L t0, L_CPU(MIPS_CURLWP)
- INT_L t1, CPU_INFO_IDEPTH(t0) # we need to inc. intr depth
+ INT_L t1, CPU_INFO_IDEPTH(s2) # we need to inc. intr depth
or s0, t1 # save old interrupt depth
INT_ADDU t1, 1
- INT_S t1, CPU_INFO_IDEPTH(t0) # store new interrupt depth
+ INT_S t1, CPU_INFO_IDEPTH(s2) # store new interrupt depth
/*
* Now we can clear exception level since no interrupts can be delivered
@@ -1155,9 +1155,8 @@
jal _C_LABEL(cpu_intr) # cpu_intr(ppl, pc, status)
srl a0, s0, 8 # 1st arg is previous pri level
- PTR_L t2, L_CPU(MIPS_CURLWP)
and t1, s0, 0xff # get previous interrupt depth
- INT_S t1, CPU_INFO_IDEPTH(t2) # to it previous value
+ INT_S t1, CPU_INFO_IDEPTH(s2) # to it previous value
#ifdef PARANOIA
mfc0 t0, MIPS_COP_0_STATUS # verify INT_IE is still set
@@ -1177,8 +1176,22 @@
jal _C_LABEL(softint_process) # softint_process(pending)
nop
+
+#ifdef __HAVE_PREEMPTION
+ srl v1, s0, 8 # get saved priority level
+ bnez v1, 4f # branch if not at IPL_NONE
+ nop
+ INT_L t0, CPU_INFO_SOFTINTS(s2) # get pending softints
+ and v0, t0, 1 << SOFTINT_KPREEMPT # do we need a kernel preempt?
+ beqz v0, 4f # nop
+ nop
+ xor t0, v0 # clear preempt bit
+ INT_S t0, CPU_INFO_SOFTINTS(s2) # and save it.
+ jal _C_LABEL(kpreempt) # kpreempt(pc)
+ PTR_L a0, TF_BASE+TF_REG_EPC(sp)
+#endif /* __HAVE_PREEMPTION */
4:
-#endif
+#endif /* __HAVE_FAST_SOFTINT */
/*
* Restore registers and return from the interrupt.
*/
@@ -1262,8 +1275,7 @@
#ifdef PARANOIA
INT_L t2, TF_BASE+TF_PPL(sp) # get saved priority level
- PTR_L t0, L_CPU(MIPS_CURLWP)
- INT_L t1, CPU_INFO_CPL(t0) # get current priority level
+ INT_L t1, CPU_INFO_CPL(s2) # get current priority level
11: bne t2, t1, 11b # loop forever is unequal
nop
@@ -1289,6 +1301,7 @@
REG_L ta3, TF_BASE+TF_REG_TA3(sp)
REG_L s0, TF_BASE+TF_REG_S0(sp)
REG_L s1, TF_BASE+TF_REG_S1(sp)
+ REG_L s2, TF_BASE+TF_REG_S2(sp)
REG_L t8, TF_BASE+TF_REG_T8(sp) # MIPS_CURLWP
REG_L t9, TF_BASE+TF_REG_T9(sp)
REG_L ra, TF_BASE+TF_REG_RA(sp)
@@ -1337,6 +1350,7 @@
REG_S a3, CALLFRAME_SIZ+TF_REG_A3(k0) # $7
mfhi v1
REG_S t0, CALLFRAME_SIZ+TF_REG_T0(k0) # $12
+ mfc0 t0, MIPS_COP_0_CAUSE
REG_S t1, CALLFRAME_SIZ+TF_REG_T1(k0) # $13
REG_S t2, CALLFRAME_SIZ+TF_REG_T2(k0) # $14
REG_S t3, CALLFRAME_SIZ+TF_REG_T3(k0) # $15
@@ -1357,6 +1371,7 @@
REG_S v0, CALLFRAME_SIZ+TF_REG_MULLO(k0)
REG_S v1, CALLFRAME_SIZ+TF_REG_MULHI(k0)
REG_S ra, CALLFRAME_SIZ+TF_REG_EPC(k0)
+ REG_S t0, CALLFRAME_SIZ+TF_REG_CAUSE(k0)
#if TF_MIPS_CURLWP != TF_REG_T8
PTR_S MIPS_CURLWP, CALLFRAME_SIZ+TF_MIPS_CURLWP(k0)# save curlwp reg (t8)
#endif
Index: src/sys/arch/mips/mips/mips_machdep.c
diff -u src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.33 src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.34
--- src/sys/arch/mips/mips/mips_machdep.c:1.205.4.1.2.1.2.33 Mon Feb 15 07:36:04 2010
+++ src/sys/arch/mips/mips/mips_machdep.c Tue Feb 16 08:13:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.33 2010/02/15 07:36:04 matt Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.34 2010/02/16 08:13:57 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -112,7 +112,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.33 2010/02/15 07:36:04 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.205.4.1.2.1.2.34 2010/02/16 08:13:57 matt Exp $");
#include "opt_cputype.h"
#include "opt_compat_netbsd32.h"
@@ -136,10 +136,10 @@
#include <sys/sa.h>
#include <sys/savar.h>
#include <sys/cpu.h>
+#include <sys/atomic.h>
#include <sys/ucontext.h>
#include <mips/kcore.h>
-#include <mips/cpu.h>
#ifdef COMPAT_NETBSD32
#include <compat/netbsd32/netbsd32.h>
@@ -2310,18 +2310,149 @@
return (0);
}
+#ifdef MULTIPROCESSOR
+static void
+mips_send_ipi(struct cpu_info *ci, int ipi)
+{
+ /* do nothing */
+}
+#endif
+
void
cpu_need_resched(struct cpu_info *ci, int flags)
{
+ struct lwp * const l = ci->ci_data.cpu_onproc;
+#ifdef MULTIPROCESSOR
+ struct cpu_info * const cur_ci = curcpu();
+#endif
+
+ KASSERT(kpreempt_disabled());
+
+ ci->ci_want_resched |= flags;
+
+ if (__predict_false((l->l_pflag & LP_INTR) != 0)) {
+ /*
+ * No point doing anything, it will switch soon.
+ * Also here to prevent an assertion failure in
+ * kpreempt() due to preemption being set on a
+ * soft interrupt LWP.
+ */
+ return;
+ }
+
+ if (__predict_false(l == ci->ci_data.cpu_idlelwp)) {
+#ifdef MULTIPROCESSOR
+ /*
+ * If the other CPU is idling, it must be waiting for an
+ * interrupt. So give it one.
+ */
+ if (__predict_false(ci != cur_ci))
+ mips_send_ipi(ci, 0);
+#endif
+ return;
+ }
- aston(ci->ci_data.cpu_onproc);
- ci->ci_want_resched = 1;
+#ifdef MULTIPROCESSOR
+ atomic_or_uint(&ci->ci_want_resched, flags);
+#else
+ ci->ci_want_resched |= flags;
+#endif
+ if (flags & RESCHED_KPREEMPT) {
#ifdef __HAVE_PREEMPTION
+ atomic_or_uint(&l->l_dopreempt, DOPREEMPT_ACTIVE);
+ if (ci == cur_ci) {
+ softint_trigger(SOFTINT_KPREEMPT);
+ } else {
+ mips_send_ipi(ci, 0);
+ }
+#endif
+ return;
+ }
+ l->l_md.md_astpending = 1; /* force call to ast() */
+#ifdef MULTIPROCESSOR
+ if (ci != cur_ci && (flags & RESCHED_IMMED)) {
+ mips_send_ipi(ci, 0);
+ }
#endif
}
void
+cpu_signotify(struct lwp *l)
+{
+ KASSERT(kpreempt_disabled());
+ KASSERT(lwp_locked(l, NULL));
+ KASSERT(l->l_stat == LSONPROC || l->l_stat == LSRUN);
+
+ l->l_md.md_astpending = 1; /* force call to ast() */
+}
+
+void
+cpu_need_proftick(struct lwp *l)
+{
+ KASSERT(kpreempt_disabled());
+ KASSERT(l->l_cpu == curcpu());
+
+ l->l_pflag |= LP_OWEUPC;
+ l->l_md.md_astpending = 1; /* force call to ast() */
+}
+
+void
+cpu_set_curpri(int pri)
+{
+ kpreempt_disable();
+ curcpu()->ci_schedstate.spc_curpriority = pri;
+ kpreempt_enable();
+}
+
+
+#ifdef __HAVE_PREEMPTION
+bool
+cpu_kpreempt_enter(uintptr_t where, int s)
+{
+ KASSERT(kpreempt_disabled());
+
+ if (where == 0) {
+ /*
+ * We are called from KPREEMPT_ENABLE(). If we are at IPL_NONE,
+ * of course we can be preempted. If we aren't, ask for a
+ * softint so that kern_intr can call kpreempt.
+ */
+ if (s == IPL_NONE)
+ return true;
+ softint_trigger(SOFTINT_KPREEMPT);
+ return false;
+ }
+
+ /*
+ * We must be called via kern_intr (which already checks for IPL_NONE
+ * so of course we call be preempted).
+ */
+ return true;
+}
+
+void
+cpu_kpreempt_exit(uintptr_t where)
+{
+
+ /* do nothing */
+}
+
+/*
+ * Return true if preemption is disabled for MD reasons. Must be called
+ * with preemption disabled, and thus is only for diagnostic checks.
+ */
+bool
+cpu_kpreempt_disabled(void)
+{
+ /*
+ * Any elevated IPL disables preemption.
+ */
+ return curcpu()->ci_cpl > IPL_NONE;
+}
+#endif /* __HAVE_PREEMPTION */
+
+void
cpu_idle(void)
{
void (*const mach_idle)(void) = mips_locoresw.lsw_cpu_idle;
@@ -2334,8 +2465,11 @@
bool
cpu_intr_p(void)
{
-
- return curcpu()->ci_idepth != 0;
+ bool rv;
+ kpreempt_disable();
+ rv = (curcpu()->ci_idepth != 0);
+ kpreempt_enable();
+ return rv;
}
#ifdef MULTIPROCESSOR
@@ -2412,7 +2546,7 @@
KASSERT(status == MIPS_INT_MASK);
KASSERT(ci->ci_cpl == IPL_NONE);
- for (int r = IPL_PREEMPT; r <= IPL_HIGH; r++) {
+ for (int r = IPL_SOFTCLOCK; r <= IPL_HIGH; r++) {
/*
* As IPL increases, more intrs may be masked but no intrs
* may become unmasked.
Index: src/sys/arch/mips/mips/mips_softint.c
diff -u src/sys/arch/mips/mips/mips_softint.c:1.1.2.4 src/sys/arch/mips/mips/mips_softint.c:1.1.2.5
--- src/sys/arch/mips/mips/mips_softint.c:1.1.2.4 Mon Feb 15 07:36:04 2010
+++ src/sys/arch/mips/mips/mips_softint.c Tue Feb 16 08:13:57 2010
@@ -29,7 +29,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_softint.c,v 1.1.2.4 2010/02/15 07:36:04 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_softint.c,v 1.1.2.5 2010/02/16 08:13:57 matt Exp $");
#include <sys/param.h>
#include <sys/proc.h>
@@ -48,9 +48,6 @@
#define SOFTINT_CLOCK_MASK (1 << SOFTINT_CLOCK)
#define SOFTINT_NET_MASK (1 << SOFTINT_NET)
#define SOFTINT_SERIAL_MASK (1 << SOFTINT_SERIAL)
-#ifdef __HAVE_PREEMPTION
-#define SOFTINT_PREEMPT_MASK (1 << SOFTINT_COUNT)
-#endif
/*
* This is more complex than usual since we want the fast softint threads
Index: src/sys/arch/mips/rmi/rmixl_intr.c
diff -u src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.11 src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.12
--- src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.11 Mon Feb 15 07:37:36 2010
+++ src/sys/arch/mips/rmi/rmixl_intr.c Tue Feb 16 08:13:57 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_intr.c,v 1.1.2.11 2010/02/15 07:37:36 matt Exp $ */
+/* $NetBSD: rmixl_intr.c,v 1.1.2.12 2010/02/16 08:13:57 matt Exp $ */
/*-
* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
@@ -64,7 +64,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.11 2010/02/15 07:37:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.12 2010/02/16 08:13:57 matt Exp $");
#include "opt_ddb.h"
@@ -106,7 +106,6 @@
#define _SR_BITS_DFLT (MIPS_INT_MASK_2|MIPS_INT_MASK_3|MIPS_INT_MASK_4)
const uint32_t ipl_sr_bits[_IPL_N] = {
[IPL_NONE] = _SR_BITS_DFLT,
- [IPL_PREEMPT] = _SR_BITS_DFLT,
[IPL_SOFTCLOCK] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK_0,
[IPL_SOFTNET] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK,
[IPL_VM] = _SR_BITS_DFLT | MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
