Module Name: src
Committed By: tsutsui
Date: Sat Feb 26 13:58:35 UTC 2011
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
- clear MIPS_FPU_EXCEPTION_BITS in MIPS_FPU_CSR in SIGILL case
as noted in commit log of rev 1.158
- update comment to reflect changes in rev 1.109
To generate a diff of this commit:
cvs rdiff -u -r1.182 -r1.183 src/sys/arch/mips/mips/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/locore.S
diff -u src/sys/arch/mips/mips/locore.S:1.182 src/sys/arch/mips/mips/locore.S:1.183
--- src/sys/arch/mips/mips/locore.S:1.182 Sat Feb 26 09:47:24 2011
+++ src/sys/arch/mips/mips/locore.S Sat Feb 26 13:58:34 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.182 2011/02/26 09:47:24 tsutsui Exp $ */
+/* $NetBSD: locore.S,v 1.183 2011/02/26 13:58:34 tsutsui Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -645,12 +645,12 @@
* Check to see if the instruction to be emulated is a floating-point
* instruction.
*/
- srl t0, a0, MIPS_OPCODE_SHIFT
- beq t0, MIPS_OPCODE_C1, 4f
+ srl t2, a0, MIPS_OPCODE_SHIFT
+ beq t2, MIPS_OPCODE_C1, 4f
nop
/*
- * Send a floating point exception signal to the current LWP.
+ * Send an ILL signal to the current LWP if the instruction can't be emulated.
*/
srl a2, 8
sll a2, 8
@@ -659,6 +659,9 @@
REG_S a2, TF_REG_CAUSE(a1)
REG_EPILOGUE
+ and t2, t0, ~MIPS_FPU_EXCEPTION_BITS
+ ctc1 t2, MIPS_FPU_CSR
+
move a1, a0 # code = instruction
jal _C_LABEL(mips_fpuillinst)
move a0, MIPS_CURLWP # get current LWP
