Module Name: src
Committed By: tsutsui
Date: Tue Mar 8 15:12:46 UTC 2011
Modified Files:
src/sys/arch/mips/mips: locore_mips1.S
Log Message:
Pass correct exception PC value to cpu_intr() as mipsX_subr.S does.
Fixes SIGILL on all FPU exceptions on R3000.
XXX: cpu_intr() may require cause value as mentioned in PR port-mips/44639
To generate a diff of this commit:
cvs rdiff -u -r1.74 -r1.75 src/sys/arch/mips/mips/locore_mips1.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/locore_mips1.S
diff -u src/sys/arch/mips/mips/locore_mips1.S:1.74 src/sys/arch/mips/mips/locore_mips1.S:1.75
--- src/sys/arch/mips/mips/locore_mips1.S:1.74 Tue Mar 8 15:05:40 2011
+++ src/sys/arch/mips/mips/locore_mips1.S Tue Mar 8 15:12:46 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips1.S,v 1.74 2011/03/08 15:05:40 tsutsui Exp $ */
+/* $NetBSD: locore_mips1.S,v 1.75 2011/03/08 15:12:46 tsutsui Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -452,6 +452,7 @@
#if defined(DDB) || defined(DEBUG) || defined(KGDB)
REG_S ra, KERNFRAME_RA(sp) # for debugging
#endif
+ move ta0, ra # save across spl* calls
#ifdef PARANOIA
INT_L s0, CPU_INFO_CPL(s2)
@@ -506,7 +507,7 @@
/*
* Now hard interrupts can be processed.
*/
- move a1, ra # 2nd arg is exception PC
+ move a1, ta0 # 2nd arg is exception PC
move a2, s1 # 3rd arg is status
jal _C_LABEL(cpu_intr) # cpu_intr(ppl, pc, status)
srl a0, s0, 8 # 1st arg is previous pri level
@@ -763,6 +764,7 @@
#ifdef __GP_SUPPORT__
PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
#endif
+ move ta0, ra # save across spl* calls
/*
* We first need to get to IPL_HIGH so that interrupts are masked.
@@ -797,7 +799,7 @@
/*
* Now hard interrupts can be processed.
*/
- move a1, ra # 2nd arg is exception pc
+ move a1, ta0 # 2nd arg is exception pc
move a2, s1 # 3rd arg is status
jal _C_LABEL(cpu_intr) # cpu_intr(ppl, pc, status)
move a0, s0 # 1st arg is previous pri level
