Module Name: src
Committed By: matt
Date: Fri Dec 2 00:01:38 UTC 2011
Modified Files:
src/sys/arch/mips/conf [matt-nb5-mips64]: files.mips
src/sys/arch/mips/include [matt-nb5-mips64]: mips3_pte.h mips_param.h
vmparam.h
src/sys/arch/mips/mips [matt-nb5-mips64]: genassym.cf mipsX_subr.S
Log Message:
Add support for 8KB pages.
To generate a diff of this commit:
cvs rdiff -u -r1.58.24.16 -r1.58.24.17 src/sys/arch/mips/conf/files.mips
cvs rdiff -u -r1.23.38.6 -r1.23.38.7 src/sys/arch/mips/include/mips3_pte.h
cvs rdiff -u -r1.23.78.6 -r1.23.78.7 src/sys/arch/mips/include/mips_param.h
cvs rdiff -u -r1.41.28.21 -r1.41.28.22 src/sys/arch/mips/include/vmparam.h
cvs rdiff -u -r1.44.12.28 -r1.44.12.29 src/sys/arch/mips/mips/genassym.cf
cvs rdiff -u -r1.26.36.1.2.48 -r1.26.36.1.2.49 \
src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/conf/files.mips
diff -u src/sys/arch/mips/conf/files.mips:1.58.24.16 src/sys/arch/mips/conf/files.mips:1.58.24.17
--- src/sys/arch/mips/conf/files.mips:1.58.24.16 Tue Nov 29 07:48:31 2011
+++ src/sys/arch/mips/conf/files.mips Fri Dec 2 00:01:37 2011
@@ -3,6 +3,8 @@
defflag opt_cputype.h NOFPU FPEMUL
MIPS64_SB1
+ ENABLE_MIPS_16KB_PAGE
+ ENABLE_MIPS_8KB_PAGE
ENABLE_MIPS_KSEGX
MIPS64_XLP MIPS64_XLR MIPS64_XLS
# and the rest...
Index: src/sys/arch/mips/include/mips3_pte.h
diff -u src/sys/arch/mips/include/mips3_pte.h:1.23.38.6 src/sys/arch/mips/include/mips3_pte.h:1.23.38.7
--- src/sys/arch/mips/include/mips3_pte.h:1.23.38.6 Tue Jan 26 21:19:25 2010
+++ src/sys/arch/mips/include/mips3_pte.h Fri Dec 2 00:01:37 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: mips3_pte.h,v 1.23.38.6 2010/01/26 21:19:25 matt Exp $ */
+/* $NetBSD: mips3_pte.h,v 1.23.38.7 2011/12/02 00:01:37 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -106,9 +106,19 @@ unsigned int pg_g:1, /* HW: ignore as
#define MIPS3_PG_WIRED 0x80000000 /* SW */
#define MIPS3_PG_RO 0x40000000 /* SW */
+#ifdef ENABLE_MIPS_16KB_PAGE
+#define MIPS3_PG_SVPN 0xffffc000 /* Software page no mask */
+#define MIPS3_PG_HVPN 0xffff8000 /* Hardware page no mask */
+#define MIPS3_PG_ODDPG 0x00004000 /* Odd even pte entry */
+#elif defined(ENABLE_MIPS_8KB_PAGE)
+#define MIPS3_PG_SVPN 0xffffe000 /* Software page no mask */
+#define MIPS3_PG_HVPN 0xffffe000 /* Hardware page no mask */
+#define MIPS3_PG_NEXT 0x00000040 /* next PFN */
+#elif defined(ENABLE_MIPS_4KB_PAGE) || 1
#define MIPS3_PG_SVPN 0xfffff000 /* Software page no mask */
#define MIPS3_PG_HVPN 0xffffe000 /* Hardware page no mask */
#define MIPS3_PG_ODDPG 0x00001000 /* Odd even pte entry */
+#endif
#define MIPS3_PG_ASID 0x000000ff /* Address space ID */
#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
#define MIPS3_PG_V 0x00000002 /* Valid */
@@ -189,7 +199,10 @@ unsigned int pg_g:1, /* HW: ignore as
((((pg_mask) | 0x00001fff) + 1) / 2)
#define MIPS3_PG_SIZE_TO_MASK(pg_size) \
- ((((pg_size) * 2) - 1) & ~0x00001fff)
+ ((((pg_size) << (((pg_size) & 0x2aaaa) == 0)) - 1) & ~0x00001fff)
+
+CTASSERT(MIPS3_PG_SIZE_TO_MASK(4096) == MIPS3_PG_SIZE_4K);
+CTASSERT(MIPS3_PG_SIZE_TO_MASK(8192) == MIPS3_PG_SIZE_4K);
/* NEC Vr41xx uses different pagemask values. */
#define MIPS4100_PG_SIZE_1K 0x00000000
Index: src/sys/arch/mips/include/mips_param.h
diff -u src/sys/arch/mips/include/mips_param.h:1.23.78.6 src/sys/arch/mips/include/mips_param.h:1.23.78.7
--- src/sys/arch/mips/include/mips_param.h:1.23.78.6 Mon Aug 16 18:01:13 2010
+++ src/sys/arch/mips/include/mips_param.h Fri Dec 2 00:01:37 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_param.h,v 1.23.78.6 2010/08/16 18:01:13 matt Exp $ */
+/* $NetBSD: mips_param.h,v 1.23.78.7 2011/12/02 00:01:37 matt Exp $ */
#ifdef _KERNEL
#include <machine/cpu.h>
@@ -39,9 +39,16 @@
#define SSIZE 1 /* initial stack size/NBPG */
#define SINCR 1 /* increment of stack/NBPG */
+#if defined(ENABLE_MIPS_16KB_PAGE) || defined(ENABLE_MIPS_8KB_PAGE)
+#define UPAGES 1 /* pages of u-area */
+#define USPACE (UPAGES*NBPG) /* size of u-area in bytes */
+#elif defined(ENABLE_MIPS_4KB_PAGE) || 1
#define UPAGES 2 /* pages of u-area */
#define USPACE (UPAGES*NBPG) /* size of u-area in bytes */
#define USPACE_ALIGN USPACE /* make sure it starts on a even VA */
+#else
+#error ENABLE_MIPS_xKB_PAGE not defined
+#endif
#ifndef MSGBUFSIZE
#define MSGBUFSIZE NBPG /* default message buffer size */
@@ -62,9 +69,15 @@
#define ALIGN(p) (((uintptr_t)(p) + ALIGNBYTES) & ~ALIGNBYTES)
#define ALIGNED_POINTER(p,t) ((((uintptr_t)(p)) & (sizeof(t)-1)) == 0)
-#define NBPG 4096 /* bytes/page */
-#define PGOFSET (NBPG-1) /* byte offset into page */
+#ifdef ENABLE_MIPS_16KB_PAGE
+#define PGSHIFT 14 /* LOG2(NBPG) */
+#elif defined(ENABLE_MIPS_8KB_PAGE)
+#define PGSHIFT 13 /* LOG2(NBPG) */
+#else
#define PGSHIFT 12 /* LOG2(NBPG) */
+#endif
+#define NBPG (1 << PGSHIFT) /* bytes/page */
+#define PGOFSET (NBPG-1) /* byte offset into page */
#define NPTEPG (NBPG/4)
#define NBSEG (NBPG*NPTEPG) /* bytes/segment */
Index: src/sys/arch/mips/include/vmparam.h
diff -u src/sys/arch/mips/include/vmparam.h:1.41.28.21 src/sys/arch/mips/include/vmparam.h:1.41.28.22
--- src/sys/arch/mips/include/vmparam.h:1.41.28.21 Tue Nov 29 07:48:31 2011
+++ src/sys/arch/mips/include/vmparam.h Fri Dec 2 00:01:37 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: vmparam.h,v 1.41.28.21 2011/11/29 07:48:31 matt Exp $ */
+/* $NetBSD: vmparam.h,v 1.41.28.22 2011/12/02 00:01:37 matt Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -42,6 +42,7 @@
#define _MIPS_VMPARAM_H_
#ifdef _KERNEL_OPT
+#include "opt_cputype.h"
#include "opt_multiprocessor.h"
#endif
@@ -50,10 +51,18 @@
*/
/*
- * We use a 4K page on MIPS systems. Override PAGE_* definitions
- * to compile-time constants.
+ * We normally use a 4K page but may use 16K on MIPS systems.
+ * Override PAGE_* definitions to compile-time constants.
*/
+#ifdef ENABLE_MIPS_16KB_PAGE
+#define PAGE_SHIFT 14
+#elif defined(ENABLE_MIPS_8KB_PAGE)
+#define PAGE_SHIFT 13
+#elif defined(ENABLE_MIPS_4KB_PAGE) || 1
#define PAGE_SHIFT 12
+#else
+#error ENABLE_MIPS_xKB_PAGE not defined
+#endif
#define PAGE_SIZE (1 << PAGE_SHIFT)
#define PAGE_MASK (PAGE_SIZE - 1)
Index: src/sys/arch/mips/mips/genassym.cf
diff -u src/sys/arch/mips/mips/genassym.cf:1.44.12.28 src/sys/arch/mips/mips/genassym.cf:1.44.12.29
--- src/sys/arch/mips/mips/genassym.cf:1.44.12.28 Tue Nov 29 07:48:31 2011
+++ src/sys/arch/mips/mips/genassym.cf Fri Dec 2 00:01:37 2011
@@ -132,8 +132,7 @@ define VM_MIN_KERNEL_ADDRESS VM_MIN_KERN
define VM_MAX_KERNEL_ADDRESS VM_MAX_KERNEL_ADDRESS
ifdef ENABLE_MIPS_KSEGX
define VM_KSEGX_ADDRESS VM_KSEGX_ADDRESS
-define VM_KSEGX_SHIFT VM_KSEGX_SHIFT
-define MIPS3_DEFAULT_PG_SHIFT MIPS3_DEFAULT_PG_SHIFT
+define VM_KSEGX_SIZE VM_KSEGX_SIZE
endif
define SIGFPE SIGFPE
@@ -151,7 +150,12 @@ define MIPS3_PG_V MIPS3_PG_V
define MIPS3_PG_D MIPS3_PG_D
define MIPS3_PG_HVPN MIPS3_PG_HVPN
define MIPS3_PG_ASID MIPS3_PG_ASID
+ifdef MIPS3_PG_NEXT
+define MIPS3_PG_NEXT MIPS3_PG_NEXT
+endif
+ifdef MIPS3_PG_ODDPG
define MIPS3_PG_ODDPG MIPS3_PG_ODDPG
+endif
define TF_SIZ sizeof(struct trapframe)
define TF_REG_ZERO offsetof(struct trapframe, tf_regs[_R_ZERO])
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.48 src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.49
--- src/sys/arch/mips/mips/mipsX_subr.S:1.26.36.1.2.48 Thu Dec 1 03:50:08 2011
+++ src/sys/arch/mips/mips/mipsX_subr.S Fri Dec 2 00:01:37 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.48 2011/12/01 03:50:08 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.49 2011/12/02 00:01:37 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -367,16 +367,35 @@ MIPSX(tlb_miss_common):
_MFC0 k0, MIPS_COP_0_BAD_VADDR #0a: k0=bad address (again)
#if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0
beqz k1, MIPSX(nopagetable) #0b: ==0 -- no page table
+#if (PGSHIFT & 1) == 0
_EXT k0, k0, PGSHIFT+1, PGSHIFT-3 #0c: k0=VA[13:21]
_INS k1, k0, 3, PGSHIFT-3 #0d: k0=page table index
#0d: k1=pte address
#else
+ _EXT k0, k0, PGSHIFT, PGSHIFT-2 #0c: k0=VA[13:21]
+ _INS k1, k0, 2, PGSHIFT-2 #0d: k0=page table index
+ #0d: k1=pte address
+#endif
+#else
beqz k1, MIPSX(nopagetable) #0b: ==0 -- no page table
PTR_SRL k0, (PGSHIFT-2) #0c: k0=VPN (aka va>>10)
+#if (PGSHIFT & 1) == 0
andi k0, (NBPG-8) #0d: k0=page table offset
+#else
+ andi k0, (NBPG-4) #0d: k0=page table offset
+#endif
PTR_ADDU k1, k0 #0e: k1=pte address
#endif
-#if (MIPS64R2 + MIPS64R2_RMIXL) > 0
+#if PGSHIFT & 1
+ INT_L k0, 0(k1) #0f: k0=lo0 pte
+#if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0
+ _EXT k0, k0, 0, WIRED_POS #11: chop top 2 bits
+#else
+ _SLL k0, WIRED_SHIFT #11: chop top 2 bits (part 1a)
+ _SRL k0, WIRED_SHIFT #12: chop top 2 bits (part 1b)
+#endif
+ INT_ADDU k1, k0, MIPS3_PG_NEXT #13: k1=lo1 pte
+#elif (MIPS64R2 + MIPS64R2_RMIXL) > 0
REG_L k0, 0(k1) #0f: load PTEs
_EXT k1, k0, 32*_QUAD_HIGHWORD, WIRED_POS #10: extract lo1 pte
_EXT k0, k0, 32*_QUAD_LOWWORD, WIRED_POS #11: extract lo0 pte
@@ -1597,11 +1616,14 @@ LEAF_NOPROFILE(MIPSX(kern_tlb_miss))
nop # - delay slot -
#endif
PTR_L k1, _C_LABEL(Sysmap)
+#if (PGSHIFT & 1) == 0
PTR_SRL k0, 1
PTR_SLL k0, 3 # compute offset from index
+#else
+ PTR_SLL k0, 2 # compute offset from index
+#endif
PTR_ADDU k1, k0
INT_L k0, 0(k1) # get PTE entry
- INT_L k1, 4(k1) # get odd PTE entry
#if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0
_EXT k0, k0, 0, WIRED_POS
#else
@@ -1609,12 +1631,17 @@ LEAF_NOPROFILE(MIPSX(kern_tlb_miss))
_SRL k0, k0, WIRED_SHIFT
#endif
_MTC0 k0, MIPS_COP_0_TLB_LO0 # load PTE entry
+#if (PGSHIFT & 1) == 0
+ INT_L k1, 4(k1) # get odd PTE entry
#if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0
_EXT k1, k1, 0, WIRED_POS
#else
_SLL k1, k1, WIRED_SHIFT
_SRL k1, k1, WIRED_SHIFT
#endif
+#else
+ INT_ADDU k1, k0, MIPS3_PG_NEXT # point to next page
+#endif /* PGSHIFT & 1) == 0 */
_MTC0 k1, MIPS_COP_0_TLB_LO1 # load PTE entry
COP0_SYNC
tlbwr # write random TLB
@@ -1695,12 +1722,14 @@ LEAF_NOPROFILE(MIPSX(tlb_invalid_excepti
bltz k0, TLB_INVALID_EXCEPTION_EXIT # ASSERT(TLB entry exists)
nop # - delay slot -
+#if (PGSHIFT & 1) == 0
and k0, k1, 4 # check even/odd page
#ifdef MIPS3
nop # required for QED 5230
#endif
bnez k0, MIPSX(kern_tlbi_odd)
nop
+#endif /* (PGSHIFT & 1) == 0 */
INT_L k0, 0(k1) # get PTE entry
#if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0
@@ -1710,6 +1739,10 @@ LEAF_NOPROFILE(MIPSX(tlb_invalid_excepti
_SRL k0, k0, WIRED_SHIFT
#endif
_MTC0 k0, MIPS_COP_0_TLB_LO0 # load PTE entry
+#if (PGSHIFT & 1) != 0
+ INT_ADDU k0, MIPS3_PG_NEXT
+ _MTC0 k0, MIPS_COP_0_TLB_LO1 # load PTE entry
+#endif
COP0_SYNC
and k0, k0, MIPS3_PG_V # check for valid entry
#ifdef MIPS3
@@ -1718,6 +1751,7 @@ LEAF_NOPROFILE(MIPSX(tlb_invalid_excepti
beqz k0, TLB_INVALID_EXCEPTION_EXIT # PTE invalid
nop # - delay slot -
+#if (PGSHIFT & 1) == 0
INT_L k0, 4(k1) # get odd PTE entry
mfc0 k1, MIPS_COP_0_TLB_INDEX
#if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0
@@ -1730,6 +1764,7 @@ LEAF_NOPROFILE(MIPSX(tlb_invalid_excepti
or k1, k1, k0
_MTC0 k0, MIPS_COP_0_TLB_LO1 # load PTE entry
COP0_SYNC
+#endif /* (PGSHIFT & 1) == 0 */
tlbwi # write TLB
COP0_SYNC
#ifdef MIPS3
@@ -1742,6 +1777,7 @@ LEAF_NOPROFILE(MIPSX(tlb_invalid_excepti
#endif
eret
+#if (PGSHIFT & 1) == 0
MIPSX(kern_tlbi_odd):
INT_L k0, 0(k1) # get PTE entry
#if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0
@@ -1782,6 +1818,7 @@ MIPSX(kern_tlbi_odd):
INT_S zero, 0(k1) # clear lock
#endif
eret
+#endif /* (PGSHIFT & 1) == 0 */
#if defined(MULTIPROCESSOR) && (MIPS64_RMIXL + MIPS64R2_RMIXL) > 0
/*
@@ -1845,7 +1882,9 @@ LEAF(MIPSX(tlb_update_addr))
mfc0 v1, MIPS_COP_0_STATUS # Save the status register.
mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
COP0_SYNC
+#if (PGSHIFT & 1) == 0
and t1, a0, MIPS3_PG_ODDPG # t1 = Even/Odd flag
+#endif
li v0, (MIPS3_PG_HVPN | MIPS3_PG_ASID)
and a0, a0, v0
_MFC0 t0, MIPS_COP_0_TLB_HI # Save current PID
@@ -1861,10 +1900,12 @@ LEAF(MIPSX(tlb_update_addr))
_SRL a1, a1, WIRED_SHIFT
#endif
mfc0 v0, MIPS_COP_0_TLB_INDEX # See what we got
+#if (PGSHIFT & 1) == 0
bnez t1, 1f # Decide even odd
nop
+#endif
# EVEN
- bltz v0, 1f # index < 0 => !found
+ bltz v0, 4f # index < 0 => !found
nop
#ifdef MIPS3
nop # required for QED5230
@@ -1872,9 +1913,14 @@ LEAF(MIPSX(tlb_update_addr))
tlbr # update, read entry first
COP0_SYNC
_MTC0 a1, MIPS_COP_0_TLB_LO0 # init low reg0.
+#if (PGSHIFT & 1) != 0
+ INT_ADDU a1, MIPS3_PG_NEXT # point to next page
+ _MTC0 a1, MIPS_COP_0_TLB_LO1 # init low reg1.
+#endif
COP0_SYNC
tlbwi # update slot found
COP0_SYNC
+#if (PGSHIFT & 1) == 0
b 4f
nop
1:
@@ -1890,6 +1936,7 @@ LEAF(MIPSX(tlb_update_addr))
COP0_SYNC
tlbwi # update slot found
COP0_SYNC
+#endif /* (PGSHIFT & 1) == 0 */
4:
#ifdef MIPS3
nop # Make sure pipeline
@@ -1972,7 +2019,7 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_addr
mfc0 v0, MIPS_COP_0_TLB_INDEX # see what we got
bltz v0, 1f # index < 0 then skip
li t1, MIPS_KSEG0_START # invalid address
- PTR_SLL v0, PGSHIFT + 1 # PAGE_SHIFT + 1
+ PTR_SLL v0, (PGSHIFT | 1) # PAGE_SHIFT | 1
PTR_ADDU t1, v0
_MTC0 t1, MIPS_COP_0_TLB_HI # make entryHi invalid
_MTC0 zero, MIPS_COP_0_TLB_LO0 # zero out entryLo0
@@ -2014,7 +2061,7 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_asid
1:
mtc0 t1, MIPS_COP_0_TLB_INDEX # set index
COP0_SYNC
- sll ta0, t1, PGSHIFT + 1 # PAGE_SHIFT + 1
+ sll ta0, t1, PGSHIFT | 1 # PAGE_SHIFT | 1
tlbr # obtain an entry
COP0_SYNC
_MFC0 a0, MIPS_COP_0_TLB_LO1
@@ -2071,7 +2118,7 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_glob
1:
mtc0 t1, MIPS_COP_0_TLB_INDEX # set index
COP0_SYNC
- sll ta0, t1, PGSHIFT + 1 # PAGE_SHIFT + 1
+ sll ta0, t1, PGSHIFT | 1 # PAGE_SHIFT | 1
tlbr # obtain an entry
COP0_SYNC
_MFC0 a0, MIPS_COP_0_TLB_LO1
@@ -2124,7 +2171,7 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_all)
1:
mtc0 t1, MIPS_COP_0_TLB_INDEX # set TLBindex
COP0_SYNC
- sll ta0, t1, PGSHIFT + 1 # PAGE_SHIFT + 1
+ sll ta0, t1, PGSHIFT | 1 # PAGE_SHIFT | 1
PTR_ADDU ta0, v0
_MTC0 ta0, MIPS_COP_0_TLB_HI # make entryHi invalid
COP0_SYNC
@@ -2222,13 +2269,17 @@ LEAF(MIPSX(tlb_enter))
.set noat
_MFC0 ta0, MIPS_COP_0_TLB_HI # save EntryHi
+#if (PGSHIFT & 1) == 0
and a3, a1, MIPS3_PG_ODDPG # select odd page bit
xor a3, a1 # clear it.
+#endif
_MTC0 a3, MIPS_COP_0_TLB_HI # set the VA for tlbp
COP0_SYNC
+#if (PGSHIFT & 1) == 0
and t2, a2, MIPS3_PG_G # make prototype tlb_lo0
and t3, a2, MIPS3_PG_G # make prototype tlb_lo1
+#endif
tlbp # is va in TLB?
COP0_SYNC
@@ -2237,11 +2288,13 @@ LEAF(MIPSX(tlb_enter))
bltz v0, 1f # nope
nop
+#if (PGSHIFT & 1) == 0
/*
* Get the existing tlb_lo's because we need to replace one of them.
*/
mfc0 t2, MIPS_COP_0_TLB_LO0 # save for update
mfc0 t3, MIPS_COP_0_TLB_LO1 # save for update
+#endif
/*
* If it's already where we want, no reason to invalidate it.
@@ -2250,9 +2303,9 @@ LEAF(MIPSX(tlb_enter))
nop
/*
- * Make an
+ * Clear the existing TLB entry for it.
*/
- sll t1, 1 + PGSHIFT # make a fake addr for the entry
+ sll t1, v0, (1 | PGSHIFT) # make a fake addr for the entry
lui v1, %hi(MIPS_KSEG0_START)
or t1, v1
_MTC0 t1, MIPS_COP_0_TLB_HI
@@ -2273,6 +2326,7 @@ LEAF(MIPSX(tlb_enter))
COP0_SYNC
2:
+#if (PGSHIFT & 1) == 0
and v1, a1, MIPS3_PG_ODDPG # odd or even page
sll v1, 31 - PGSHIFT # move to MSB
sra v1, 31 # v1 a mask (0/~0 = even/odd)
@@ -2287,6 +2341,11 @@ LEAF(MIPSX(tlb_enter))
mtc0 t2, MIPS_COP_0_TLB_LO0 # set tlb_lo0 (even)
mtc0 t3, MIPS_COP_0_TLB_LO1 # set tlb_lo1 (odd)
+#else
+ mtc0 a2, MIPS_COP_0_TLB_LO0 # set tlb_lo1 (lower half)
+ INT_ADDU a2, MIPS3_PG_NEXT
+ mtc0 a2, MIPS_COP_0_TLB_LO1 # set tlb_lo1 (upper half)
+#endif
COP0_SYNC
tlbwi # enter it into the TLB
@@ -2404,9 +2463,13 @@ END(MIPSX(setfunc_trampoline))
* sure TBIS(it) in the case.
*/
LEAF_NOPROFILE(MIPSX(cpu_switch_resume))
-#if PAGE_SIZE < USPACE
+#if PAGE_SIZE < USPACE || 1
INT_L a1, L_MD_UPTE_0(a0) # a1 = upte[0]
+#if (PGSHIFT & 1) == 0
INT_L a2, L_MD_UPTE_1(a0) # a2 = upte[1]
+#else
+ INT_ADDU a2, a1, MIPS3_PG_NEXT # a2 = page following upte[0]
+#endif
PTR_L v0, L_PCB(a0) # va = l->l_addr
#if VM_MIN_KERNEL_ADDRESS == MIPS_KSEG2_START
li t0, VM_MIN_KERNEL_ADDRESS # compute index
@@ -2442,11 +2505,13 @@ LEAF_NOPROFILE(MIPSX(cpu_switch_resume))
nop
#endif
+#if (PGSHIFT & 1) == 0
and t0, v0, MIPS3_PG_ODDPG
beqz t0, MIPSX(entry0)
nop
PANIC("USPACE sat on odd page boundary")
+#endif
MIPSX(entry0):
_MFC0 t3, MIPS_COP_0_TLB_HI # save TLB_HI
@@ -2459,7 +2524,7 @@ MIPSX(entry0):
nop
#endif
bltz t0, MIPSX(entry0set)
- sll t0, t0, PGSHIFT + 1 # PAGE_SHIFT + 1
+ sll t0, t0, (PGSHIFT | 1) # (PAGE_SHIFT | 1)
PTR_LA t0, MIPS_KSEG0_START(t0)
_MTC0 t0, MIPS_COP_0_TLB_HI
_MTC0 zero, MIPS_COP_0_TLB_LO0
