Module Name: src
Committed By: matt
Date: Wed Dec 28 05:36:11 UTC 2011
Modified Files:
src/sys/arch/mips/conf [matt-nb5-mips64]: files.rmixl
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_cfi_xlnor.c
rmixl_nor_pci.c rmixlreg.h rmixlvar.h
Added Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_flash_eb_space.c
rmixl_flash_el_space.c
Log Message:
Add NOR support for XLP.
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.15 -r1.1.2.16 src/sys/arch/mips/conf/files.rmixl
cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/rmi/rmixl_cfi_xlnor.c \
src/sys/arch/mips/rmi/rmixl_nor_pci.c
cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/mips/rmi/rmixl_flash_eb_space.c \
src/sys/arch/mips/rmi/rmixl_flash_el_space.c
cvs rdiff -u -r1.1.2.14 -r1.1.2.15 src/sys/arch/mips/rmi/rmixlreg.h
cvs rdiff -u -r1.1.2.22 -r1.1.2.23 src/sys/arch/mips/rmi/rmixlvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/conf/files.rmixl
diff -u src/sys/arch/mips/conf/files.rmixl:1.1.2.15 src/sys/arch/mips/conf/files.rmixl:1.1.2.16
--- src/sys/arch/mips/conf/files.rmixl:1.1.2.15 Tue Dec 27 19:58:18 2011
+++ src/sys/arch/mips/conf/files.rmixl Wed Dec 28 05:36:10 2011
@@ -1,4 +1,4 @@
-# $NetBSD: files.rmixl,v 1.1.2.15 2011/12/27 19:58:18 matt Exp $
+# $NetBSD: files.rmixl,v 1.1.2.16 2011/12/28 05:36:10 matt Exp $
#
# Configuration info for RMI XLP, XLR, XLS
#
@@ -77,6 +77,8 @@ file arch/mips/rmi/rmixl_nand_pci.c
device xlnor { [cs=-1] }
attach xlnor at pci with xlnor_pci
file arch/mips/rmi/rmixl_nor_pci.c xlnor_pci
+file arch/mips/rmi/rmixl_flash_eb_space.c xlnor_pci
+file arch/mips/rmi/rmixl_flash_el_space.c xlnor_pci
device cfi: norbus
attach cfi at xliobus with cfi_iobus
Index: src/sys/arch/mips/rmi/rmixl_cfi_xlnor.c
diff -u src/sys/arch/mips/rmi/rmixl_cfi_xlnor.c:1.1.2.1 src/sys/arch/mips/rmi/rmixl_cfi_xlnor.c:1.1.2.2
--- src/sys/arch/mips/rmi/rmixl_cfi_xlnor.c:1.1.2.1 Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixl_cfi_xlnor.c Wed Dec 28 05:36:11 2011
@@ -27,9 +27,12 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "opt_flash.h"
+#include "locators.h"
+
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rmixl_cfi_xlnor.c,v 1.1.2.1 2011/12/27 19:58:19 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rmixl_cfi_xlnor.c,v 1.1.2.2 2011/12/28 05:36:11 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -38,10 +41,11 @@ __KERNEL_RCSID(1, "$NetBSD: rmixl_cfi_xl
#include <dev/nor/nor.h>
#include <dev/nor/cfi.h>
-#include "locators.h"
+#include <mips/rmi/rmixl_iobusvar.h>
-static int cfi_xlnor_match(device_t, cfdata_t, void *);
+static int cfi_xlnor_match(device_t, cfdata_t, void *);
static void cfi_xlnor_attach(device_t, device_t, void *);
+static int cfi_xlnor_detach(device_t, int);
struct cfi_xlnor_softc {
device_t sc_dev;
@@ -53,16 +57,117 @@ struct cfi_xlnor_softc {
};
CFATTACH_DECL_NEW(cfi_xlnor, sizeof(struct cfi_xlnor_softc),
- cfi_xlnor_match, cfi_xlnor_attach, 0, 0);
+ cfi_xlnor_match, cfi_xlnor_attach, cfi_xlnor_detach, 0);
static int
cfi_xlnor_match(device_t parent, cfdata_t cf, void *aux)
{
- return 0;
+ struct rmixl_iobus_attach_args *ia = aux;
+ bus_size_t tmpsize = CFI_QRY_MIN_MAP_SIZE;
+ bus_addr_t addr = ia->ia_iobus_addr;
+ struct cfi cfi;
+ int rv;
+
+ KASSERT(ia->ia_iobus_bst != NULL);
+ KASSERT(ia->ia_iobus_addr == 0);
+ KASSERT(ia->ia_iobus_size >= tmpsize);
+ KASSERT(ia->ia_obio_bst == NULL);
+
+ if (cf->cf_loc[XLIOBUSCF_CS] != ia->ia_cs
+ && cf->cf_loc[XLIOBUSCF_CS] != XLIOBUSCF_CS_DEFAULT)
+ return 0;
+
+ cfi.cfi_bst = ia->ia_iobus_bst;
+ int error = bus_space_map(cfi.cfi_bst, addr, tmpsize, 0, &cfi.cfi_bsh);
+ if (error != 0) {
+ aprint_error("%s: cannot map %#"PRIxBUSSIZE" at offset %#"
+ PRIxBUSADDR": error %d\n", __func__, tmpsize, addr, error);
+ return 0;
+ }
+
+ if (!cfi_probe(&cfi)) {
+ aprint_debug("%s: probe addr %#"PRIxBUSADDR", CFI not found\n",
+ __func__, addr);
+ rv = 0;
+ } else {
+ rv = 1;
+ }
+
+ bus_space_unmap(cfi.cfi_bst, cfi.cfi_bsh, tmpsize);
+
+ return rv;
}
static void
cfi_xlnor_attach(device_t parent, device_t self, void *aux)
{
+ struct cfi_xlnor_softc *sc = device_private(self);
+ struct rmixl_iobus_attach_args *ia = aux;
+ struct cfi_query_data * const qryp = &sc->sc_cfi.cfi_qry_data;
+ const bus_size_t tmpsize = CFI_QRY_MIN_MAP_SIZE;
+ bool found;
+ int error;
+
aprint_normal("\n");
+
+ sc->sc_dev = self;
+ sc->sc_cfi.cfi_bst = ia->ia_iobus_bst;
+ sc->sc_addr = ia->ia_iobus_addr;
+
+ KASSERT(ia->ia_iobus_addr == 0);
+
+ /* map enough to identify, remap later when size is known */
+ error = bus_space_map(sc->sc_cfi.cfi_bst, sc->sc_addr, tmpsize,
+ 0, &sc->sc_cfi.cfi_bsh);
+ if (error != 0) {
+ aprint_error_dev(self, "could not map error %d\n", error);
+ return;
+ }
+
+ found = cfi_identify(&sc->sc_cfi);
+
+ bus_space_unmap(sc->sc_cfi.cfi_bst, sc->sc_cfi.cfi_bsh, tmpsize);
+
+ if (! found) {
+ /* should not happen, we already probed OK in match */
+ aprint_error_dev(self, "could not map error %d\n", error);
+ return;
+ }
+
+ sc->sc_size = 1 << qryp->device_size;
+
+ sc->sc_nor_if = nor_interface_cfi;
+ sc->sc_nor_if.private = &sc->sc_cfi;
+ sc->sc_nor_if.access_width = (1 << sc->sc_cfi.cfi_portwidth);
+
+ cfi_print(self, &sc->sc_cfi);
+
+ error = bus_space_map(sc->sc_cfi.cfi_bst, sc->sc_addr, sc->sc_size,
+ 0, &sc->sc_cfi.cfi_bsh);
+ if (error != 0) {
+ aprint_error_dev(self, "could not map error %d\n", error);
+ return;
+ }
+
+ if (! pmf_device_register1(self, NULL, NULL, NULL))
+ aprint_error_dev(self, "couldn't establish power handler\n");
+
+ sc->sc_nordev = nor_attach_mi(&sc->sc_nor_if, self);
+
+}
+
+static int
+cfi_xlnor_detach(device_t self, int flags)
+{
+ struct cfi_xlnor_softc *sc = device_private(self);
+ int rv = 0;
+
+ pmf_device_deregister(self);
+
+ if (sc->sc_nordev != NULL)
+ rv = config_detach(sc->sc_nordev, flags);
+
+ bus_space_unmap(sc->sc_cfi.cfi_bst, sc->sc_cfi.cfi_bsh, sc->sc_size);
+
+ return rv;
}
Index: src/sys/arch/mips/rmi/rmixl_nor_pci.c
diff -u src/sys/arch/mips/rmi/rmixl_nor_pci.c:1.1.2.1 src/sys/arch/mips/rmi/rmixl_nor_pci.c:1.1.2.2
--- src/sys/arch/mips/rmi/rmixl_nor_pci.c:1.1.2.1 Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixl_nor_pci.c Wed Dec 28 05:36:11 2011
@@ -29,7 +29,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rmixl_nor_pci.c,v 1.1.2.1 2011/12/27 19:58:19 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rmixl_nor_pci.c,v 1.1.2.2 2011/12/28 05:36:11 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -47,15 +47,34 @@ __KERNEL_RCSID(1, "$NetBSD: rmixl_nor_pc
#include <mips/rmi/rmixlreg.h>
#include <mips/rmi/rmixlvar.h>
+#include <mips/rmi/rmixl_iobusvar.h>
+
#include "locators.h"
static int xlnor_pci_match(device_t, cfdata_t, void *);
static void xlnor_pci_attach(device_t, device_t, void *);
+static int xlnor_print(void *, const char *);
+static int xlnor_intr(void *);
+
+struct xlnor_cs {
+ struct mips_bus_space cs_bst;
+ struct rmixl_region cs_region;
+ uint32_t cs_devparm;
+ uint32_t cs_devtime0;
+ uint32_t cs_devtime1;
+ u_int cs_number;
+};
+
-struct xlnor_softc {
+struct xlnor_softc {
device_t sc_dev;
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
+ size_t sc_ndevices;
+
+ kmutex_t sc_buslock;
+
+ struct xlnor_cs sc_cs[RMIXLP_NOR_NCS];
};
CFATTACH_DECL_NEW(xlnor_pci, sizeof(struct xlnor_softc),
@@ -87,10 +106,112 @@ xlnor_pci_attach(device_t parent, device
* Why isn't this accessible via a BAR?
*/
if (bus_space_subregion(sc->sc_bst, rcp->rc_pci_ecfg_eb_memh,
- pa->pa_tag | 0x100, 0, &sc->sc_bsh)) {
+ pa->pa_tag, 0, &sc->sc_bsh)) {
aprint_error(": can't map registers\n");
return;
}
- aprint_normal(": XLP NOR Controller\n");
+ mutex_init(&sc->sc_buslock, IPL_NONE, MUTEX_DEFAULT);
+
+ /*
+ * Let's see what devices we have attached.
+ */
+ for (size_t i = 0; i < RMIXLP_NOR_NCS; i++) {
+ struct rmixl_region * const rp = &rcp->rc_norflash[i];
+ if (rp->r_pbase == (bus_addr_t)-1 || rp->r_size == 0)
+ continue;
+
+ struct xlnor_cs * const cs = &sc->sc_cs[sc->sc_ndevices++];
+ cs->cs_region = *rp;
+ cs->cs_devparm = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
+ RMIXLP_NOR_CS_DEVPARMn(i));
+ cs->cs_devtime0 = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
+ RMIXLP_NOR_CS_DEVTIME0n(i));
+ cs->cs_devtime1 = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
+ RMIXLP_NOR_CS_DEVTIME1n(i));
+ cs->cs_number = i;
+
+ /*
+ * Each chip gets it's own bus space.
+ */
+ if (cs->cs_devparm & RMIXLP_NOR_CS_DEVPARM_LE) {
+ rmixl_flash_el_bus_mem_init(&cs->cs_bst,
+ &cs->cs_region);
+ } else {
+ rmixl_flash_eb_bus_mem_init(&cs->cs_bst,
+ &cs->cs_region);
+ }
+ }
+
+ aprint_normal(": XLP NOR Controller (%zu device%s)\n",
+ sc->sc_ndevices, (sc->sc_ndevices == 1 ? "" : "s"));
+
+ pci_intr_handle_t pcih;
+
+ pci_intr_map(pa, &pcih);
+
+ if (pci_intr_establish(pa->pa_pc, pcih, IPL_VM, xlnor_intr, sc) == NULL) {
+ aprint_error_dev(self, "failed to establish interrupt\n");
+ } else {
+ const char * const intrstr = pci_intr_string(pa->pa_pc, pcih);
+ aprint_normal_dev(self, "interrupting at %s\n", intrstr);
+ }
+
+
+ for (size_t i = 0; i < sc->sc_ndevices; i++) {
+ struct xlnor_cs * const cs = &sc->sc_cs[i];
+ KASSERT(cs->cs_region.r_size >= 1024);
+ size_t size = cs->cs_region.r_size >> 10;
+ const char units[] = "KMGTPE";
+ u_int j = 0;
+ for (; size >= 1024; size >>= 10) {
+ j++;
+ }
+ KASSERT(j < sizeof(units));
+ aprint_normal_dev(sc->sc_dev, "cs %u: %zu%cB "
+ "%u-bit %s endian with %smuxed lines\n",
+ cs->cs_number, size, units[j],
+ 8 << __SHIFTOUT(cs->cs_devparm, RMIXLP_NOR_CS_DEVPARM_DW),
+ cs->cs_devparm & RMIXLP_NOR_CS_DEVPARM_LE
+ ? "little" : "big",
+ cs->cs_devparm & RMIXLP_NOR_CS_DEVPARM_MUX
+ ? "" : "non-");
+
+ aprint_debug_dev(sc->sc_dev,
+ "cs %u: devparm=%#x, devtime0=%#x, devtime1=%#x\n",
+ cs->cs_number, cs->cs_devparm,
+ cs->cs_devtime0, cs->cs_devtime1);
+
+ struct rmixl_iobus_attach_args iaa = {
+ .ia_obio_bst = NULL,
+ .ia_obio_bsh = 0,
+ .ia_iobus_bst = &cs->cs_bst,
+ .ia_iobus_addr = 0,
+ .ia_iobus_size = cs->cs_region.r_size,
+ .ia_dev_parm = cs->cs_devparm,
+ .ia_cs = cs->cs_number,
+ };
+
+ config_found(self, &iaa, xlnor_print);
+ }
+}
+
+static int
+xlnor_print(void *aux, const char *pnp)
+{
+ struct rmixl_iobus_attach_args *ia = aux;
+
+ if (pnp != NULL)
+ aprint_normal("%s:", pnp);
+ aprint_normal(" cs %d", ia->ia_cs);
+
+ return UNCONF;
+}
+
+static int
+xlnor_intr(void *v)
+{
+
+ panic("%s(%p)", __func__, v);
+ return 0;
}
Index: src/sys/arch/mips/rmi/rmixlreg.h
diff -u src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.14 src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.15
--- src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.14 Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixlreg.h Wed Dec 28 05:36:11 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixlreg.h,v 1.1.2.14 2011/12/27 19:58:19 matt Exp $ */
+/* $NetBSD: rmixlreg.h,v 1.1.2.15 2011/12/28 05:36:11 matt Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -1462,7 +1462,7 @@
#define RMIXLP_NOR_NCS 8
#define RMIXLP_NOR_CS_BASEADDRESSn(n) _RMIXL_OFFSET(0x40+(n))
#define RMIXLP_NOR_CS_BASELIMITn(n) _RMIXL_OFFSET(0x48+(n))
-#define RMIXLP_NOR_CS_DEVPARAMn(n) _RMIXL_OFFSET(0x50+(n))
+#define RMIXLP_NOR_CS_DEVPARMn(n) _RMIXL_OFFSET(0x50+(n))
#define RMIXLP_NOR_CS_DEVTIME0n(n) _RMIXL_OFFSET(0x58+2*(n))
#define RMIXLP_NOR_CS_DEVTIME1n(n) _RMIXL_OFFSET(0x59+2*(n))
#define RMIXLP_NOR_SYSCTRL _RMIXL_OFFSET(0x68)
@@ -1482,46 +1482,46 @@
// Interface Byte signal Enable.
// 0: Disables programmable data width selection
// 1: Enables programmable data width selection
-#define RMIXLP_NOR_DEVPARAM_BE __BIT(16)
+#define RMIXLP_NOR_CS_DEVPARM_BE __BIT(16)
// Little Endian.
// 0:Big Endian
// 1:Little Endian
-#define RMIXLP_NOR_DEVPARAM_LE __BIT(13)
-#define RMIXLP_NOR_DEVPARAM_DW __BITS(12:11) // Device Data Width
-#define RMIXLP_NOR_DEVPARAM_DW_8_BITS 0
-#define RMIXLP_NOR_DEVPARAM_DW_16_BITS 1
-#define RMIXLP_NOR_DEVPARAM_DW_32_BITS 2
+#define RMIXLP_NOR_CS_DEVPARM_LE __BIT(13)
+#define RMIXLP_NOR_CS_DEVPARM_DW __BITS(12,11) // Device Data Width
+#define RMIXLP_NOR_CS_DEVPARM_DW_8_BITS 0
+#define RMIXLP_NOR_CS_DEVPARM_DW_16_BITS 1
+#define RMIXLP_NOR_CS_DEVPARM_DW_32_BITS 2
// Multiplexed/non-multiplexed device data/address mode
// 0:Non-multiplexed (only valid if field DW is set to 0)
// 1:Multiplexed data and address bus
-#define RMIXLP_NOR_DEVPARAM_MUX __BIT(10)
+#define RMIXLP_NOR_CS_DEVPARM_MUX __BIT(10)
// Wait/Ready signal Polarity
// 0:Wait active high
// 1:Wait active low
-#define RMIXLP_NOR_DEVPARAM_WRP __BIT(9)
+#define RMIXLP_NOR_CS_DEVPARM_WRP __BIT(9)
// Wait/ready signal Write interface Enable.
// Enables/disables wait-acknowledge mode during write cycles.
// 0: Enable device Wait mode. External IO_WAIT_L signal is used.
// 1: Disable Wait mode; external IO_WAIT_L signal is not used.
-#define RMIXLP_NOR_DEVPARAM_WWE __BIT(8)
+#define RMIXLP_NOR_CS_DEVPARM_WWE __BIT(8)
// Wait/Ready signal Read interface Enable.
// Enables/disables wait-acknowledge mode during read cycles.
// 0: Enable device Wait mode. External IO_WAIT_L signal is used.
// 1: Disable Wait mode; external IO_WAIT_L signal is not used.
// This signal is distinct from the RYBY (Ready/Busy) signal,
// which is shared by all Flash devices.
-#define RMIXLP_NOR_DEVPARAM_WRE __BIT(7)
+#define RMIXLP_NOR_CS_DEVPARM_WRE __BIT(7)
// Synchronous Read Data Burst Enabled (when set to 1).
-#define RMIXLP_NOR_DEVPARAM_SRDBE __BIT(5)
+#define RMIXLP_NOR_CS_DEVPARM_SRDBE __BIT(5)
// Word-align Address.
// If set to 1, address bits are word-aligned.
// This allows address bits of a 16-bit Flash device to connect to XLP
// address bits [24:1] instead of [23:0] or the address bits of a 32-bit
// Flash device to connect to XLP address bits [25:2] instead of [23:0].
-#define RMIXLP_NOR_DEVPARAM_WA __BIT(2)
-#define RMIXLP_NOR_DEVPARAM_FLASH_TYPE __BITS(1:0) // Flash Type
-#define RMIXLP_NOR_DEVPARAM_FLASH_TYPE_NOR 0 // NOR Flash
-#define RMIXLP_NOR_DEVPARAM_FLASH_TYPE_ONCHIP 1 // On-chip ROM
+#define RMIXLP_NOR_CS_DEVPARM_WA __BIT(2)
+#define RMIXLP_NOR_CS_DEVPARM_FLASH_TYPE __BITS(1,0) // Flash Type
+#define RMIXLP_NOR_CS_DEVPARM_FLASH_TYPE_NOR 0 // NOR Flash
+#define RMIXLP_NOR_CS_DEVPARM_FLASH_TYPE_ONCHIP 1 // On-chip ROM
// CS to CS timing.
// This field indicates the number of clock cycles from the falling
Index: src/sys/arch/mips/rmi/rmixlvar.h
diff -u src/sys/arch/mips/rmi/rmixlvar.h:1.1.2.22 src/sys/arch/mips/rmi/rmixlvar.h:1.1.2.23
--- src/sys/arch/mips/rmi/rmixlvar.h:1.1.2.22 Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixlvar.h Wed Dec 28 05:36:11 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixlvar.h,v 1.1.2.22 2011/12/27 19:58:19 matt Exp $ */
+/* $NetBSD: rmixlvar.h,v 1.1.2.23 2011/12/28 05:36:11 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -120,15 +120,15 @@ struct rmixl_region {
struct rmixl_config {
struct rmixl_region rc_io;
- struct rmixl_region rc_flash[4]; /* FLASH_BAR */
+ struct rmixl_region rc_flash[RMIXLP_SBC_NFLASH]; /* FLASH_BAR */
struct rmixl_region rc_pci_cfg;
struct rmixl_region rc_pci_ecfg;
struct rmixl_region rc_pci_mem;
struct rmixl_region rc_pci_io;
- struct rmixl_region rc_pci_link_mem[4];
- struct rmixl_region rc_pci_link_io[4];
+ struct rmixl_region rc_pci_link_mem[RMIXLP_SBC_NPCIE_MEM];
+ struct rmixl_region rc_pci_link_io[RMIXLP_SBC_NPCIE_IO];
struct rmixl_region rc_srio_mem;
- struct rmixl_region rc_norflash[8]; /* XLP 8 CS for NOR */
+ struct rmixl_region rc_norflash[RMIXLP_NOR_NCS]; /* XLP */
struct mips_bus_space rc_obio_eb_memt; /* DEVIO -eb */
struct mips_bus_space rc_obio_el_memt; /* DEVIO -el */
struct mips_bus_space rc_iobus_memt; /* Peripherals IO Bus */
@@ -164,9 +164,11 @@ struct rmixl_config {
extern struct rmixl_config rmixl_configuration;
extern const char *rmixl_cpuname;
+extern void rmixl_flash_eb_bus_mem_init(bus_space_tag_t, void *);
+extern void rmixl_flash_el_bus_mem_init(bus_space_tag_t, void *);
+extern void rmixl_iobus_bus_mem_init(bus_space_tag_t, void *);
extern void rmixl_obio_eb_bus_mem_init(bus_space_tag_t, void *);
extern void rmixl_obio_el_bus_mem_init(bus_space_tag_t, void *);
-extern void rmixl_iobus_bus_mem_init(bus_space_tag_t, void *);
extern void rmixl_pci_cfg_el_bus_mem_init(bus_space_tag_t, void *);
extern void rmixl_pci_cfg_eb_bus_mem_init(bus_space_tag_t, void *);
extern void rmixl_pci_ecfg_el_bus_mem_init(bus_space_tag_t, void *);
Added files:
Index: src/sys/arch/mips/rmi/rmixl_flash_eb_space.c
diff -u /dev/null src/sys/arch/mips/rmi/rmixl_flash_eb_space.c:1.1.2.1
--- /dev/null Wed Dec 28 05:36:11 2011
+++ src/sys/arch/mips/rmi/rmixl_flash_eb_space.c Wed Dec 28 05:36:11 2011
@@ -0,0 +1,60 @@
+/* $NetBSD: rmixl_flash_eb_space.c,v 1.1.2.1 2011/12/28 05:36:11 matt Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * bus_space(9) support for Peripherals IO Bus on RMI {XLP,XLR,XLS} chips
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rmixl_flash_eb_space.c,v 1.1.2.1 2011/12/28 05:36:11 matt Exp $");
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/bus.h>
+
+#include <mips/rmi/rmixlreg.h>
+#include <mips/rmi/rmixlvar.h>
+
+#define CHIP rmixl_flash_eb
+#define CHIP_MEM /* defined */
+#define CHIP_ACCESS_SIZE 1
+#define CHIP_BIG_ENDIAN
+
+#define CHIP_V(v) ((struct rmixl_region *)(v))
+#define CHIP_EX_MALLOC_SAFE(v) true
+
+/* MEM region 1 */
+#define CHIP_W1_BUS_START(v) 0
+#define CHIP_W1_BUS_END(v) (CHIP_V(v)->r_size - 1)
+#define CHIP_W1_SYS_START(v) (CHIP_V(v)->r_pbase)
+#define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + CHIP_W1_BUS_END(v))
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
Index: src/sys/arch/mips/rmi/rmixl_flash_el_space.c
diff -u /dev/null src/sys/arch/mips/rmi/rmixl_flash_el_space.c:1.1.2.1
--- /dev/null Wed Dec 28 05:36:11 2011
+++ src/sys/arch/mips/rmi/rmixl_flash_el_space.c Wed Dec 28 05:36:11 2011
@@ -0,0 +1,60 @@
+/* $NetBSD: rmixl_flash_el_space.c,v 1.1.2.1 2011/12/28 05:36:11 matt Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * bus_space(9) support for Peripherals IO Bus on RMI {XLP,XLR,XLS} chips
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rmixl_flash_el_space.c,v 1.1.2.1 2011/12/28 05:36:11 matt Exp $");
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/bus.h>
+
+#include <mips/rmi/rmixlreg.h>
+#include <mips/rmi/rmixlvar.h>
+
+#define CHIP rmixl_flash_el
+#define CHIP_MEM /* defined */
+#define CHIP_ACCESS_SIZE 1
+#define CHIP_LITTLE_ENDIAN
+
+#define CHIP_V(v) ((struct rmixl_region *)(v))
+#define CHIP_EX_MALLOC_SAFE(v) true
+
+/* MEM region 1 */
+#define CHIP_W1_BUS_START(v) 0
+#define CHIP_W1_BUS_END(v) (CHIP_V(v)->r_size - 1)
+#define CHIP_W1_SYS_START(v) (CHIP_V(v)->r_pbase)
+#define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + CHIP_W1_BUS_END(v))
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
