Module Name: src
Committed By: matt
Date: Tue Dec 27 19:58:19 UTC 2011
Modified Files:
src/sys/arch/mips/conf [matt-nb5-mips64]: files.rmixl
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixlreg.h rmixlvar.h
Added Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_cfi_xlnor.c
rmixl_iobus.c rmixl_iobus_space.c rmixl_iobusvar.h
rmixl_nand_iobus.c rmixl_nand_pci.c rmixl_nor_pci.c rmixl_spi_pci.c
Log Message:
Add NOR/NAND (from HEAD)/SPI attachments.
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.14 -r1.1.2.15 src/sys/arch/mips/conf/files.rmixl
cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/mips/rmi/rmixl_cfi_xlnor.c \
src/sys/arch/mips/rmi/rmixl_nand_iobus.c \
src/sys/arch/mips/rmi/rmixl_nand_pci.c \
src/sys/arch/mips/rmi/rmixl_nor_pci.c \
src/sys/arch/mips/rmi/rmixl_spi_pci.c
cvs rdiff -u -r0 -r1.3.8.2 src/sys/arch/mips/rmi/rmixl_iobus.c \
src/sys/arch/mips/rmi/rmixl_iobus_space.c
cvs rdiff -u -r0 -r1.1.14.2 src/sys/arch/mips/rmi/rmixl_iobusvar.h
cvs rdiff -u -r1.1.2.13 -r1.1.2.14 src/sys/arch/mips/rmi/rmixlreg.h
cvs rdiff -u -r1.1.2.21 -r1.1.2.22 src/sys/arch/mips/rmi/rmixlvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/conf/files.rmixl
diff -u src/sys/arch/mips/conf/files.rmixl:1.1.2.14 src/sys/arch/mips/conf/files.rmixl:1.1.2.15
--- src/sys/arch/mips/conf/files.rmixl:1.1.2.14 Sat Dec 24 01:57:53 2011
+++ src/sys/arch/mips/conf/files.rmixl Tue Dec 27 19:58:18 2011
@@ -1,4 +1,4 @@
-# $NetBSD: files.rmixl,v 1.1.2.14 2011/12/24 01:57:53 matt Exp $
+# $NetBSD: files.rmixl,v 1.1.2.15 2011/12/27 19:58:18 matt Exp $
#
# Configuration info for RMI XLP, XLR, XLS
#
@@ -59,6 +59,36 @@ device rmixl_pcix: pcibus
attach rmixl_pcix at obio # XLR
file arch/mips/rmi/rmixl_pcix.c rmixl_pcix needs-flag
+# XLS/XLR Periperal IO Bus to NOR, NAND, and PCMCIA memory controllers
+define xliobus { [cs=-1], [addr=-1], [size=-1], [intr=-1] }
+device xliobus: xliobus
+attach xliobus at obio with xliobus_obio
+file arch/mips/rmi/rmixl_iobus_space.c xliobus_obio
+file arch/mips/rmi/rmixl_iobus.c xliobus_obio
+
+# NAND flash controller
+device xlnand: nandbus
+attach xlnand at xliobus with xlnand_iobus
+attach xlnand at pci with xlnand_pci
+file arch/mips/rmi/rmixl_nand_iobus.c xlnand_iobus
+file arch/mips/rmi/rmixl_nand_pci.c xlnand_pci
+
+# NOR controller (XLP equiv of xliobus but for NOR only).
+device xlnor { [cs=-1] }
+attach xlnor at pci with xlnor_pci
+file arch/mips/rmi/rmixl_nor_pci.c xlnor_pci
+
+device cfi: norbus
+attach cfi at xliobus with cfi_iobus
+attach cfi at xlnor with cfi_xlnor
+file arch/mips/rmi/rmixl_cfi_iobus.c cfi_iobus
+file arch/mips/rmi/rmixl_cfi_xlnor.c cfi_xlnor
+
+# PCMCIA controller
+device xlpcic: pcmciabus
+attach xlpcic at xliobus
+file arch/mips/rmi/rmixl_pcic.c xlpcic
+
# On-chip USB interface
define rmixl_usbi { [addr=-1], [size=-1], [intr=-1] }
device rmixl_usbi: rmixl_usbi
@@ -97,3 +127,8 @@ attach xli2c at obio with xli2c_obio
attach xli2c at pci with xli2c_pci
file arch/mips/rmi/rmixl_i2c_obio.c xli2c_obio
file arch/mips/rmi/rmixl_i2c_pci.c xli2c_pci
+
+# XL SPI controller
+device xlspi: spibus
+attach xlspi at pci with xlspi_pci
+file arch/mips/rmi/rmixl_spi_pci.c xlspi_pci
Index: src/sys/arch/mips/rmi/rmixlreg.h
diff -u src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.13 src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.14
--- src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.13 Sat Dec 24 01:57:54 2011
+++ src/sys/arch/mips/rmi/rmixlreg.h Tue Dec 27 19:58:19 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixlreg.h,v 1.1.2.13 2011/12/24 01:57:54 matt Exp $ */
+/* $NetBSD: rmixlreg.h,v 1.1.2.14 2011/12/27 19:58:19 matt Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -392,9 +392,9 @@
#define RMIXL_SBC_DRAM_CHNBD_DTR(n) _RMIXL_OFFSET(0x010 + (n))
/* DRAM Region Channels B,D Address Translation Regs[0-7] */
#define RMIXL_SBC_DRAM_BRIDGE_CFG _RMIXL_OFFSET(0x18) /* SBC DRAM config reg */
+#define RMIXL_SBC_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */
+#define RMIXL_SBC_FLASH_BAR _RMIXL_OFFSET(0x1a) /* Flash Memory Base Addr reg */
#if defined(MIPS64_XLR)
-#define RMIXLR_SBC_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */
-#define RMIXLR_SBC_FLASH_BAR _RMIXL_OFFSET(0x1a) /* Flash Memory Base Addr reg */
#define RMIXLR_SBC_SRAM_BAR _RMIXL_OFFSET(0x1b) /* SRAM Base Addr reg */
#define RMIXLR_SBC_HTMEM_BAR _RMIXL_OFFSET(0x1c) /* HyperTransport Mem Base Addr reg */
#define RMIXLR_SBC_HTINT_BAR _RMIXL_OFFSET(0x1d) /* HyperTransport Interrupt Base Addr reg */
@@ -408,8 +408,6 @@
#define RMIXLR_SBC_SYS2IO_CREDITS _RMIXL_OFFSET(0x35) /* System Bridge I/O Transaction Credits register */
#endif /* MIPS64_XLR */
#if defined(MIPS64_XLS)
-#define RMIXLS_SBC_IO_BAR _RMIXL_OFFSET(0x19) /* I/O Config Base Addr reg */
-#define RMIXLS_SBC_FLASH_BAR _RMIXL_OFFSET(0x20) /* Flash Memory Base Addr reg */
#define RMIXLS_SBC_PCIE_CFG_BAR _RMIXL_OFFSET(0x40) /* PCI Configuration BAR */
#define RMIXLS_SBC_PCIE_ECFG_BAR _RMIXL_OFFSET(0x41) /* PCI Extended Configuration BAR */
#define RMIXLS_SBC_PCIE_MEM_BAR _RMIXL_OFFSET(0x42) /* PCI Memory region BAR */
@@ -439,6 +437,19 @@
#define RMIXL_ADDR_ERR_BITERR_INT_EN _RMIXL_OFFSET(0x33) /* Bit Error intr enable */
/*
+ * RMIXL_SBC_FLASH_BAR bit defines
+ */
+#define RMIXL_FLASH_BAR_BASE __BITS(31,16) /* phys address bits 39:24 */
+#define RMIXL_FLASH_BAR_TO_BA(r) \
+ (((r) & RMIXL_FLASH_BAR_BASE) << (24 - 16))
+#define RMIXL_FLASH_BAR_MASK __BITS(15,5) /* phys address mask bits 34:24 */
+#define RMIXL_FLASH_BAR_TO_MASK(r) \
+ (((((r) & RMIXL_FLASH_BAR_MASK)) << (24 - 5)) | __BITS(23, 0))
+#define RMIXL_FLASH_BAR_RESV __BITS(4,1) /* (reserved) */
+#define RMIXL_FLASH_BAR_ENB __BIT(0) /* 1=Enable */
+#define RMIXL_FLASH_BAR_MASK_MAX RMIXL_FLASH_BAR_TO_MASK(RMIXL_FLASH_BAR_MASK)
+
+/*
* RMIXL_SBC_DRAM_BAR bit defines
*/
#define RMIXL_DRAM_BAR_BASE_ADDR __BITS(31,16) /* bits 39:24 of Base Address */
@@ -889,6 +900,86 @@
*/
#define RMIXL_GPIO_LOW_PWR_DIS_RESV __BITS(31,9)
+/*
+ * Peripheral I/O bus (Flash/PCMCIA) controller registers
+ */
+#define RMIXL_FLASH_NCS 10 /* number of chip selects */
+#define RMIXL_FLASH_CS_BOOT 0 /* CS0 is boot flash */
+#define RMIXL_FLASH_CS_PCMCIA_CF 6 /* CS6 is PCMCIA compact flash */
+#define RMIXL_FLASH_CSBASE_ADDRn(n) _RMIXL_OFFSET(0x00+(n)) /* CSn Base Address reg */
+#define RMIXL_FLASH_CSADDR_MASKn(n) _RMIXL_OFFSET(0x10+(n)) /* CSn Address Mask reg */
+#define RMIXL_FLASH_CSDEV_PARMn(n) _RMIXL_OFFSET(0x20+(n)) /* CSn Device Parameter reg */
+#define RMIXL_FLASH_CSTIME_PARMAn(n) _RMIXL_OFFSET(0x30+(n)) /* CSn Timing Parameters A reg */
+#define RMIXL_FLASH_CSTIME_PARMBn(n) _RMIXL_OFFSET(0x40+(n)) /* CSn Timing Parameters B reg */
+#define RMIXL_FLASH_INT_MASK _RMIXL_OFFSET(0x50) /* Flash Interrupt Mask reg */
+#define RMIXL_FLASH_INT_STATUS _RMIXL_OFFSET(0x60) /* Flash Interrupt Status reg */
+#define RMIXL_FLASH_ERROR_STATUS _RMIXL_OFFSET(0x70) /* Flash Error Status reg */
+#define RMIXL_FLASH_ERROR_ADDR _RMIXL_OFFSET(0x80) /* Flash Error Address reg */
+
+/*
+ * RMIXL_FLASH_CSDEV_PARMn bits
+ */
+#define RMIXL_FLASH_CSDEV_RESV __BITS(31,16)
+#define RMIXL_FLASH_CSDEV_BFN __BIT(15) /* Boot From Nand
+ * 0=Boot from NOR or
+ * PCCard Type 1 Flash
+ * 1=Boot from NAND
+ */
+#define RMIXL_FLASH_CSDEV_NANDEN __BIT(14) /* NAND Flash Enable
+ * 0=NOR
+ * 1=NAND
+ */
+#define RMIXL_FLASH_CSDEV_ADVTYPE __BIT(13) /* Add Valid Sensing Type
+ * 0=level
+ * 1=pulse
+ */
+#define RMIXL_FLASH_CSDEV_PARITY_TYPE __BIT(12) /* Parity Type
+ * 0=even
+ * 1=odd
+ */
+#define RMIXL_FLASH_CSDEV_PARITY_EN __BIT(11) /* Parity Enable */
+#define RMIXL_FLASH_CSDEV_GENIF_EN __BIT(10) /* Generic PLD/FPGA interface mode
+ * if this bit is set, then
+ * GPIO[13:10] cannot be used
+ * for interrupts
+ */
+#define RMIXL_FLASH_CSDEV_PCMCIA_EN __BIT(9) /* PCMCIA Interface mode */
+#define RMIXL_FLASH_CSDEV_DWIDTH __BITS(8,7) /* Data Bus Width:
+ * 00: 8 bit
+ * 01: 16 bit
+ * 10: 32 bit
+ * 11: 8 bit
+ */
+#define RMIXL_FLASH_CSDEV_DWIDTH_SHFT 7
+#define RMIXL_FLASH_CSDEV_MX_ADDR __BIT(6) /* Multiplexed Address
+ * 0: non-muxed
+ * AD[31:24] = Data,
+ * AD[23:0] = Addr
+ * 1: muxed
+ * External latch required
+ */
+#define RMIXL_FLASH_CSDEV_WAIT_POL __BIT(5) /* WAIT polarity
+ * 0: Active high
+ * 1: Active low
+ */
+#define RMIXL_FLASH_CSDEV_WAIT_EN __BIT(4) /* Enable External WAIT Ack mode */
+#define RMIXL_FLASH_CSDEV_BURST __BITS(3,1) /* Burst Length:
+ * 000: 2x
+ * 001: 4x
+ * 010: 8x
+ * 011: 16x
+ * 100: 32x
+ */
+#define RMIXL_FLASH_CSDEV_BURST_SHFT 1
+#define RMIXL_FLASH_CSDEV_BURST_EN __BITS(0) /* Burst Enable */
+
+
+/*
+ * NAND Flash Memory Control registers
+ */
+#define RMIXL_NAND_CLEn(n) _RMIXL_OFFSET(0x90+(n)) /* CSn 8-bit CLE command value reg */
+#define RMIXL_NAND_ALEn(n) _RMIXL_OFFSET(0xa0+(n)) /* CSn 8-bit ALE address phase reg */
+
/*
* PCIE Interface Controller registers
@@ -1367,6 +1458,158 @@
#define RMIXLP_SM_POWER_ON_RESET_CFG_NORSP __BIT(4)
#define RMIXLP_SM_POWER_ON_RESET_CFG_BD __BITS(3,0)
+#define RMIXLP_NOR_PCITAG _RMIXL_PCITAG(0,7,0)
+#define RMIXLP_NOR_NCS 8
+#define RMIXLP_NOR_CS_BASEADDRESSn(n) _RMIXL_OFFSET(0x40+(n))
+#define RMIXLP_NOR_CS_BASELIMITn(n) _RMIXL_OFFSET(0x48+(n))
+#define RMIXLP_NOR_CS_DEVPARAMn(n) _RMIXL_OFFSET(0x50+(n))
+#define RMIXLP_NOR_CS_DEVTIME0n(n) _RMIXL_OFFSET(0x58+2*(n))
+#define RMIXLP_NOR_CS_DEVTIME1n(n) _RMIXL_OFFSET(0x59+2*(n))
+#define RMIXLP_NOR_SYSCTRL _RMIXL_OFFSET(0x68)
+#define RMIXLP_NOR_BYTESWAP _RMIXL_OFFSET(0x69)
+#define RMIXLP_NOR_ERRLOG0 _RMIXL_OFFSET(0x6a)
+#define RMIXLP_NOR_ERRLOG1 _RMIXL_OFFSET(0x6b)
+#define RMIXLP_NOR_ERRLOG2 _RMIXL_OFFSET(0x6c)
+#define RMIXLP_NOR_ID_TIMEOUT_VAL _RMIXL_OFFSET(0x6d)
+#define RMIXLP_NOR_INSTAT _RMIXL_OFFSET(0x6e)
+#define RMIXLP_NOR_INTEN _RMIXL_OFFSET(0x6f)
+#define RMIXLP_NOR_STATUS _RMIXL_OFFSET(0x70)
+
+#define RMIXLP_NOR_CS_ADDRESS_TO_PA(r) ((uint64_t)(r) << 8)
+#define RMIXLP_NOR_PA_TO_CS_ADDRESS(r) ((uint64_t)(r) >> 8)
+#define RMIXLP_NOR_CS_SIZE(b,l) ((l)-(b)+256)
+
+ // Interface Byte signal Enable.
+ // 0: Disables programmable data width selection
+ // 1: Enables programmable data width selection
+#define RMIXLP_NOR_DEVPARAM_BE __BIT(16)
+ // Little Endian.
+ // 0:Big Endian
+ // 1:Little Endian
+#define RMIXLP_NOR_DEVPARAM_LE __BIT(13)
+#define RMIXLP_NOR_DEVPARAM_DW __BITS(12:11) // Device Data Width
+#define RMIXLP_NOR_DEVPARAM_DW_8_BITS 0
+#define RMIXLP_NOR_DEVPARAM_DW_16_BITS 1
+#define RMIXLP_NOR_DEVPARAM_DW_32_BITS 2
+ // Multiplexed/non-multiplexed device data/address mode
+ // 0:Non-multiplexed (only valid if field DW is set to 0)
+ // 1:Multiplexed data and address bus
+#define RMIXLP_NOR_DEVPARAM_MUX __BIT(10)
+ // Wait/Ready signal Polarity
+ // 0:Wait active high
+ // 1:Wait active low
+#define RMIXLP_NOR_DEVPARAM_WRP __BIT(9)
+ // Wait/ready signal Write interface Enable.
+ // Enables/disables wait-acknowledge mode during write cycles.
+ // 0: Enable device Wait mode. External IO_WAIT_L signal is used.
+ // 1: Disable Wait mode; external IO_WAIT_L signal is not used.
+#define RMIXLP_NOR_DEVPARAM_WWE __BIT(8)
+ // Wait/Ready signal Read interface Enable.
+ // Enables/disables wait-acknowledge mode during read cycles.
+ // 0: Enable device Wait mode. External IO_WAIT_L signal is used.
+ // 1: Disable Wait mode; external IO_WAIT_L signal is not used.
+ // This signal is distinct from the RYBY (Ready/Busy) signal,
+ // which is shared by all Flash devices.
+#define RMIXLP_NOR_DEVPARAM_WRE __BIT(7)
+ // Synchronous Read Data Burst Enabled (when set to 1).
+#define RMIXLP_NOR_DEVPARAM_SRDBE __BIT(5)
+ // Word-align Address.
+ // If set to 1, address bits are word-aligned.
+ // This allows address bits of a 16-bit Flash device to connect to XLP
+ // address bits [24:1] instead of [23:0] or the address bits of a 32-bit
+ // Flash device to connect to XLP address bits [25:2] instead of [23:0].
+#define RMIXLP_NOR_DEVPARAM_WA __BIT(2)
+#define RMIXLP_NOR_DEVPARAM_FLASH_TYPE __BITS(1:0) // Flash Type
+#define RMIXLP_NOR_DEVPARAM_FLASH_TYPE_NOR 0 // NOR Flash
+#define RMIXLP_NOR_DEVPARAM_FLASH_TYPE_ONCHIP 1 // On-chip ROM
+
+ // CS to CS timing.
+ // This field indicates the number of clock cycles from the falling
+ // edge of IO_CSn to the next falling edge of IO_CSn, where n = 0-7.
+#define RMIXLP_NOR_DEVTIME0_CS_TO_CS __BITS(31,28)
+
+ // WE to CS timing.
+ // This field indicates the number of clock cycles from the rising
+ // edge of IO_WE_L to the rising edge of IO_CSn_L.
+#define RMIXLP_NOR_DEVTIME0_WE_TO_CS __BITS(27,24)
+
+ // OE to CS timing.
+ // This field indicates the number of clock cycles from the rising
+ // edge of IO_OE_L to the rising edge of IO_CSn_L.
+#define RMIXLP_NOR_DEVTIME0_OE_TO_CS __BITS(23,22)
+
+ // CS to WE timing.
+ // This field indicates the number of clock cycles from the falling
+ // edge of IO_CSn_L to the falling edge of IO_WE_L
+#define RMIXLP_NOR_DEVTIME0_CS_TO_WE __BITS(21,19)
+
+ // CS to OE timing.
+ // This field indicates the number of clock cycles from the falling
+ // edge of IO_CSn_L to the falling edge of IO_OE_L.
+#define RMIXLP_NOR_DEVTIME0_CS_TO_OE __BITS(18,16)
+
+ // Wait/Ready to Data timing.
+ // This field indicates the number of clock cycles from the falling
+ // edge of IO_WE_L to when data is available on a write, or the
+ // falling edge of IO_OE_L to when date is available on a read.
+#define RMIXLP_NOR_DEVTIME0_WAIT_TO_DATA __BITS(15,11)
+
+ // OE to Wait timing.
+ // This field indicates the IO_WE_L to wait time on a write,
+ // or the IO_OE_L to wait time on a read.
+#define RMIXLP_NOR_DEVTIME0_OE_TO_WAIT __BITS(10,6)
+
+ // ALE to CS timing.
+ // This field indicates the number of clock cycles from the falling
+ // edge of IO_ALE to the falling edge of IO_CSn_L. This field is
+ // encoded as follows:
+#define RMIXLP_NOR_DEVTIME0_ALE_TO_CS ___BITS(5,3)
+ // 000: IO_CSn_L is one cycle ahead of IO_ALE.
+#define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_AHEAD1 0
+ // 001: IO_CSn_L is aligned with IO_ALE.
+#define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_ALIGNED 1
+ // 010-111: IO_ALE is ahead of IO_CSn_L.
+#define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND1 2
+#define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND2 3
+#define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND3 4
+#define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND4 5
+#define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND5 6
+#define RMIXLP_NOR_DEVTIME0_ALE_TO_CS_BEHIND6 7
+
+ // ALE pulse width.
+ // This field indicates the number of clock cycles from the falling
+ // edge of IO_ALE to the rising edge of IO_ALE.
+#define RMIXLP_NOR_DEVTIME0_ALE_WIDTH __BITS(2,0)
+
+#define RMIXLP_NOR_DEVTIME1_WAIT_TIMEOUT __BITS(26,12)
+ // Wait Timeout.
+ // If the Interrupt is an error, the Enable bit is set.
+
+ // RDY/BSY signal Polarity:
+ // 0:Ready low, busy high
+ // 1:Ready high, busy low
+ // This signal is shared by all Flash devices. If any of the devices
+ // puts the signal into the busy state, this signal will indicate
+ // not-ready (busy) status.
+#define RMIXLP_NOR_SYSCTRL_RDYBSY_POL __BIT(1)
+
+ // Interconnect Timeout Enable (if set to 1).
+#define RMIXLP_NOR_SYSCTRL_ITE __BIT(0)
+
+ // RDY/BSY pin transition, if set to 1.
+#define RMIXLP_NOR_INTSTAT_RDYBSY __BIT(0)
+
+ // Error Log. Setting this bit enables error logging.
+#define RMIXLP_NOR_INTEN_EL __BIT(1)
+ // RYBY Interrupt Enable. Setting this bit enables NOR Flash interrupts.
+#define RMIXLP_NOR_INTEN_RDYBSY __BIT(0)
+
+ // RDY/BSY Status. 1: NOR device is ready.
+#define RMIXLP_NOR_STATUS_RDYBSY __BIT(0)
+#define RMIXLP_NAND_PCITAG _RMIXL_PCITAG(0,7,1)
+
+#define RMIXLP_SPI_PCITAG _RMIXL_PCITAG(0,7,2)
+
#define RMIXLP_MMC_PCITAG _RMIXL_PCITAG(0,7,3)
#define RMIXLP_MMC_SLOTSIZE _RMIXL_OFFSET(0x40)
Index: src/sys/arch/mips/rmi/rmixlvar.h
diff -u src/sys/arch/mips/rmi/rmixlvar.h:1.1.2.21 src/sys/arch/mips/rmi/rmixlvar.h:1.1.2.22
--- src/sys/arch/mips/rmi/rmixlvar.h:1.1.2.21 Sat Dec 24 01:57:54 2011
+++ src/sys/arch/mips/rmi/rmixlvar.h Tue Dec 27 19:58:19 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixlvar.h,v 1.1.2.21 2011/12/24 01:57:54 matt Exp $ */
+/* $NetBSD: rmixlvar.h,v 1.1.2.22 2011/12/27 19:58:19 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -128,6 +128,7 @@ struct rmixl_config {
struct rmixl_region rc_pci_link_mem[4];
struct rmixl_region rc_pci_link_io[4];
struct rmixl_region rc_srio_mem;
+ struct rmixl_region rc_norflash[8]; /* XLP 8 CS for NOR */
struct mips_bus_space rc_obio_eb_memt; /* DEVIO -eb */
struct mips_bus_space rc_obio_el_memt; /* DEVIO -el */
struct mips_bus_space rc_iobus_memt; /* Peripherals IO Bus */
Added files:
Index: src/sys/arch/mips/rmi/rmixl_cfi_xlnor.c
diff -u /dev/null src/sys/arch/mips/rmi/rmixl_cfi_xlnor.c:1.1.2.1
--- /dev/null Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixl_cfi_xlnor.c Tue Dec 27 19:58:19 2011
@@ -0,0 +1,68 @@
+/*-
+ * Copyright (c) 2011 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: rmixl_cfi_xlnor.c,v 1.1.2.1 2011/12/27 19:58:19 matt Exp $");
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/bus.h>
+
+#include <dev/nor/nor.h>
+#include <dev/nor/cfi.h>
+
+#include "locators.h"
+
+static int cfi_xlnor_match(device_t, cfdata_t, void *);
+static void cfi_xlnor_attach(device_t, device_t, void *);
+
+struct cfi_xlnor_softc {
+ device_t sc_dev;
+ device_t sc_nordev;
+ struct cfi sc_cfi;
+ bus_addr_t sc_addr;
+ bus_size_t sc_size;
+ struct nor_interface sc_nor_if;
+};
+
+CFATTACH_DECL_NEW(cfi_xlnor, sizeof(struct cfi_xlnor_softc),
+ cfi_xlnor_match, cfi_xlnor_attach, 0, 0);
+
+static int
+cfi_xlnor_match(device_t parent, cfdata_t cf, void *aux)
+{
+ return 0;
+}
+
+static void
+cfi_xlnor_attach(device_t parent, device_t self, void *aux)
+{
+ aprint_normal("\n");
+}
Index: src/sys/arch/mips/rmi/rmixl_nand_iobus.c
diff -u /dev/null src/sys/arch/mips/rmi/rmixl_nand_iobus.c:1.1.2.1
--- /dev/null Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixl_nand_iobus.c Tue Dec 27 19:58:19 2011
@@ -0,0 +1,411 @@
+/* $NetBSD: rmixl_nand_iobus.c,v 1.1.2.1 2011/12/27 19:58:19 matt Exp $ */
+
+/*-
+ * Copyright (c) 2010 Department of Software Engineering,
+ * University of Szeged, Hungary
+ * Copyright (c) 2010 Adam Hoka <[email protected]>
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by the Department of Software Engineering, University of Szeged, Hungary
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Device driver for the RMI XLS NAND controller
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rmixl_nand_iobus.c,v 1.1.2.1 2011/12/27 19:58:19 matt Exp $");
+
+#include "opt_flash.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/cdefs.h>
+#include <sys/device.h>
+#include <sys/endian.h>
+
+#include <sys/bus.h>
+
+#include <mips/rmi/rmixlreg.h>
+#include <mips/rmi/rmixlvar.h>
+#include <mips/rmi/rmixl_iobusvar.h>
+#include <mips/rmi/rmixl_intr.h>
+
+#include <dev/nand/nand.h>
+#include <dev/nand/onfi.h>
+
+
+static int xlnand_iobus_match(device_t, cfdata_t, void *);
+static void xlnand_iobus_attach(device_t, device_t, void *);
+static int xlnand_iobus_detach(device_t, int);
+static void xlnand_command(device_t, uint8_t);
+static void xlnand_address(device_t, uint8_t);
+static void xlnand_busy(device_t);
+static void xlnand_read_1(device_t, uint8_t *);
+static void xlnand_write_1(device_t, uint8_t);
+static void xlnand_read_2(device_t, uint16_t *);
+static void xlnand_write_2(device_t, uint16_t);
+static void xlnand_read_buf(device_t, void *, size_t);
+static void xlnand_write_buf(device_t, const void *, size_t);
+
+
+struct xlnand_softc {
+ device_t sc_dev;
+ device_t sc_nanddev;
+ struct iobus_softc *sc_iobus_sc;
+
+ int sc_cs; /* chip select index */
+ int sc_buswidth; /* in bytes */
+
+ struct nand_interface sc_nand_if;
+
+ bus_space_tag_t sc_obio_bst;
+ bus_space_handle_t sc_obio_bsh;
+ u_long sc_cmd_reg;
+ u_long sc_addr_reg;
+
+ bus_addr_t sc_iobus_addr;
+ bus_size_t sc_iobus_size;
+ bus_space_tag_t sc_iobus_bst;
+ bus_space_handle_t sc_iobus_bsh;
+ u_long sc_data_reg;
+
+};
+
+CFATTACH_DECL_NEW(xlnand_iobus, sizeof(struct xlnand_softc),
+ xlnand_iobus_match, xlnand_iobus_attach, xlnand_iobus_detach, NULL);
+
+static int
+xlnand_iobus_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct rmixl_iobus_attach_args *ia = aux;
+ bus_space_handle_t bsh;
+ volatile uint32_t *vaddr;
+ int err;
+ int rv;
+
+ if ((ia->ia_dev_parm & RMIXL_FLASH_CSDEV_NANDEN) == 0)
+ return 0; /* not NAND */
+
+ /* NAND on XLP attaches differently */
+ if (cpu_rmixlp(mips_options.mips_cpu)) {
+ return 0;
+ }
+
+ if (! cpu_rmixls(mips_options.mips_cpu)) {
+ return 0;
+ }
+
+ /*
+ * probe for NAND -- this may be redundant
+ * if the device isn't there, the NANDEN test (above)
+ * should have failed
+ */
+ err = bus_space_map(ia->ia_iobus_bst, ia->ia_iobus_addr,
+ sizeof(uint32_t), 0, &bsh);
+ if (err != 0) {
+ aprint_debug("%s: bus_space_map err %d, "
+ "iobus space addr %#" PRIxBUSADDR "\n",
+ __func__, err, ia->ia_iobus_addr);
+ return 0;
+ }
+
+ vaddr = bus_space_vaddr(ia->ia_iobus_bst, bsh);
+ rv = rmixl_probe_4(vaddr);
+ if (rv == 0)
+ aprint_debug("%s: rmixl_probe_4 failed, vaddr %p\n",
+ __func__, vaddr);
+
+ bus_space_unmap(ia->ia_iobus_bst, bsh, sizeof(uint32_t));
+
+ return rv;
+}
+
+static void
+xlnand_iobus_attach(device_t parent, device_t self, void *aux)
+{
+ struct xlnand_softc *sc = device_private(self);
+ sc->sc_iobus_sc = device_private(parent);
+ struct rmixl_iobus_attach_args *ia = aux;
+ uint32_t val;
+ int err;
+
+ aprint_normal("\n");
+
+ sc->sc_dev = self;
+ sc->sc_obio_bst = ia->ia_obio_bst;
+ sc->sc_obio_bsh = ia->ia_obio_bsh;
+ sc->sc_iobus_bst = ia->ia_iobus_bst;
+ sc->sc_iobus_addr = ia->ia_iobus_addr;
+ sc->sc_iobus_size = sizeof(uint32_t);
+ sc->sc_cs = ia->ia_cs;
+
+ sc->sc_cmd_reg = RMIXL_NAND_CLEn(ia->ia_cs);
+ sc->sc_addr_reg = RMIXL_NAND_ALEn(ia->ia_cs);
+
+ aprint_debug_dev(self, "CS#%d cstime_parma %#x, cstime_parmb %#x\n",
+ ia->ia_cs,
+ bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_FLASH_CSTIME_PARMAn(ia->ia_cs)),
+ bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_FLASH_CSTIME_PARMBn(ia->ia_cs)));
+
+ err = bus_space_map(sc->sc_iobus_bst, sc->sc_iobus_addr,
+ sc->sc_iobus_size, 0, &sc->sc_iobus_bsh);
+ if (err != 0) {
+ aprint_error_dev(self,
+ "bus space map err %d, iobus space\n", err);
+ return;
+ }
+
+ /*
+ * determine buswidth
+ */
+ val = ia->ia_dev_parm;
+ val &= RMIXL_FLASH_CSDEV_DWIDTH;
+ val >>= RMIXL_FLASH_CSDEV_DWIDTH_SHFT;
+ switch(val) {
+ case 0: /* FALLTHROUGH */
+ case 3:
+ sc->sc_buswidth = 1; /* 8 bit */
+ break;
+ case 1:
+ sc->sc_buswidth = 2; /* 16 bit */
+ break;
+ case 2:
+ sc->sc_buswidth = 4; /* 32 bit */
+ break;
+ }
+ aprint_debug_dev(self, "bus width %d bits\n", 8 * sc->sc_buswidth);
+
+ nand_init_interface(&sc->sc_nand_if);
+
+ sc->sc_nand_if.command = xlnand_command;
+ sc->sc_nand_if.address = xlnand_address;
+ sc->sc_nand_if.read_buf_1 = xlnand_read_buf;
+ sc->sc_nand_if.read_buf_2 = xlnand_read_buf;
+ sc->sc_nand_if.read_1 = xlnand_read_1;
+ sc->sc_nand_if.read_2 = xlnand_read_2;
+ sc->sc_nand_if.write_buf_1 = xlnand_write_buf;
+ sc->sc_nand_if.write_buf_2 = xlnand_write_buf;
+ sc->sc_nand_if.write_1 = xlnand_write_1;
+ sc->sc_nand_if.write_2 = xlnand_write_2;
+ sc->sc_nand_if.busy = xlnand_busy;
+
+ sc->sc_nand_if.ecc.necc_code_size = 3;
+ sc->sc_nand_if.ecc.necc_block_size = 256;
+
+ /*
+ * reset to get NAND into known state
+ */
+ xlnand_command(self, ONFI_RESET);
+ xlnand_busy(self);
+
+ if (! pmf_device_register1(self, NULL, NULL, NULL))
+ aprint_error_dev(self, "couldn't establish power handler\n");
+
+ sc->sc_nanddev = nand_attach_mi(&sc->sc_nand_if, self);
+}
+
+static int
+xlnand_iobus_detach(device_t self, int flags)
+{
+ struct xlnand_softc *sc = device_private(self);
+ int rv = 0;
+
+ pmf_device_deregister(self);
+
+ if (sc->sc_nanddev != NULL)
+ rv = config_detach(sc->sc_nanddev, flags);
+
+ bus_space_unmap(sc->sc_iobus_bst, sc->sc_iobus_bsh, sc->sc_iobus_size);
+
+ return rv;
+}
+
+static void
+xlnand_command(device_t self, uint8_t command)
+{
+ struct xlnand_softc *sc = device_private(self);
+
+ bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ sc->sc_cmd_reg, command);
+}
+
+static void
+xlnand_address(device_t self, uint8_t address)
+{
+ struct xlnand_softc *sc = device_private(self);
+
+ bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ sc->sc_addr_reg, address);
+}
+
+static void
+xlnand_busy(device_t self)
+{
+ struct xlnand_softc *sc = device_private(self);
+ uint32_t istatus;
+
+ for(u_int count=100000; count--;) {
+ istatus = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_FLASH_INT_STATUS);
+ if ((istatus & __BIT(8)) != 0)
+ return;
+ DELAY(1);
+ }
+#ifdef DEBUG
+ printf("%s: timed out, istatus=%#x\n", __func__, istatus);
+#ifdef DDB
+ Debugger();
+#endif
+#endif
+}
+
+static void
+xlnand_read_1(device_t self, uint8_t *data)
+{
+ struct xlnand_softc *sc = device_private(self);
+
+ *data = bus_space_read_1(sc->sc_iobus_bst, sc->sc_iobus_bsh, 0);
+}
+
+static void
+xlnand_write_1(device_t self, uint8_t data)
+{
+ struct xlnand_softc *sc = device_private(self);
+
+ bus_space_write_1(sc->sc_iobus_bst, sc->sc_iobus_bsh, 0, data);
+}
+
+static void
+xlnand_read_2(device_t self, uint16_t *data)
+{
+ struct xlnand_softc *sc = device_private(self);
+
+ *data = bus_space_read_2(sc->sc_iobus_bst, sc->sc_iobus_bsh, 0);
+}
+
+static void
+xlnand_write_2(device_t self, uint16_t data)
+{
+ struct xlnand_softc *sc = device_private(self);
+
+ bus_space_write_2(sc->sc_iobus_bst, sc->sc_iobus_bsh, 0, data);
+}
+
+static void
+xlnand_read_buf(device_t self, void *buf, size_t len)
+{
+ struct xlnand_softc *sc = device_private(self);
+ uintptr_t addr = (uintptr_t)buf;
+ size_t sz;
+
+ /* leading byte alignment */
+ if ((len >= 1) && ((addr & 1) != 0)) {
+ *((uint8_t *)addr) = bus_space_read_1(sc->sc_iobus_bst,
+ sc->sc_iobus_bsh, 0);
+ addr += 1;
+ len -= 1;
+ }
+
+ /* leading short alignment */
+ if ((len >= 2) && ((addr & 2) != 0)) {
+ *((uint16_t *)addr) = bus_space_read_2(sc->sc_iobus_bst,
+ sc->sc_iobus_bsh, 0);
+ addr += 2;
+ len -= 2;
+ }
+
+ /* word alignment */
+ sz = len >> 2;
+ if (sz != 0) {
+ bus_space_read_multi_4(sc->sc_iobus_bst, sc->sc_iobus_bsh,
+ 0, (uint32_t *)addr, sz);
+ sz <<= 2;
+ addr += sz;
+ len -= sz;
+ }
+
+ /* trailing short alignment */
+ if (len >= 2) {
+ *((uint16_t *)addr) = bus_space_read_2(sc->sc_iobus_bst,
+ sc->sc_iobus_bsh, 0);
+ addr += 2;
+ len -= 2;
+ }
+
+ /* trailing byte alignment */
+ if (len != 0)
+ *((uint8_t *)addr) = bus_space_read_1(sc->sc_iobus_bst,
+ sc->sc_iobus_bsh, 0);
+}
+
+static void
+xlnand_write_buf(device_t self, const void *buf, size_t len)
+{
+ struct xlnand_softc *sc = device_private(self);
+ uintptr_t addr = (uintptr_t)buf;
+ size_t sz;
+
+ /* leading byte alignment */
+ if ((len >= 1) && ((addr & 1) != 0)) {
+ bus_space_write_1(sc->sc_iobus_bst, sc->sc_iobus_bsh, 0,
+ *((uint8_t *)addr));
+ addr += 1;
+ len -= 1;
+ }
+
+ /* leading short alignment */
+ if ((len >= 2) && ((addr & 2) != 0)) {
+ bus_space_write_2(sc->sc_iobus_bst, sc->sc_iobus_bsh, 0,
+ *((uint16_t *)addr));
+ addr += 2;
+ len -= 2;
+ }
+
+ /* word alignment */
+ sz = len >> 2;
+ if (sz != 0) {
+ bus_space_write_multi_4(sc->sc_iobus_bst, sc->sc_iobus_bsh,
+ 0, (uint32_t *)addr, sz);
+ sz <<= 2;
+ addr += sz;
+ len -= sz;
+ }
+
+ /* trailing short alignment */
+ if (len >= 2) {
+ bus_space_write_2(sc->sc_iobus_bst, sc->sc_iobus_bsh, 0,
+ *((uint16_t *)addr));
+ addr += 2;
+ len -= 2;
+ }
+
+ /* trailing byte alignment */
+ if (len != 0)
+ bus_space_write_1(sc->sc_iobus_bst, sc->sc_iobus_bsh, 0,
+ *((uint8_t *)addr));
+}
Index: src/sys/arch/mips/rmi/rmixl_nand_pci.c
diff -u /dev/null src/sys/arch/mips/rmi/rmixl_nand_pci.c:1.1.2.1
--- /dev/null Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixl_nand_pci.c Tue Dec 27 19:58:19 2011
@@ -0,0 +1,96 @@
+/*-
+ * Copyright (c) 2011 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: rmixl_nand_pci.c,v 1.1.2.1 2011/12/27 19:58:19 matt Exp $");
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/bus.h>
+
+#include "locators.h"
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/nand/nand.h>
+#include <dev/nand/onfi.h>
+
+#include <mips/rmi/rmixlreg.h>
+#include <mips/rmi/rmixlvar.h>
+
+#include "locators.h"
+
+static int xlnand_pci_match(device_t, cfdata_t, void *);
+static void xlnand_pci_attach(device_t, device_t, void *);
+
+struct xlnand_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+};
+
+CFATTACH_DECL_NEW(xlnand_pci, sizeof(struct xlnand_softc),
+ xlnand_pci_match, xlnand_pci_attach, NULL, NULL);
+
+static int
+xlnand_pci_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct pci_attach_args * const pa = aux;
+
+ if (pa->pa_id == PCI_ID_CODE(PCI_VENDOR_NETLOGIC, PCI_PRODUCT_NETLOGIC_XLP_NAND))
+ return 1;
+
+ return 0;
+}
+
+static void
+xlnand_pci_attach(device_t parent, device_t self, void *aux)
+{
+ struct rmixl_config * const rcp = &rmixl_configuration;
+ struct pci_attach_args * const pa = aux;
+ struct xlnand_softc * const sc = device_private(self);
+ // struct norbus_attach_args iba;
+
+ sc->sc_dev = self;
+ sc->sc_bst = &rcp->rc_pci_ecfg_eb_memt;
+
+ /*
+ * Why isn't this accessible via a BAR?
+ */
+ if (bus_space_subregion(sc->sc_bst, rcp->rc_pci_ecfg_eb_memh,
+ pa->pa_tag | 0x100, 0, &sc->sc_bsh)) {
+ aprint_error(": can't map registers\n");
+ return;
+ }
+
+ aprint_normal(": XLP NAND Controller\n");
+}
Index: src/sys/arch/mips/rmi/rmixl_nor_pci.c
diff -u /dev/null src/sys/arch/mips/rmi/rmixl_nor_pci.c:1.1.2.1
--- /dev/null Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixl_nor_pci.c Tue Dec 27 19:58:19 2011
@@ -0,0 +1,96 @@
+/*-
+ * Copyright (c) 2011 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: rmixl_nor_pci.c,v 1.1.2.1 2011/12/27 19:58:19 matt Exp $");
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/bus.h>
+
+#include "locators.h"
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/nor/nor.h>
+#include <dev/nor/cfi.h>
+
+#include <mips/rmi/rmixlreg.h>
+#include <mips/rmi/rmixlvar.h>
+
+#include "locators.h"
+
+static int xlnor_pci_match(device_t, cfdata_t, void *);
+static void xlnor_pci_attach(device_t, device_t, void *);
+
+struct xlnor_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+};
+
+CFATTACH_DECL_NEW(xlnor_pci, sizeof(struct xlnor_softc),
+ xlnor_pci_match, xlnor_pci_attach, NULL, NULL);
+
+static int
+xlnor_pci_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct pci_attach_args * const pa = aux;
+
+ if (pa->pa_id == PCI_ID_CODE(PCI_VENDOR_NETLOGIC, PCI_PRODUCT_NETLOGIC_XLP_NOR))
+ return 1;
+
+ return 0;
+}
+
+static void
+xlnor_pci_attach(device_t parent, device_t self, void *aux)
+{
+ struct rmixl_config * const rcp = &rmixl_configuration;
+ struct pci_attach_args * const pa = aux;
+ struct xlnor_softc * const sc = device_private(self);
+ // struct norbus_attach_args iba;
+
+ sc->sc_dev = self;
+ sc->sc_bst = &rcp->rc_pci_ecfg_eb_memt;
+
+ /*
+ * Why isn't this accessible via a BAR?
+ */
+ if (bus_space_subregion(sc->sc_bst, rcp->rc_pci_ecfg_eb_memh,
+ pa->pa_tag | 0x100, 0, &sc->sc_bsh)) {
+ aprint_error(": can't map registers\n");
+ return;
+ }
+
+ aprint_normal(": XLP NOR Controller\n");
+}
Index: src/sys/arch/mips/rmi/rmixl_spi_pci.c
diff -u /dev/null src/sys/arch/mips/rmi/rmixl_spi_pci.c:1.1.2.1
--- /dev/null Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixl_spi_pci.c Tue Dec 27 19:58:19 2011
@@ -0,0 +1,100 @@
+/*-
+ * Copyright (c) 2011 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: rmixl_spi_pci.c,v 1.1.2.1 2011/12/27 19:58:19 matt Exp $");
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/bus.h>
+
+#include "locators.h"
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <mips/rmi/rmixlreg.h>
+#include <mips/rmi/rmixlvar.h>
+
+#include "locators.h"
+
+#ifdef DEBUG
+int xlspi_debug = 0;
+#define DPRINTF(x, ...) do { if (xlspi_debug) printf(x, ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(x)
+#endif
+
+static int xlspi_pci_match(device_t, cfdata_t, void *);
+static void xlspi_pci_attach(device_t, device_t, void *);
+
+struct xlspi_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+};
+
+CFATTACH_DECL_NEW(xlspi_pci, sizeof(struct xlspi_softc),
+ xlspi_pci_match, xlspi_pci_attach, NULL, NULL);
+
+static int
+xlspi_pci_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct pci_attach_args * const pa = aux;
+
+ if (pa->pa_id == PCI_ID_CODE(PCI_VENDOR_NETLOGIC, PCI_PRODUCT_NETLOGIC_XLP_SPI))
+ return 1;
+
+ return 0;
+}
+
+static void
+xlspi_pci_attach(device_t parent, device_t self, void *aux)
+{
+ struct rmixl_config * const rcp = &rmixl_configuration;
+ struct pci_attach_args * const pa = aux;
+ struct xlspi_softc * const sc = device_private(self);
+ // struct norbus_attach_args iba;
+
+ sc->sc_dev = self;
+ sc->sc_bst = &rcp->rc_pci_ecfg_eb_memt;
+
+ /*
+ * Why isn't this accessible via a BAR?
+ */
+ if (bus_space_subregion(sc->sc_bst, rcp->rc_pci_ecfg_eb_memh,
+ pa->pa_tag | 0x100, 0, &sc->sc_bsh)) {
+ aprint_error(": can't map registers\n");
+ return;
+ }
+
+ aprint_normal(": XLP SPI Controller\n");
+}
Index: src/sys/arch/mips/rmi/rmixl_iobus.c
diff -u /dev/null src/sys/arch/mips/rmi/rmixl_iobus.c:1.3.8.2
--- /dev/null Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixl_iobus.c Tue Dec 27 19:58:19 2011
@@ -0,0 +1,385 @@
+/* $NetBSD: rmixl_iobus.c,v 1.3.8.2 2011/12/27 19:58:19 matt Exp $ */
+
+/*-
+ * Copyright (c) 2011 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Cliff Neighbors
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * RMI Peripherals IO Bus support
+ * - interface to NOR, NAND, PCMCIA Memory controlers, &etc.
+ * - manages the 10 Chip Selects
+ * - manages the "Flash" interrupts
+ * - manages the "Flash" errors
+ */
+
+/*
+ * iobus control registers are accessed as 32 bits.
+ * ALEn and CLEn NAND control registers are defined as 8 bits wide
+ * but that seems to be a documentation error.
+ *
+ * iobus data access may be as 1 or 2 or 4 bytes, even if device is 1 byte wide;
+ * the controller will sequence the bytes, in big-endian order.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rmixl_iobus.c,v 1.3.8.2 2011/12/27 19:58:19 matt Exp $");
+
+#include "locators.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <sys/bus.h>
+
+#include <mips/rmi/rmixlreg.h>
+#include <mips/rmi/rmixlvar.h>
+#include <mips/rmi/rmixl_intr.h>
+#include <mips/rmi/rmixl_obiovar.h>
+#include <mips/rmi/rmixl_iobusvar.h>
+// #include <mips/rmi/rmixl_gpiovar.h>
+
+typedef struct {
+ bool cs_allocated;
+ uint32_t cs_addr; /* base address on the Peripherals I/O Bus */
+ uint32_t cs_mask; /* address mask on the Peripherals I/O Bus */
+ uint32_t cs_dev_parm;
+} rmixl_iobus_csconfig_t;
+
+typedef struct rmixl_iobus_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_obio_bst; /* for iobus device controler access */
+ bus_space_handle_t sc_obio_bsh; /* " " " " " */
+ bus_addr_t sc_obio_addr;
+ bus_size_t sc_obio_size;
+ bus_space_tag_t sc_iobus_bst; /* for iobus access */
+ rmixl_iobus_csconfig_t sc_csconfig[RMIXL_FLASH_NCS];
+} rmixl_iobus_softc_t;
+
+
+static int rmixl_iobus_obio_match(device_t, cfdata_t, void *);
+static void rmixl_iobus_obio_attach(device_t, device_t, void *);
+static void rmixl_iobus_csconfig_init(struct rmixl_iobus_softc *);
+static int rmixl_iobus_print(void *, const char *);
+static int rmixl_iobus_search(device_t, cfdata_t, const int *, void *);
+#ifdef NOTYET
+static int rmixl_iobus_intr(void *);
+#endif
+
+#ifdef RMIXL_IOBUS_DEBUG
+rmixl_iobus_softc_t *rmixl_iobus_sc;
+#endif
+
+
+CFATTACH_DECL_NEW(xliobus_obio, sizeof (rmixl_iobus_softc_t),
+ rmixl_iobus_obio_match, rmixl_iobus_obio_attach, NULL, NULL);
+
+int
+rmixl_iobus_obio_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct obio_attach_args *obio = aux;
+
+ if (obio->obio_addr == RMIXL_IO_DEV_FLASH)
+ return rmixl_probe_4((volatile uint32_t *)
+ RMIXL_IOREG_VADDR(obio->obio_addr));
+
+ return 0;
+}
+
+void
+rmixl_iobus_obio_attach(device_t parent, device_t self, void *aux)
+{
+ rmixl_iobus_softc_t *sc = device_private(self);
+ struct obio_attach_args *obio = aux;
+ struct rmixl_config *rcp = &rmixl_configuration;
+ uint64_t r;
+ int err;
+
+#ifdef RMIXL_IOBUS_DEBUG
+ rmixl_iobus_sc = sc;
+#endif
+ sc->sc_dev = self;
+ sc->sc_obio_bst = obio->obio_eb_bst;
+ sc->sc_obio_addr = obio->obio_addr;
+ sc->sc_obio_size = 0x1000;
+
+ err = bus_space_map(sc->sc_obio_bst, sc->sc_obio_addr,
+ sc->sc_obio_size, 0, &sc->sc_obio_bsh);
+ if (err != 0) {
+ aprint_error_dev(self,
+ "bus space map err %d, iobus space\n", err);
+ return;
+ }
+
+ r = RMIXL_IOREG_READ(RMIXL_SBC_FLASH_BAR);
+ KASSERT((r & 1) != 0); /* BAR is enabled */
+ rcp->rc_flash[0].r_pbase = RMIXL_FLASH_BAR_TO_BA(r);
+ rcp->rc_flash[0].r_size = RMIXL_FLASH_BAR_TO_MASK(r) + 1;
+
+ aprint_normal("\n");
+ aprint_debug_dev(self,
+ "Flash BAR pbase %#" PRIx64 " size %#" PRIx64 "\n",
+ rcp->rc_flash[0].r_pbase, rcp->rc_flash[0].r_size);
+
+ /* initialize iobus bus space */
+ rmixl_iobus_bus_mem_init(&rcp->rc_iobus_memt, rcp);
+ sc->sc_iobus_bst = (bus_space_tag_t)&rcp->rc_iobus_memt;
+
+ /* disable all Flsah interupts */
+ bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_FLASH_INT_MASK, 0);
+
+ /* write-1-to-clear Flash interrupt status */
+ bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_FLASH_INT_STATUS, ~0);
+
+ rmixl_iobus_csconfig_init(sc);
+
+ /* attach any children */
+ config_search_ia(rmixl_iobus_search, self, "rmixl_iobus", NULL);
+}
+
+static void
+rmixl_iobus_csconfig_init(struct rmixl_iobus_softc *sc)
+{
+ rmixl_iobus_csconfig_t *cs = &sc->sc_csconfig[0];
+
+ for (int i=0; i < RMIXL_FLASH_NCS; i++) {
+ memset(cs, 0, sizeof(rmixl_iobus_csconfig_t));
+ cs->cs_addr = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_FLASH_CSBASE_ADDRn(i)) << 16;
+ cs->cs_mask = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_FLASH_CSADDR_MASKn(i)) << 16;
+ cs->cs_mask |= __BITS(15,0);
+ cs->cs_dev_parm = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_FLASH_CSDEV_PARMn(i));
+ aprint_debug_dev(sc->sc_dev,
+ "CS#%d: addr 0x%08x mask 0x%08x parm 0x%08x\n",
+ i, cs->cs_addr, cs->cs_mask, cs->cs_dev_parm);
+ cs++;
+ }
+}
+
+
+static int
+rmixl_iobus_print(void *aux, const char *pnp)
+{
+ struct rmixl_iobus_attach_args *ia = aux;
+
+ if (ia->ia_cs != XLIOBUSCF_CS_DEFAULT)
+ aprint_normal(" CS#%d", ia->ia_cs);
+ if (ia->ia_iobus_addr != XLIOBUSCF_ADDR_DEFAULT) {
+ aprint_normal(" addr %#" PRIxBUSADDR, ia->ia_iobus_addr);
+ if (ia->ia_iobus_size != XLIOBUSCF_SIZE_DEFAULT)
+ aprint_normal("-%#" PRIxBUSSIZE,
+ ia->ia_iobus_addr + (ia->ia_iobus_size - 1));
+ }
+ if (ia->ia_iobus_intr != XLIOBUSCF_INTR_DEFAULT)
+ aprint_normal(" intr %d", ia->ia_iobus_intr);
+
+ return UNCONF;
+}
+
+static int
+rmixl_iobus_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
+{
+ struct rmixl_iobus_softc *sc = device_private(parent);
+ struct rmixl_iobus_attach_args ia;
+ rmixl_iobus_csconfig_t *cs;
+
+ ia.ia_obio_bst = sc->sc_obio_bst;
+ ia.ia_obio_bsh = sc->sc_obio_bsh;
+ ia.ia_iobus_bst = sc->sc_iobus_bst;
+ ia.ia_iobus_addr = (bus_addr_t)cf->cf_loc[XLIOBUSCF_ADDR];
+ ia.ia_iobus_size = (bus_size_t)cf->cf_loc[XLIOBUSCF_SIZE];
+ ia.ia_iobus_intr = cf->cf_loc[XLIOBUSCF_INTR];
+ ia.ia_cs = cf->cf_loc[XLIOBUSCF_CS];
+
+ if (ia.ia_cs != XLIOBUSCF_CS_DEFAULT) {
+ /* CS is configured */
+ cs = &sc->sc_csconfig[ia.ia_cs];
+
+ /* ensure exclusive use of chip select */
+ if (cs->cs_allocated) {
+ aprint_error_dev(parent, "CS#%d already allocated\n",
+ ia.ia_cs);
+ return 0;
+ }
+ if (ia.ia_iobus_addr != XLIOBUSCF_ADDR_DEFAULT) {
+ if (ia.ia_iobus_addr != cs->cs_addr) {
+ /*
+ * both CS and addr are configured,
+ * ensure they match
+ */
+ aprint_error_dev(parent,
+ "CS#%d addr 0x%08x mismatch cf_loc "
+ "addr 0x%08" PRIxBUSADDR "\n",
+ ia.ia_cs, cs->cs_addr, ia.ia_iobus_addr);
+ return 0;
+ }
+ } else {
+ /* no addr configured, pull from CS */
+ ia.ia_iobus_addr = cs->cs_addr;
+ }
+ } else {
+ /* addr is configured, CS is not; search for matching CS */
+ bool found = false;
+ cs = &sc->sc_csconfig[0];
+ for (int i=0; i < RMIXL_FLASH_NCS; i++) {
+ if (cs->cs_allocated)
+ continue;
+ if (cs->cs_addr == ia.ia_iobus_addr) {
+ ia.ia_cs = i;
+ found = true;
+ break;
+ }
+ cs++;
+ }
+ if (! found) {
+ aprint_error_dev(parent, "no CS for addr 0x%08"
+ PRIxBUSADDR "\n", ia.ia_iobus_addr);
+ return 0;
+ }
+ }
+
+ if (ia.ia_iobus_size != XLIOBUSCF_SIZE_DEFAULT) {
+ /* ensure size fits w/ CS mask */
+ if ((ia.ia_iobus_size - 1) > (bus_size_t)cs->cs_mask) {
+ aprint_error_dev(parent, "size %#" PRIxBUSSIZE
+ " exceeds CS#%d mask 0x%08x\n",
+ ia.ia_iobus_size, ia.ia_cs, cs->cs_mask);
+ }
+ } else {
+ /* size not configured, pull from CS */
+ ia.ia_iobus_size = (bus_size_t)cs->cs_mask + 1;
+ }
+
+ ia.ia_dev_parm = cs->cs_dev_parm;
+
+ if (config_match(parent, cf, &ia) > 0) {
+ cs->cs_allocated = true;
+ config_attach(parent, cf, &ia, rmixl_iobus_print);
+ }
+
+ return 0;
+}
+
+
+#ifdef NOTYET
+
+void
+rmixl_iobus_intr_disestablish(void *uh, void *ih)
+{
+ rmixl_iobus_softc_t *sc = uh;
+ u_int intr;
+
+ for (intr=0; intr <= RMIXL_UB_INTERRUPT_MAX; intr++) {
+ if (ih == &sc->sc_dispatch[intr]) {
+ uint32_t r;
+
+ /* disable this interrupt in the usb interface */
+ r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_USB_INTERRUPT_ENABLE);
+ r &= 1 << intr;
+ bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_USB_INTERRUPT_ENABLE, r);
+
+ /* free the dispatch slot */
+ sc->sc_dispatch[intr].func = NULL;
+ sc->sc_dispatch[intr].arg = NULL;
+
+ break;
+ }
+ }
+}
+
+void *
+rmixl_iobus_intr_establish(void *uh, u_int intr, int (func)(void *), void *arg)
+{
+ rmixl_iobus_softc_t *sc = uh;
+ uint32_t r;
+ void *ih = NULL;
+ int s;
+
+ s = splusb();
+
+ if (intr > RMIXL_UB_INTERRUPT_MAX) {
+ aprint_error_dev(sc->sc_dev, "invalid intr %d\n", intr);
+ goto out;
+ }
+
+ if (sc->sc_dispatch[intr].func != NULL) {
+ aprint_error_dev(sc->sc_dev, "intr %dq busy\n", intr);
+ goto out;
+ }
+
+ sc->sc_dispatch[intr].func = func;
+ sc->sc_dispatch[intr].arg = arg;
+ ih = &sc->sc_dispatch[intr];
+
+ /* enable this interrupt in the usb interface */
+ r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_USB_INTERRUPT_ENABLE);
+ r |= 1 << intr;
+ bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_USB_INTERRUPT_ENABLE, r);
+
+ out:
+ splx(s);
+ return ih;
+}
+
+static int
+rmixl_iobus_intr(void *arg)
+{
+ rmixl_iobus_softc_t *sc = arg;
+ uint32_t r;
+ int intr;
+ int rv = 0;
+
+ r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
+ RMIXL_USB_INTERRUPT_STATUS);
+ if (r != 0) {
+ for (intr=0; intr <= RMIXL_UB_INTERRUPT_MAX; intr++) {
+ uint32_t bit = 1 << intr;
+ if ((r & bit) != 0) {
+ int (*f)(void *) = sc->sc_dispatch[intr].func;
+ void *a = sc->sc_dispatch[intr].arg;
+ if (f != NULL) {
+ (void)(*f)(a);
+ sc->sc_dispatch[intr].count.ev_count++;
+ rv = 1;
+ }
+ }
+ }
+ }
+
+ return rv;
+}
+
+#endif /* NOTYET */
Index: src/sys/arch/mips/rmi/rmixl_iobus_space.c
diff -u /dev/null src/sys/arch/mips/rmi/rmixl_iobus_space.c:1.3.8.2
--- /dev/null Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixl_iobus_space.c Tue Dec 27 19:58:19 2011
@@ -0,0 +1,70 @@
+/* $NetBSD: rmixl_iobus_space.c,v 1.3.8.2 2011/12/27 19:58:19 matt Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * bus_space(9) support for Peripherals IO Bus on RMI {XLP,XLR,XLS} chips
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rmixl_iobus_space.c,v 1.3.8.2 2011/12/27 19:58:19 matt Exp $");
+
+#include <sys/types.h>
+#include <sys/param.h>
+
+#include <sys/bus.h>
+#include <mips/rmi/rmixl_iobusvar.h>
+#include <mips/rmi/rmixlreg.h>
+#include <mips/rmi/rmixlvar.h>
+
+#define CHIP rmixl_iobus
+#define CHIP_MEM /* defined */
+#define CHIP_ACCESS_SIZE 1
+#define CHIP_BIG_ENDIAN
+
+#define CHIP_V(v) ((struct rmixl_config *)(v))
+#define CHIP_EX_MALLOC_SAFE(v) (CHIP_V(v)->rc_mallocsafe)
+
+/*
+ * RMIXL_FLASH_BAR_MASK_MAX is __BITS(34,0)
+ * so avoid extent if that value overflows 'long'
+ */
+#ifdef _LP64
+#define CHIP_EXTENT(v) (CHIP_V(v)->rc_iobus_ex)
+#endif
+
+
+/* MEM region 1 */
+#define CHIP_W1_BUS_START(v) 0
+#define CHIP_W1_BUS_END(v) RMIXL_FLASH_BAR_MASK_MAX
+#define CHIP_W1_SYS_START(v) (CHIP_V(v)->rc_flash[0].r_pbase)
+#define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + CHIP_W1_BUS_END(v))
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
Index: src/sys/arch/mips/rmi/rmixl_iobusvar.h
diff -u /dev/null src/sys/arch/mips/rmi/rmixl_iobusvar.h:1.1.14.2
--- /dev/null Tue Dec 27 19:58:19 2011
+++ src/sys/arch/mips/rmi/rmixl_iobusvar.h Tue Dec 27 19:58:19 2011
@@ -0,0 +1,45 @@
+/* $NetBSD: rmixl_iobusvar.h,v 1.1.14.2 2011/12/27 19:58:19 matt Exp $ */
+/*-
+ * Copyright (c) 2011 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Cliff Neighbors
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RMIXL_IOBUSVAR_H_
+#define _RMIXL_IOBUSVAR_H_
+
+struct rmixl_iobus_attach_args {
+ bus_space_tag_t ia_obio_bst; /* for iobus controler access */
+ bus_space_handle_t ia_obio_bsh; /* " " " " */
+ bus_space_tag_t ia_iobus_bst; /* for iobus access */
+ bus_addr_t ia_iobus_addr; /* device iobus address */
+ bus_size_t ia_iobus_size; /* device iobus size */
+ uint32_t ia_iobus_intr; /* TBD */
+ uint32_t ia_dev_parm; /* copy of chip select device parameters */
+ int ia_cs; /* chip select index */
+};
+
+#endif /* _RMIXL_IOBUSVAR_H_ */
