Module Name: src
Committed By: macallan
Date: Sat Nov 22 15:17:02 UTC 2014
Modified Files:
src/sys/arch/evbmips/evbmips: interrupt.c
Added Files:
src/sys/arch/evbmips/conf: CI20 files.ingenic std.ingenic
src/sys/arch/evbmips/ingenic: autoconf.c clock.c machdep.c mainbus.c
src/sys/arch/mips/conf: files.ingenic
src/sys/arch/mips/ingenic: ingenic_com.c ingenic_regs.h
Log Message:
initial support for CI20 / Ingenic JZ4780
not much there yet, it loads, attaches a serial port and you can drop into
ddb
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbmips/conf/CI20 \
src/sys/arch/evbmips/conf/files.ingenic \
src/sys/arch/evbmips/conf/std.ingenic
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/evbmips/evbmips/interrupt.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbmips/ingenic/autoconf.c \
src/sys/arch/evbmips/ingenic/clock.c \
src/sys/arch/evbmips/ingenic/machdep.c \
src/sys/arch/evbmips/ingenic/mainbus.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/mips/conf/files.ingenic
cvs rdiff -u -r0 -r1.1 src/sys/arch/mips/ingenic/ingenic_com.c \
src/sys/arch/mips/ingenic/ingenic_regs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/evbmips/interrupt.c
diff -u src/sys/arch/evbmips/evbmips/interrupt.c:1.19 src/sys/arch/evbmips/evbmips/interrupt.c:1.20
--- src/sys/arch/evbmips/evbmips/interrupt.c:1.19 Tue May 14 09:16:59 2013
+++ src/sys/arch/evbmips/evbmips/interrupt.c Sat Nov 22 15:17:02 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.19 2013/05/14 09:16:59 macallan Exp $ */
+/* $NetBSD: interrupt.c,v 1.20 2014/11/22 15:17:02 macallan Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.19 2013/05/14 09:16:59 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.20 2014/11/22 15:17:02 macallan Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -79,8 +79,10 @@ cpu_intr(int ppl, vaddr_t pc, uint32_t s
KASSERTMSG(ipl == IPL_SCHED,
"%s: ipl (%d) != IPL_SCHED (%d)",
__func__, ipl, IPL_SCHED);
+#ifdef MIPS3_ENABLE_CLOCK_INTR
/* call the common MIPS3 clock interrupt handler */
mips3_clockintr(&cf);
+#endif
pending ^= MIPS_INT_MASK_5;
}
Added files:
Index: src/sys/arch/evbmips/conf/CI20
diff -u /dev/null src/sys/arch/evbmips/conf/CI20:1.1
--- /dev/null Sat Nov 22 15:17:02 2014
+++ src/sys/arch/evbmips/conf/CI20 Sat Nov 22 15:17:02 2014
@@ -0,0 +1,215 @@
+# $NetBSD: CI20,v 1.1 2014/11/22 15:17:02 macallan Exp $
+#
+# MIPS Creator CI20
+#
+
+# for now
+include "arch/evbmips/conf/std.ingenic"
+
+#options INCLUDE_CONFIG_FILE # embed config file in kernel binary
+
+#ident "DB120-$Revision: 1.1 $"
+
+maxusers 32
+
+#makeoptions COPTS="-Os" # Optimise for space. Implies -O2
+
+options MIPS32R2
+makeoptions CPUFLAGS+="-mips32r2"
+makeoptions NEED_MDSETIMAGE="yes"
+makeoptions NEED_BINARY="yes"
+makeoptions NEED_UBOOTIMAGE="gz"
+options COM_16650,COM_TOLERANCE=50 # +/- 5%
+options CONSPEED=115200 # u-boot default
+options CONSADDR=0x10030000
+options MEMSIZE="(256*1024*1024)"
+
+# Options for necessary to use MD
+#options MEMORY_DISK_HOOKS
+#options MEMORY_DISK_IS_ROOT # force root on memory disk
+#options MEMORY_DISK_SERVER=0 # no userspace memory disk support
+#options MEMORY_DISK_ROOT_SIZE=6144 # size of memory disk, in blocks
+#options MEMORY_DISK_ROOT_SIZE=16384 # size of memory disk, in blocks
+#options MEMORY_DISK_ROOT_SIZE=7300
+
+# Size reduction options
+#options VNODE_OP_NOINLINE
+#options PIPE_SOCKETPAIR
+options SOSEND_NO_LOAN
+
+# Standard system options
+options KTRACE # system call tracing support
+#options SYSVMSG # System V message queues
+#options SYSVSEM # System V semaphores
+#options SYSVSHM # System V shared memory
+options NTP # network time protocol
+
+# Debugging options
+options DIAGNOSTIC # extra kernel sanity checking
+options DEBUG # extra kernel debugging support
+#options KMEMSTATS # kernel memory statistics (vmstat -m)
+#options USERCONF # userconf(4) support
+#options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel
+options DDB # kernel dynamic debugger
+options DDB_HISTORY_SIZE=100 # enable history editing in DDB
+makeoptions DEBUG="-g" # compile full symbol table
+makeoptions COPY_SYMTAB=1 # size for embedded symbol table
+
+# Compatibility options
+#options COMPAT_43 # compatibility with 4.3BSD binaries
+#options COMPAT_09 # NetBSD 0.9,
+#options COMPAT_10 # NetBSD 1.0,
+#options COMPAT_11 # NetBSD 1.1,
+#options COMPAT_12 # NetBSD 1.2,
+#options COMPAT_13 # NetBSD 1.3,
+#options COMPAT_14 # NetBSD 1.4,
+#options COMPAT_15 # NetBSD 1.5,
+#options COMPAT_16 # NetBSD 1.6,
+#options COMPAT_20 # NetBSD 2.0,
+#options COMPAT_30 # NetBSD 3.0, and
+#options COMPAT_40 # NetBSD 4.0 binary compatibility.
+#options EXEC_ECOFF # exec ECOFF binaries
+#options COMPAT_ULTRIX # binary compatibility with Ultrix
+#options COMPAT_BSDPTY # /dev/[pt]ty?? ptys.
+
+# File systems
+file-system FFS # Berkeley Fast Filesystem
+file-system MFS # memory-based filesystem
+#file-system EXT2FS # second extended file system (linux)
+file-system NFS # Sun NFS-compatible filesystem client
+#file-system KERNFS # kernel data-structure filesystem
+#file-system NULLFS # NULL layered filesystem
+#file-system OVERLAY # overlay file system
+#file-system FDESC # user file descriptor filesystem
+#file-system UMAPFS # uid/gid remapping filesystem
+#file-system LFS # Log-based filesystem (still experimental)
+#file-system PROCFS # /proc
+#file-system CD9660 # ISO 9660 + Rock Ridge file system
+#file-system UNION # union file system
+#file-system MSDOSFS # MS-DOS FAT filesystem(s).
+#file-system CODA # Coda File System; also needs vcoda (below)
+#file-system PTYFS # /dev/pts/N support
+
+# File system options
+#options NFSSERVER # Sun NFS-compatible filesystem server
+#options QUOTA # legacy UFS quotas
+#options QUOTA2 # new, in-filesystem UFS quotas
+#options FFS_EI # FFS Endian Independent support
+options WAPBL # File system journaling support
+options FFS_NO_SNAPSHOT # No FFS snapshot support
+#options EXT2FS_SYSTEM_FLAGS # makes ext2fs file flags (append and
+ # immutable) behave as system flags.
+
+# Networking options
+#options GATEWAY # IP packet forwarding
+options INET # Internet protocols
+#options INET6 # IPV6
+#options IPSEC # IP security
+#options IPSEC_DEBUG # debug for IP security
+#options MROUTING # packet forwarding of multicast packets
+#options PIM # Protocol Independent Multicast
+#options NETATALK # AppleTalk (over Ethernet) protocol
+#options PPP_BSDCOMP # BSD-Compress compression support for PPP
+#options PPP_DEFLATE # Deflate compression support for PPP
+#options PPP_FILTER # Active filter support for PPP (requires bpf)
+#options IPFILTER_LOG # ipmon(8) log support
+#options IPFILTER_LOOKUP # ippool(8) support
+
+# Compatibility with 4.2BSD implementation of TCP/IP. Not recommended.
+#options TCP_COMPAT_42
+
+# JIT compiler for bpfilter
+#options SLJIT
+#options BPFJIT
+
+# These options enable verbose messages for several subsystems.
+# Warning, these may compile large string tables into the kernel!
+options MIIVERBOSE # verbose PHY autoconfig messages
+
+# Bitmask for enabling the PCI IDE channels in the southbridge.
+# Set bit 0 (0x01) for channel 0, bit 1 (0x02) for channel 1.
+#
+# Do this if your firmware (usually PMON and YAMON) doens't enable the IDE
+# channels for you (thus causing the NetBSD `pciide' driver to ignore them).
+#options PCI_NETBSD_ENABLE_IDE=0x1
+
+options NFS_BOOT_BOOTP
+#options NFS_BOOT_DHCP
+#options NFS_V2_ONLY
+
+config netbsd root on ? type ?
+
+mainbus0 at root
+cpu0 at mainbus?
+#wdog0 at mainbus?
+#options COM_REGMAP
+com* at mainbus?
+#ehci* at arbus? addr ?
+#usb* at ehci?
+#uhub* at usb?
+#uhub* at uhub? port ?
+#umass* at uhub? port ? configuration ? interface ?
+#scsibus* at umass? channel ?
+#sd* at scsibus? target ? lun ?
+#ae* at arbus? addr ?
+#ath* at arbus? addr ?
+#athflash* at arbus? addr ?
+#argpio* at arbus? addr ?
+#gpio* at argpio?
+
+# no RTC! so fake with a stub (required to prevent evbmips panic)
+
+
+# MII/PHY support
+#acphy* at mii? phy ? # DAltima AC101 and AMD Am79c874 PHYs
+#amhphy* at mii? phy ? # AMD 79c901 Ethernet PHYs
+#dmphy* at mii? phy ? # Davicom DM9101 PHYs
+#glxtphy* at mii? phy ? # Level One LXT-1000 PHYs
+#gphyter* at mii? phy ? # NS83861 Gig-E PHY
+#icsphy* at mii? phy ? # Integrated Circuit Systems ICS1890
+#lxtphy* at mii? phy ? # Level One LXT-970 PHYs
+#makphy* at mii? phy ? # Marvell Semiconductor 88E1000 PHYs
+#nsphy* at mii? phy ? # NS83840 PHYs
+#nsphyter* at mii? phy ? # NS83843 PHYs
+#pnaphy* at mii? phy ? # generic HomePNA PHYs
+#qsphy* at mii? phy ? # Quality Semiconductor QS6612 PHYs
+#sqphy* at mii? phy ? # Seeq 80220/80221/80223 PHYs
+#tlphy* at mii? phy ? # ThunderLAN PHYs
+#tqphy* at mii? phy ? # TDK Semiconductor PHYs
+#rlphy* at mii? phy ? # RealTek PHYs
+#ukphy* at mii? phy ? # generic unknown PHYs
+
+
+# Pseudo-devices
+
+# Disk/mass storage pseudo-devices
+#pseudo-device ccd # concatenated disk devices
+#pseudo-device raid # RAIDframe disk driver
+#pseudo-device fss # file system snapshot device
+#pseudo-device md # memory disk device (ramdisk)
+#pseudo-device vnd # disk-like interface to files
+
+# Network pseudo-devices
+pseudo-device bpfilter # Berkeley packet filter
+#pseudo-device ipfilter # IP filter (firewall) and NAT
+pseudo-device loop # network loopback
+#pseudo-device ppp # Point-to-Point Protocol
+#pseudo-device sl # Serial Line IP
+#pseudo-device strip # Starmode Radio IP (Metricom)
+#pseudo-device tun # network tunneling over tty
+#pseudo-device tap # virtual Ethernet
+#pseudo-device gre # generic L3 over IP tunnel
+#pseudo-device ipip # RFC 2003 IP Encapsulation
+#pseudo-device gif # RFC1933 tunnel
+#pseudo-device faith # IPv[46] tcp relay translation
+#pseudo-device stf # 6to4 IPv6 over IPv4 encapsulation
+#pseudo-device vlan # IEEE 802.1q encapsulation
+#pseudo-device bridge # simple inter-network bridging
+
+# Miscellaneous pseudo-devices
+pseudo-device pty # pseudo-terminals
+pseudo-device clockctl # user control of clock subsystem
+pseudo-device ksyms # /dev/ksyms
+
+# A pseudo device needed for Coda # also needs CODA (above)
+#pseudo-device vcoda # coda minicache <-> venus comm.
Index: src/sys/arch/evbmips/conf/files.ingenic
diff -u /dev/null src/sys/arch/evbmips/conf/files.ingenic:1.1
--- /dev/null Sat Nov 22 15:17:02 2014
+++ src/sys/arch/evbmips/conf/files.ingenic Sat Nov 22 15:17:02 2014
@@ -0,0 +1,23 @@
+# $NetBSD: files.ingenic,v 1.1 2014/11/22 15:17:02 macallan Exp $
+
+#file arch/evbmips/ingenic/intr.c
+
+file arch/evbmips/ingenic/autoconf.c
+file arch/evbmips/ingenic/machdep.c
+
+file arch/mips/mips/bus_dma.c
+file arch/evbmips/evbmips/disksubr.c
+file arch/evbmips/evbmips/interrupt.c
+file arch/evbmips/ingenic/clock.c
+
+# System bus
+device mainbus { }
+attach mainbus at root
+file arch/evbmips/ingenic/mainbus.c mainbus
+
+device cpu
+attach cpu at mainbus
+file arch/evbmips/evbmips/cpu.c cpu
+
+# Memory Disk
+file dev/md_root.c memory_disk_hooks
Index: src/sys/arch/evbmips/conf/std.ingenic
diff -u /dev/null src/sys/arch/evbmips/conf/std.ingenic:1.1
--- /dev/null Sat Nov 22 15:17:02 2014
+++ src/sys/arch/evbmips/conf/std.ingenic Sat Nov 22 15:17:02 2014
@@ -0,0 +1,15 @@
+# $NetBSD: std.ingenic,v 1.1 2014/11/22 15:17:02 macallan Exp $
+
+machine evbmips mips
+include "conf/std" # MI standard options
+
+options EXEC_ELF32 # exec ELF32 binaries
+options EXEC_SCRIPT # exec #! scripts
+
+makeoptions CPUFLAGS+="-mips32r2"
+makeoptions DEFTEXTADDR="0x80020000"
+makeoptions BOARDTYPE="ingenic"
+
+include "arch/evbmips/conf/files.ingenic"
+include "arch/mips/conf/files.ingenic"
+
Index: src/sys/arch/evbmips/ingenic/autoconf.c
diff -u /dev/null src/sys/arch/evbmips/ingenic/autoconf.c:1.1
--- /dev/null Sat Nov 22 15:17:02 2014
+++ src/sys/arch/evbmips/ingenic/autoconf.c Sat Nov 22 15:17:02 2014
@@ -0,0 +1,69 @@
+/* $NetBSD: autoconf.c,v 1.1 2014/11/22 15:17:02 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.1 2014/11/22 15:17:02 macallan Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+/*
+ * Configure all devices on system
+ */
+void
+cpu_configure(void)
+{
+
+ intr_init();
+
+ /* Kick off autoconfiguration. */
+ (void)splhigh();
+ if (config_rootfound("mainbus", NULL) == NULL)
+ panic("no mainbus found");
+}
+
+void
+cpu_rootconf(void)
+{
+
+ rootconf();
+}
+
+void
+device_register(device_t dev, void *aux)
+{
+#ifdef notyet
+ (*platformsw->apsw_device_register)(dev, aux);
+#endif
+}
Index: src/sys/arch/evbmips/ingenic/clock.c
diff -u /dev/null src/sys/arch/evbmips/ingenic/clock.c:1.1
--- /dev/null Sat Nov 22 15:17:02 2014
+++ src/sys/arch/evbmips/ingenic/clock.c Sat Nov 22 15:17:02 2014
@@ -0,0 +1,93 @@
+/* $NetBSD: clock.c,v 1.1 2014/11/22 15:17:02 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.1 2014/11/22 15:17:02 macallan Exp $");
+
+#include <sys/param.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <mips/ingenic/ingenic_regs.h>
+
+void
+cpu_initclocks(void)
+{
+
+ /* timecounter setup and such */
+}
+
+/* shamelessly stolen from mips3_clock.c */
+void
+delay(int n)
+{
+ u_long divisor_delay;
+ uint32_t cur, last, delta, usecs;
+
+ last = readreg(JZ_OST_CNT_LO);
+ delta = usecs = 0;
+
+ divisor_delay = curcpu()->ci_divisor_delay;
+ if (divisor_delay == 0) {
+ /*
+ * Frequency values in curcpu() are not initialized.
+ * Assume faster frequency since longer delays are harmless.
+ * Note CPU_MIPS_DOUBLE_COUNT is ignored here.
+ */
+#define FAST_FREQ (300 * 1000 * 1000) /* fast enough? */
+ divisor_delay = FAST_FREQ / (1000 * 1000);
+ }
+ while (n > usecs) {
+ cur = readreg(JZ_OST_CNT_LO);
+
+ /*
+ * We setup the OS timer to always counts upto UINT32_MAX,
+ * so no need to check wrapped around case.
+ */
+ delta += (cur - last);
+
+ last = cur;
+
+ while (delta >= divisor_delay) {
+ /*
+ * delta is not so larger than divisor_delay here,
+ * and using DIV/DIVU ops could be much slower.
+ * (though longer delay may be harmless)
+ */
+ usecs++;
+ delta -= divisor_delay;
+ }
+ }
+}
+
+void
+setstatclockrate(int r)
+{
+ /* nothing to see here */
+}
Index: src/sys/arch/evbmips/ingenic/machdep.c
diff -u /dev/null src/sys/arch/evbmips/ingenic/machdep.c:1.1
--- /dev/null Sat Nov 22 15:17:02 2014
+++ src/sys/arch/evbmips/ingenic/machdep.c Sat Nov 22 15:17:02 2014
@@ -0,0 +1,346 @@
+/* $NetBSD: machdep.c,v 1.1 2014/11/22 15:17:02 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.1 2014/11/22 15:17:02 macallan Exp $");
+
+#include "opt_ddb.h"
+#include "opt_kgdb.h"
+#include "opt_modular.h"
+
+#include <sys/param.h>
+#include <sys/boot_flag.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/kcore.h>
+#include <sys/ksyms.h>
+#include <sys/mount.h>
+#include <sys/reboot.h>
+#include <sys/cpu.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <dev/cons.h>
+
+#include <mips/ingenic/ingenic_regs.h>
+
+#include "ksyms.h"
+
+#if NKSYMS || defined(DDB) || defined(MODULAR)
+#include <mips/db_machdep.h>
+#include <ddb/db_extern.h>
+#endif
+
+#include <mips/cache.h>
+#include <mips/locore.h>
+#include <mips/cpuregs.h>
+
+/* Maps for VM objects. */
+struct vm_map *phys_map = NULL;
+
+int maxmem; /* max memory per process */
+
+int mem_cluster_cnt;
+phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
+
+void mach_init(void); /* XXX */
+void ingenic_reset(void);
+
+void ingenic_putchar_init(void);
+void ingenic_puts(const char *);
+void ingenic_com_cnattach(void);
+
+static void
+cal_timer(void)
+{
+ uint32_t cntfreq;
+ volatile uint32_t junk;
+
+ /*
+ * The manual seems to imply that EXCCLK is 12MHz, although in real
+ * life it appears to be 48MHz. Either way, we want a 12MHz counter.
+ */
+ curcpu()->ci_cpu_freq = 1200000000; /* for now */
+ cntfreq = 12000000; /* EXTCLK / 4 */
+
+ curcpu()->ci_cctr_freq = cntfreq;
+ curcpu()->ci_cycles_per_hz = (cntfreq + hz / 2) / hz;
+
+ /* Compute number of cycles per 1us (1/MHz). 0.5MHz is for roundup. */
+ curcpu()->ci_divisor_delay = ((cntfreq + 500000) / 1000000);
+
+ /* actually start the counter now */
+ /* stop OS timer */
+ writereg(JZ_TC_TECR, TESR_OST);
+ /* zero everything */
+ writereg(JZ_OST_CTRL, 0);
+ writereg(JZ_OST_CNT_LO, 0);
+ writereg(JZ_OST_CNT_HI, 0);
+ writereg(JZ_OST_DATA, 0xffffffff);
+ /* use EXTCLK, don't reset */
+ writereg(JZ_OST_CTRL, OSTC_EXT_EN | OSTC_MODE | OSTC_DIV_4);
+ /* start the timer */
+ writereg(JZ_TC_TESR, TESR_OST);
+ /* make sure the timer actually runs */
+ junk = readreg(JZ_OST_CNT_LO);
+ do {} while (junk == readreg(JZ_OST_CNT_LO));
+}
+
+void
+mach_init(void)
+{
+ void *kernend;
+ uint32_t memsize;
+ extern char edata[], end[]; /* XXX */
+
+ /* clear the BSS segment */
+ kernend = (void *)mips_round_page(end);
+
+ memset(edata, 0, (char *)kernend - edata);
+
+ /* setup early console */
+ ingenic_putchar_init();
+
+ /* set CPU model info for sysctl_hw */
+ cpu_setmodel("Ingenic XBurst");
+ mips_vector_init(NULL, false);
+ cal_timer();
+ uvm_setpagesize();
+ /*
+ * Look at arguments passed to us and compute boothowto.
+ */
+ boothowto = RB_AUTOBOOT;
+#ifdef KADB
+ boothowto |= RB_KDB;
+#endif
+
+ /*
+ * Determine the memory size.
+ *
+ * Note: Reserve the first page! That's where the trap
+ * vectors are located.
+ */
+ memsize = 0x40000000;
+
+ printf("Memory size: 0x%08x\n", memsize);
+ physmem = btoc(memsize);
+
+ /* XXX this is CI20 specific */
+ mem_clusters[0].start = PAGE_SIZE;
+ mem_clusters[0].size = 0x10000000 - PAGE_SIZE;
+ mem_clusters[1].start = 0x30000000;
+ mem_clusters[1].size = 0x30000000;
+ mem_cluster_cnt = 2;
+
+ /*
+ * Load the available pages into the VM system.
+ */
+ mips_page_physload(MIPS_KSEG0_START, (vaddr_t)kernend,
+ mem_clusters, mem_cluster_cnt, NULL, 0);
+
+ /*
+ * Initialize message buffer (at end of core).
+ */
+ mips_init_msgbuf();
+
+ /*
+ * Initialize the virtual memory system.
+ */
+ pmap_bootstrap();
+
+ /*
+ * Allocate uarea page for lwp0 and set it.
+ */
+ mips_init_lwp0_uarea();
+
+ /*
+ * Initialize debuggers, and break into them, if appropriate.
+ */
+#ifdef DDB
+ if (boothowto & RB_KDB)
+ Debugger();
+#endif
+}
+
+void
+consinit(void)
+{
+ /*
+ * Everything related to console initialization is done
+ * in mach_init().
+ */
+ ingenic_com_cnattach();
+}
+
+void
+cpu_startup(void)
+{
+ char pbuf[9];
+ vaddr_t minaddr, maxaddr;
+#ifdef DEBUG
+ extern int pmapdebug; /* XXX */
+ int opmapdebug = pmapdebug;
+
+ pmapdebug = 0; /* Shut up pmap debug during bootstrap */
+#endif
+
+ /*
+ * Good {morning,afternoon,evening,night}.
+ */
+ printf("%s%s", copyright, version);
+ printf("%s\n", cpu_getmodel());
+ format_bytes(pbuf, sizeof(pbuf), ctob(physmem));
+ printf("total memory = %s\n", pbuf);
+
+ minaddr = 0;
+ /*
+ * Allocate a submap for physio
+ */
+ phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
+ VM_PHYS_SIZE, 0, FALSE, NULL);
+
+ /*
+ * No need to allocate an mbuf cluster submap. Mbuf clusters
+ * are allocated via the pool allocator, and we use KSEG to
+ * map those pages.
+ */
+
+#ifdef DEBUG
+ pmapdebug = opmapdebug;
+#endif
+ format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free));
+ printf("avail memory = %s\n", pbuf);
+}
+
+void
+cpu_reboot(int howto, char *bootstr)
+{
+ static int waittime = -1;
+
+ /* Take a snapshot before clobbering any registers. */
+ savectx(curpcb);
+
+ /* If "always halt" was specified as a boot flag, obey. */
+ if (boothowto & RB_HALT)
+ howto |= RB_HALT;
+
+ boothowto = howto;
+
+ /* If system is cold, just halt. */
+ if (cold) {
+ boothowto |= RB_HALT;
+ goto haltsys;
+ }
+
+ if ((boothowto & RB_NOSYNC) == 0 && waittime < 0) {
+ waittime = 0;
+
+ /*
+ * Synchronize the disks....
+ */
+ vfs_shutdown();
+
+ /*
+ * If we've been adjusting the clock, the todr
+ * will be out of synch; adjust it now.
+ */
+ resettodr();
+ }
+
+ /* Disable interrupts. */
+ splhigh();
+
+ if (boothowto & RB_DUMP)
+ dumpsys();
+
+ haltsys:
+ /* Run any shutdown hooks. */
+ doshutdownhooks();
+
+ pmf_system_shutdown(boothowto);
+
+#if 0
+ if ((boothowto & RB_POWERDOWN) == RB_POWERDOWN)
+ if (board && board->ab_poweroff)
+ board->ab_poweroff();
+#endif
+
+ /*
+ * Firmware may autoboot (depending on settings), and we cannot pass
+ * flags to it (at least I haven't figured out how to yet), so
+ * we "pseudo-halt" now.
+ */
+ if (boothowto & RB_HALT) {
+ printf("\n");
+ printf("The operating system has halted.\n");
+ printf("Please press any key to reboot.\n\n");
+ cnpollc(1); /* For proper keyboard command handling */
+ cngetc();
+ cnpollc(0);
+ }
+
+ printf("reseting board...\n\n");
+ mips_icache_sync_all();
+ mips_dcache_wbinv_all();
+ ingenic_reset();
+ __asm volatile("jr %0" :: "r"(MIPS_RESET_EXC_VEC));
+ printf("Oops, back from reset\n\nSpinning...");
+ for (;;)
+ /* spin forever */ ; /* XXX */
+ /*NOTREACHED*/
+}
+
+void
+ingenic_reset(void)
+{
+ /*
+ * for now, provoke a watchdog reset in about a second, so UART buffers
+ * have a fighting chance to flush before we pull the plug
+ */
+ writereg(JZ_WDOG_TCER, 0); /* disable watchdog */
+ writereg(JZ_WDOG_TCNT, 0); /* reset counter */
+ writereg(JZ_WDOG_TDR, 128); /* wait for ~1s */
+ writereg(JZ_WDOG_TCSR, TCSR_RTC_EN | TCSR_DIV_256);
+ writereg(JZ_WDOG_TCER, TCER_ENABLE); /* fire! */
+}
+
+void
+evbmips_intr_init(void)
+{
+#if notyet
+ (*platformsw->apsw_intr_init)();
+#endif
+}
+
+void
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
+{
+#if notyet
+ (*platformsw->apsw_intrsw->aisw_iointr)(ipl, pc, ipending);
+#endif
+}
Index: src/sys/arch/evbmips/ingenic/mainbus.c
diff -u /dev/null src/sys/arch/evbmips/ingenic/mainbus.c:1.1
--- /dev/null Sat Nov 22 15:17:02 2014
+++ src/sys/arch/evbmips/ingenic/mainbus.c Sat Nov 22 15:17:02 2014
@@ -0,0 +1,90 @@
+/* $NetBSD: mainbus.c,v 1.1 2014/11/22 15:17:02 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.1 2014/11/22 15:17:02 macallan Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <mips/cache.h>
+#include <mips/cpuregs.h>
+
+#include "locators.h"
+
+static int mainbus_match(device_t, cfdata_t, void *);
+static void mainbus_attach(device_t, device_t, void *);
+static int mainbus_print(void *, const char *);
+
+CFATTACH_DECL_NEW(mainbus, 0,
+ mainbus_match, mainbus_attach, NULL, NULL);
+
+/* There can be only one. */
+int mainbus_found = 0;
+
+struct mainbusdev {
+ const char *md_name;
+};
+
+struct mainbusdev mainbusdevs[] = {
+ { "cpu", },
+ { "com", },
+ { NULL, }
+};
+
+static int
+mainbus_match(device_t parent, cfdata_t match, void *aux)
+{
+
+ if (mainbus_found)
+ return (0);
+
+ return (1);
+}
+
+static void
+mainbus_attach(device_t parent, device_t self, void *aux)
+{
+ const struct mainbusdev *md;
+
+ mainbus_found = 1;
+ printf("\n");
+
+ for (md = mainbusdevs; md->md_name != NULL; md++) {
+ struct mainbusdev ma = *md;
+ config_found_ia(self, "mainbus", &ma, mainbus_print);
+ }
+}
+
+static int
+mainbus_print(void *aux, const char *pnp)
+{
+
+ return (QUIET);
+}
Index: src/sys/arch/mips/conf/files.ingenic
diff -u /dev/null src/sys/arch/mips/conf/files.ingenic:1.1
--- /dev/null Sat Nov 22 15:17:02 2014
+++ src/sys/arch/mips/conf/files.ingenic Sat Nov 22 15:17:01 2014
@@ -0,0 +1,6 @@
+# $NetBSD: files.ingenic,v 1.1 2014/11/22 15:17:01 macallan Exp $
+
+# On-chip UART device
+attach com at mainbus with com_mainbus
+file arch/mips/ingenic/ingenic_com.c com_mainbus
+
Index: src/sys/arch/mips/ingenic/ingenic_com.c
diff -u /dev/null src/sys/arch/mips/ingenic/ingenic_com.c:1.1
--- /dev/null Sat Nov 22 15:17:02 2014
+++ src/sys/arch/mips/ingenic/ingenic_com.c Sat Nov 22 15:17:01 2014
@@ -0,0 +1,205 @@
+/* $NetBSD: ingenic_com.c,v 1.1 2014/11/22 15:17:01 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: ingenic_com.c,v 1.1 2014/11/22 15:17:01 macallan Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/termios.h>
+#include <sys/ttydefaults.h>
+#include <sys/types.h>
+
+#include <sys/bus.h>
+
+#include <dev/cons.h>
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+
+#include <mips/cpuregs.h>
+
+#include <mips/ingenic/ingenic_regs.h>
+
+#include "opt_com.h"
+
+volatile int32_t *com0addr = (int32_t *)MIPS_PHYS_TO_KSEG1(JZ_UART0);
+
+void ingenic_putchar_init(void);
+void ingenic_puts(const char *);
+void ingenic_putchar(char);
+
+#ifndef CONMODE
+# define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8)
+#endif
+
+
+struct mips_bus_space ingenic_com_mbst;
+int mbst_valid = 0;
+static void ingenic_com_bus_mem_init(bus_space_tag_t, void *);
+void ingenic_com_cnattach(void);
+
+static int ingenic_com_match(device_t, cfdata_t , void *);
+static void ingenic_com_attach(device_t, device_t, void *);
+
+struct ingenic_com_softc {
+ struct com_softc sc_com;
+};
+
+CFATTACH_DECL_NEW(com_mainbus, sizeof(struct ingenic_com_softc),
+ ingenic_com_match, ingenic_com_attach, NULL, NULL);
+
+bus_space_handle_t regh = 0;
+
+void
+ingenic_putchar_init(void)
+{
+ /*
+ * XXX don't screw with the UART's speed until we know what clock
+ * we're on
+ */
+#if 0
+ int rate;
+#endif
+ extern int comspeed(long, long, int);
+
+ com0addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(JZ_UART0);
+#if 0
+ if (comcnfreq != -1) {
+ rate = comspeed(comcnspeed, comcnfreq, COM_TYPE_INGENIC);
+ if (rate < 0)
+ return; /* XXX */
+#endif
+ com0addr[com_ier] = 0;
+ com0addr[com_lctl] = htole32(LCR_DLAB);
+#if 0
+ com0addr[com_dlbl] = htole32(rate & 0xff);
+ com0addr[com_dlbh] = htole32(rate >> 8);
+#endif
+ com0addr[com_lctl] = htole32(LCR_8BITS); /* XXX */
+ com0addr[com_mcr] = htole32(MCR_DTR|MCR_RTS);
+ com0addr[com_fifo] = htole32(
+ FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
+ FIFO_TRIGGER_1 | FIFO_UART_ON);
+#if 0
+ }
+#endif
+}
+
+
+void
+ingenic_putchar(char c)
+{
+ int timo = 150000;
+
+ while ((le32toh(com0addr[com_lsr]) & LSR_TXRDY) == 0)
+ if (--timo == 0)
+ break;
+
+ com0addr[com_data] = htole32((uint32_t)c);
+
+ while ((le32toh(com0addr[com_lsr]) & LSR_TSRE) == 0)
+ if (--timo == 0)
+ break;
+}
+
+void
+ingenic_puts(const char *restrict s)
+{
+ char c;
+
+ while ((c = *s++) != 0)
+ ingenic_putchar(c);
+}
+
+static void
+ingenic_com_bus_init(void)
+{
+ if (mbst_valid) return;
+ ingenic_com_bus_mem_init(&ingenic_com_mbst, NULL);
+ mbst_valid = 1;
+}
+
+void
+ingenic_com_cnattach(void)
+{
+ struct com_regs regs;
+
+ ingenic_com_bus_init();
+ bus_space_map(&ingenic_com_mbst, 0, 0x1000, 0, ®h);
+
+ memset(®s, 0, sizeof(regs));
+ COM_INIT_REGS(regs, &ingenic_com_mbst, regh, 0);
+
+ /*
+ * XXX
+ * UART clock is either 6MHz or 12MHz, the manual is rather unclear
+ * so we just leave alone whatever u-boot set up
+ * my uplcom is too tolerant to show any difference
+ */
+ comcnattach1(®s, -1, 6000000, COM_TYPE_INGENIC, CONMODE);
+}
+
+static int
+ingenic_com_match(device_t parent, cfdata_t cfdata, void *args)
+{
+ struct mainbusdev {
+ const char *md_name;
+ } *aa = args;
+ if (strcmp(aa->md_name, "com") == 0) return 1;
+ return 0;
+}
+
+
+static void
+ingenic_com_attach(device_t parent, device_t self, void *args)
+{
+ struct ingenic_com_softc *isc = device_private(self);
+ struct com_softc *sc = &isc->sc_com;
+
+ sc->sc_dev = self;
+ sc->sc_frequency = 12000000;
+ sc->sc_type = COM_TYPE_INGENIC;
+ memset(&sc->sc_regs, 0, sizeof(sc->sc_regs));
+ COM_INIT_REGS(sc->sc_regs, &ingenic_com_mbst, regh, 0);
+ com_attach_subr(sc);
+ printf("\n");
+ /* interrupt */
+}
+
+#define CHIP ingenic_com
+#define CHIP_MEM /* defined */
+#define CHIP_W1_BUS_START(v) 0x00000000UL
+#define CHIP_W1_BUS_END(v) 0x00010000UL
+#define CHIP_W1_SYS_START(v) 0x10030000UL
+#define CHIP_W1_SYS_END(v) 0x10035000UL
+#define CHIP_ACCESS_SIZE 1
+#define CHIP_ALIGN_STRIDE 2
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
Index: src/sys/arch/mips/ingenic/ingenic_regs.h
diff -u /dev/null src/sys/arch/mips/ingenic/ingenic_regs.h:1.1
--- /dev/null Sat Nov 22 15:17:02 2014
+++ src/sys/arch/mips/ingenic/ingenic_regs.h Sat Nov 22 15:17:01 2014
@@ -0,0 +1,105 @@
+/* $NetBSD: ingenic_regs.h,v 1.1 2014/11/22 15:17:01 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <mips/locore.h>
+
+#ifndef INGENIC_REGS_H
+#define INGENIC_REGS_H
+
+/* UARTs, mostly 16550 compatible with 32bit spaced registers */
+#define JZ_UART0 0x10030000
+#define JZ_UART1 0x10031000
+#define JZ_UART2 0x10032000
+#define JZ_UART3 0x10033000
+#define JZ_UART4 0x10034000
+
+/* watchdog */
+#define JZ_WDOG_TDR 0x10002000 /* compare */
+#define JZ_WDOG_TCER 0x10002004
+ #define TCER_ENABLE 0x01 /* enable counter */
+#define JZ_WDOG_TCNT 0x10002008 /* 16bit up count */
+#define JZ_WDOG_TCSR 0x1000200c
+ #define TCSR_PCK_EN 0x01 /* PCLK */
+ #define TCSR_RTC_EN 0x02 /* RTCCLK - 32.768kHz */
+ #define TCSR_EXT_EN 0x04 /* EXTCLK - 12MHz? */
+ #define TCSR_PRESCALE_M 0x38
+ #define TCSR_DIV_1 0x00
+ #define TCSR_DIV_4 0x08
+ #define TCSR_DIV_16 0x10
+ #define TCSR_DIV_64 0x18
+ #define TCSR_DIV_256 0x20
+ #define TCSR_DIV_1024 0x28
+
+/* timers and PWMs */
+#define JZ_TC_TER 0x10002010 /* TC enable reg, ro */
+#define JZ_TC_TESR 0x10002014 /* TC enable set reg. */
+ #define TESR_TCST0 0x0001 /* enable counter 0 */
+ #define TESR_TCST1 0x0002 /* enable counter 1 */
+ #define TESR_TCST2 0x0004 /* enable counter 2 */
+ #define TESR_TCST3 0x0008 /* enable counter 3 */
+ #define TESR_TCST4 0x0010 /* enable counter 4 */
+ #define TESR_TCST5 0x0014 /* enable counter 5 */
+ #define TESR_TCST6 0x0018 /* enable counter 6 */
+ #define TESR_TCST7 0x001c /* enable counter 7 */
+ #define TESR_OST 0x8000 /* enable OST */
+#define JZ_TC_TECR 0x10002018 /* TC enable clear reg. */
+
+/* operating system timer */
+#define JZ_OST_DATA 0x100020e0 /* compare */
+#define JZ_OST_CNT_LO 0x100020e4
+#define JZ_OST_CNT_HI 0x100020e8
+#define JZ_OST_CTRL 0x100020ec
+ #define OSTC_PCK_EN 0x0001 /* use PCLK */
+ #define OSTC_RTC_EN 0x0002 /* use RTCCLK */
+ #define OSTC_EXT_EN 0x0004 /* use EXTCLK */
+ #define OSTC_PRESCALE_M 0x0038
+ #define OSTC_DIV_1 0x0000
+ #define OSTC_DIV_4 0x0008
+ #define OSTC_DIV_16 0x0010
+ #define OSTC_DIV_64 0x0018
+ #define OSTC_DIV_256 0x0020
+ #define OSTC_DIV_1024 0x0028
+ #define OSTC_SHUTDOWN 0x0200
+ #define OSTC_MODE 0x8000 /* 0 - reset to 0 when = OST_DATA */
+#define JZ_OST_CNT_U32 0x100020fc /* copy of CNT_HI when reading CNT_LO */
+
+static inline void
+writereg(uint32_t reg, uint32_t val)
+{
+ *(int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;
+ wbflush();
+}
+
+static inline uint32_t
+readreg(uint32_t reg)
+{
+ wbflush();
+ return *(int32_t *)MIPS_PHYS_TO_KSEG1(reg);
+}
+
+#endif /* INGENIC_REGS_H */
\ No newline at end of file
