Module Name: src
Committed By: jmcneill
Date: Fri Dec 5 14:36:44 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_board.c awin_io.c awin_mmc.c
awin_reg.h awin_var.h
src/sys/arch/evbarm/conf: ALLWINNER_A80
Log Message:
A80 MMC support. Works for SD card slot on Cubie4, but not eMMC yet.
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/allwinner/awin_board.c
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/allwinner/awin_io.c
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/allwinner/awin_mmc.c
cvs rdiff -u -r1.59 -r1.60 src/sys/arch/arm/allwinner/awin_reg.h
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/allwinner/awin_var.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbarm/conf/ALLWINNER_A80
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_board.c
diff -u src/sys/arch/arm/allwinner/awin_board.c:1.30 src/sys/arch/arm/allwinner/awin_board.c:1.31
--- src/sys/arch/arm/allwinner/awin_board.c:1.30 Fri Dec 5 01:13:11 2014
+++ src/sys/arch/arm/allwinner/awin_board.c Fri Dec 5 14:36:44 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_board.c,v 1.30 2014/12/05 01:13:11 jmcneill Exp $ */
+/* $NetBSD: awin_board.c,v 1.31 2014/12/05 14:36:44 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -36,7 +36,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.30 2014/12/05 01:13:11 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.31 2014/12/05 14:36:44 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -128,8 +128,8 @@ awin_cpu_clk(void)
#if defined(ALLWINNER_A80)
const uint32_t c0cpux = bus_space_read_4(&awin_bs_tag, awin_core_bsh,
AWIN_A80_CCU_OFFSET + AWIN_A80_CCU_PLL_C0CPUX_CTRL_REG);
- const u_int p = (c0cpux & AWIN_A80_CCU_PLL_OUT_EXT_DIVP) ? 4 : 1;
- const u_int n = __SHIFTOUT(c0cpux, AWIN_A80_CCU_PLL_FACTOR_N);
+ const u_int p = (c0cpux & AWIN_A80_CCU_PLL_CxCPUX_OUT_EXT_DIVP) ? 4 : 1;
+ const u_int n = __SHIFTOUT(c0cpux, AWIN_A80_CCU_PLL_CxCPUX_FACTOR_N);
ci->ci_data.cpu_cc_freq = ((uint64_t)AWIN_REF_FREQ * n) / p;
#else
@@ -333,6 +333,8 @@ awin_pll6_enable(void)
bus_space_tag_t bst = &awin_bs_tag;
bus_space_handle_t bsh = awin_core_bsh;
+ KASSERT(awin_chip_id() != AWIN_CHIP_ID_A80);
+
/*
* SATA needs PLL6 to be a 100MHz clock.
*/
@@ -549,6 +551,7 @@ awin_pll5x_get_rate(void)
unsigned int n, k, p;
KASSERT(awin_chip_id() != AWIN_CHIP_ID_A31);
+ KASSERT(awin_chip_id() != AWIN_CHIP_ID_A80);
const uint32_t cfg = bus_space_read_4(bst, bsh,
AWIN_CCM_OFFSET + AWIN_PLL5_CFG_REG);
@@ -567,6 +570,8 @@ awin_pll6_get_rate(void)
bus_space_handle_t bsh = awin_core_bsh;
unsigned int n, k, m;
+ KASSERT(awin_chip_id() != AWIN_CHIP_ID_A80);
+
const uint32_t cfg = bus_space_read_4(bst, bsh,
AWIN_CCM_OFFSET + AWIN_PLL6_CFG_REG);
@@ -582,3 +587,22 @@ awin_pll6_get_rate(void)
return (AWIN_REF_FREQ * n * k) / m;
}
+
+uint32_t
+awin_periph0_get_rate(void)
+{
+ bus_space_tag_t bst = &awin_bs_tag;
+ bus_space_handle_t bsh = awin_core_bsh;
+ unsigned int n, idiv, odiv;
+
+ KASSERT(awin_chip_id() == AWIN_CHIP_ID_A80);
+
+ const uint32_t cfg = bus_space_read_4(bst, bsh,
+ AWIN_A80_CCU_OFFSET + AWIN_A80_CCU_PLL_PERIPH0_CTRL_REG);
+
+ n = __SHIFTOUT(cfg, AWIN_A80_CCU_PLL_PERIPH0_FACTOR_N);
+ idiv = __SHIFTOUT(cfg, AWIN_A80_CCU_PLL_PERIPH0_INPUT_DIV) + 1;
+ odiv = __SHIFTOUT(cfg, AWIN_A80_CCU_PLL_PERIPH0_OUTPUT_DIV) + 1;
+
+ return ((AWIN_REF_FREQ * n) / idiv) / odiv;
+}
Index: src/sys/arch/arm/allwinner/awin_io.c
diff -u src/sys/arch/arm/allwinner/awin_io.c:1.31 src/sys/arch/arm/allwinner/awin_io.c:1.32
--- src/sys/arch/arm/allwinner/awin_io.c:1.31 Fri Dec 5 11:53:43 2014
+++ src/sys/arch/arm/allwinner/awin_io.c Fri Dec 5 14:36:44 2014
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.31 2014/12/05 11:53:43 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.32 2014/12/05 14:36:44 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -204,11 +204,23 @@ awinio_attach(device_t parent, device_t
sc->sc_dmat = &awin_dma_tag;
sc->sc_coherent_dmat = &awin_coherent_dma_tag;
- bus_space_subregion(sc->sc_bst, sc->sc_bsh, AWIN_CCM_OFFSET, 0x1000,
- &sc->sc_ccm_bsh);
+ switch (awin_chip_id()) {
+ case AWIN_CHIP_ID_A80:
+ bus_space_subregion(sc->sc_bst, sc->sc_bsh,
+ AWIN_A80_CCU_SCLK_OFFSET, 0x1000, &sc->sc_ccm_bsh);
+ break;
+ default:
+ bus_space_subregion(sc->sc_bst, sc->sc_bsh, AWIN_CCM_OFFSET,
+ 0x1000, &sc->sc_ccm_bsh);
+ break;
+ }
aprint_naive("\n");
- aprint_normal(": %s (0x%04x)\n", chip_name, chip_id);
+ aprint_normal(": %s", chip_name);
+ if ((chip_id & 0xff00) != 0xff00) {
+ aprint_normal(" (0x%04x)\n", chip_id);
+ }
+ aprint_normal("\n");
const struct awin_locators * const eloc =
awin_locators + __arraycount(awin_locators);
Index: src/sys/arch/arm/allwinner/awin_mmc.c
diff -u src/sys/arch/arm/allwinner/awin_mmc.c:1.16 src/sys/arch/arm/allwinner/awin_mmc.c:1.17
--- src/sys/arch/arm/allwinner/awin_mmc.c:1.16 Thu Dec 4 03:03:44 2014
+++ src/sys/arch/arm/allwinner/awin_mmc.c Fri Dec 5 14:36:44 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_mmc.c,v 1.16 2014/12/04 03:03:44 jmcneill Exp $ */
+/* $NetBSD: awin_mmc.c,v 1.17 2014/12/05 14:36:44 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill <[email protected]>
@@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: awin_mmc.c,v 1.16 2014/12/04 03:03:44 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: awin_mmc.c,v 1.17 2014/12/05 14:36:44 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -46,7 +46,14 @@ __KERNEL_RCSID(0, "$NetBSD: awin_mmc.c,v
#include <arm/allwinner/awin_var.h>
#define AWIN_MMC_NDESC 16
-#define AWIN_MMC_DMA_FTRGLEVEL 0x20070008
+#define AWIN_MMC_DMA_FTRGLEVEL_A20 0x20070008
+#define AWIN_MMC_DMA_FTRGLEVEL_A80 0x200f0010
+
+static const struct awin_gpio_pinset awin_mmc_pinsets_a80[4] = {
+ [0] = { 'F', AWIN_A80_PIO_PF_SDMMC0_FUNC, AWIN_A80_PIO_PF_SDMMC0_PINS },
+ [1] = { 'G', AWIN_A80_PIO_PG_SDMMC1_FUNC, AWIN_A80_PIO_PG_SDMMC1_PINS },
+ [2] = { 'C', AWIN_A80_PIO_PC_SDMMC2_FUNC, AWIN_A80_PIO_PC_SDMMC2_PINS },
+};
static int awin_mmc_match(device_t, cfdata_t, void *);
static void awin_mmc_attach(device_t, device_t, void *);
@@ -88,6 +95,7 @@ struct awin_mmc_softc {
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
bus_space_handle_t sc_clk_bsh;
+ bus_space_handle_t sc_comm_bsh;
bus_dma_tag_t sc_dmat;
bool sc_use_dma;
@@ -99,10 +107,12 @@ struct awin_mmc_softc {
int sc_mmc_width;
int sc_mmc_present;
+ int sc_mmc_port;
device_t sc_sdmmc_dev;
uint32_t sc_fifo_reg;
+ uint32_t sc_dma_ftrglevel;
uint32_t sc_idma_xferlen;
bus_dma_segment_t sc_idma_segs[1];
@@ -203,13 +213,12 @@ awin_mmc_attach(device_t parent, device_
sc->sc_dev = self;
sc->sc_bst = aio->aio_core_bst;
sc->sc_dmat = aio->aio_dmat;
+ sc->sc_mmc_port = loc->loc_port;
mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO);
cv_init(&sc->sc_intr_cv, "awinmmcirq");
cv_init(&sc->sc_idst_cv, "awinmmcdma");
bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
- bus_space_subregion(sc->sc_bst, aio->aio_ccm_bsh,
- AWIN_SD0_CLK_REG + (loc->loc_port * 4), 0, &sc->sc_clk_bsh);
sc->sc_use_dma = true;
prop_dictionary_get_bool(cfg, "dma", &sc->sc_use_dma);
@@ -217,15 +226,47 @@ awin_mmc_attach(device_t parent, device_
aprint_naive("\n");
aprint_normal(": SD3.0 (%s)\n", sc->sc_use_dma ? "DMA" : "PIO");
- awin_pll6_enable();
+ if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+
+ if (awin_mmc_pinsets_a80[loc->loc_port].pinset_group) {
+ awin_gpio_pinset_acquire(
+ &awin_mmc_pinsets_a80[loc->loc_port]);
+ }
+
+ bus_space_subregion(sc->sc_bst, aio->aio_ccm_bsh,
+ AWIN_A80_CCU_SCLK_SDMMC0_CLK_REG + (loc->loc_port * 4), 4,
+ &sc->sc_clk_bsh);
+ bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
+ AWIN_A80_SDMMC_COMM_OFFSET + (loc->loc_port * 4), 4,
+ &sc->sc_comm_bsh);
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_A80_CCU_SCLK_BUS_CLK_GATING0_REG,
+ AWIN_A80_CCU_SCLK_BUS_CLK_GATING0_SD, 0);
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_A80_CCU_SCLK_BUS_SOFT_RST0_REG,
+ AWIN_A80_CCU_SCLK_BUS_SOFT_RST0_SD, 0);
+
+ const uint32_t comm = bus_space_read_4(sc->sc_bst,
+ sc->sc_comm_bsh, 0);
+ bus_space_write_4(sc->sc_bst, sc->sc_comm_bsh, 0,
+ comm |
+ AWIN_A80_SDMMC_COMM_SDC_RESET_SW |
+ AWIN_A80_SDMMC_COMM_SDC_CLOCK_SW);
+ delay(1000);
+ } else {
+ bus_space_subregion(sc->sc_bst, aio->aio_ccm_bsh,
+ AWIN_SD0_CLK_REG + (loc->loc_port * 4), 4, &sc->sc_clk_bsh);
+
+ awin_pll6_enable();
- awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
- AWIN_AHB_GATING0_REG,
- AWIN_AHB_GATING0_SDMMC0 << loc->loc_port, 0);
- if (awin_chip_id() == AWIN_CHIP_ID_A31) {
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
- AWIN_A31_AHB_RESET0_REG,
- AWIN_A31_AHB_RESET0_SD0_RST << loc->loc_port, 0);
+ AWIN_AHB_GATING0_REG,
+ AWIN_AHB_GATING0_SDMMC0 << loc->loc_port, 0);
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_A31_AHB_RESET0_REG,
+ AWIN_A31_AHB_RESET0_SD0_RST << loc->loc_port, 0);
+ }
}
if (prop_dictionary_get_cstring_nocopy(cfg, "detect-gpio", &pin_name)) {
@@ -253,10 +294,19 @@ awin_mmc_attach(device_t parent, device_
}
}
- if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ switch (awin_chip_id()) {
+ case AWIN_CHIP_ID_A80:
sc->sc_fifo_reg = AWIN_A31_MMC_FIFO;
- } else {
+ sc->sc_dma_ftrglevel = AWIN_MMC_DMA_FTRGLEVEL_A80;
+ break;
+ case AWIN_CHIP_ID_A31:
+ sc->sc_fifo_reg = AWIN_A31_MMC_FIFO;
+ sc->sc_dma_ftrglevel = AWIN_MMC_DMA_FTRGLEVEL_A20;
+ break;
+ default:
sc->sc_fifo_reg = AWIN_MMC_FIFO;
+ sc->sc_dma_ftrglevel = AWIN_MMC_DMA_FTRGLEVEL_A20;
+ break;
}
if (sc->sc_use_dma) {
@@ -293,7 +343,7 @@ awin_mmc_attach_i(device_t self)
saa.saa_sct = &awin_mmc_chip_functions;
saa.saa_sch = sc;
saa.saa_clkmin = 400;
- saa.saa_clkmax = 50000;
+ saa.saa_clkmax = awin_chip_id() == AWIN_CHIP_ID_A80 ? 48000 : 50000;
saa.saa_caps = SMC_CAPS_4BIT_MODE|
SMC_CAPS_8BIT_MODE|
SMC_CAPS_SD_HIGHSPEED|
@@ -394,13 +444,28 @@ static int
awin_mmc_host_reset(sdmmc_chipset_handle_t sch)
{
struct awin_mmc_softc *sc = sch;
+ int retry = 1000;
#ifdef AWIN_MMC_DEBUG
aprint_normal_dev(sc->sc_dev, "host reset\n");
#endif
+ if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+ if (sc->sc_mmc_port == 2 || sc->sc_mmc_port == 3) {
+ MMC_WRITE(sc, AWIN_MMC_HWRST, 0);
+ delay(10);
+ MMC_WRITE(sc, AWIN_MMC_HWRST, 1);
+ delay(300);
+ }
+ }
+
MMC_WRITE(sc, AWIN_MMC_GCTRL,
MMC_READ(sc, AWIN_MMC_GCTRL) | AWIN_MMC_GCTRL_RESET);
+ while (--retry > 0) {
+ if (!(MMC_READ(sc, AWIN_MMC_GCTRL) & AWIN_MMC_GCTRL_RESET))
+ break;
+ delay(100);
+ }
MMC_WRITE(sc, AWIN_MMC_IMASK,
AWIN_MMC_INT_CMD_DONE | AWIN_MMC_INT_ERROR |
@@ -487,6 +552,24 @@ awin_mmc_update_clock(struct awin_mmc_so
if (retry == 0) {
aprint_error_dev(sc->sc_dev, "timeout updating clock\n");
+#ifdef AWIN_MMC_DEBUG
+ device_printf(sc->sc_dev, "GCTRL: 0x%08x\n",
+ MMC_READ(sc, AWIN_MMC_GCTRL));
+ device_printf(sc->sc_dev, "CLKCR: 0x%08x\n",
+ MMC_READ(sc, AWIN_MMC_CLKCR));
+ device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n",
+ MMC_READ(sc, AWIN_MMC_TIMEOUT));
+ device_printf(sc->sc_dev, "WIDTH: 0x%08x\n",
+ MMC_READ(sc, AWIN_MMC_WIDTH));
+ device_printf(sc->sc_dev, "CMD: 0x%08x\n",
+ MMC_READ(sc, AWIN_MMC_CMD));
+ device_printf(sc->sc_dev, "MINT: 0x%08x\n",
+ MMC_READ(sc, AWIN_MMC_MINT));
+ device_printf(sc->sc_dev, "RINT: 0x%08x\n",
+ MMC_READ(sc, AWIN_MMC_RINT));
+ device_printf(sc->sc_dev, "STATUS: 0x%08x\n",
+ MMC_READ(sc, AWIN_MMC_STATUS));
+#endif
return ETIMEDOUT;
}
@@ -498,16 +581,23 @@ awin_mmc_bus_clock(sdmmc_chipset_handle_
{
struct awin_mmc_softc *sc = sch;
uint32_t odly, sdly, clkcr, clksrc, n, m;
- u_int pll_freq = awin_pll6_get_rate() / 1000;
u_int osc24m_freq = AWIN_REF_FREQ / 1000;
+ uint32_t pll_freq;
+
+ if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+ pll_freq = awin_periph0_get_rate() / 1000;
+ } else {
+ pll_freq = awin_pll6_get_rate() / 1000;
+ }
#ifdef AWIN_MMC_DEBUG
- aprint_normal_dev(sc->sc_dev, "freq = %d\n", freq);
+ aprint_normal_dev(sc->sc_dev, "freq = %d, pll_freq = %d\n",
+ freq, pll_freq);
#endif
if (freq <= 400) {
odly = 0;
- sdly = awin_chip_id() == AWIN_CHIP_ID_A31 ? 0 : 7;
+ sdly = 0;
clksrc = AWIN_SD_CLK_SRC_SEL_OSC24M;
n = 2;
m = ((osc24m_freq / (1 << n)) / freq) - 1;
@@ -515,24 +605,26 @@ awin_mmc_bus_clock(sdmmc_chipset_handle_
odly = 0;
sdly = 5;
clksrc = AWIN_SD_CLK_SRC_SEL_PLL6;
- n = 0;
- m = (pll_freq / freq) - 1;
+ n = awin_chip_id() == AWIN_CHIP_ID_A80 ? 2 : 0;
+ m = ((pll_freq / freq) / (1 << n)) - 1;
} else if (freq <= 50000) {
- odly = 3;
- sdly = 5;
+ odly = awin_chip_id() == AWIN_CHIP_ID_A80 ? 5 : 3;
+ sdly = awin_chip_id() == AWIN_CHIP_ID_A80 ? 4 : 5;
clksrc = AWIN_SD_CLK_SRC_SEL_PLL6;
- n = 0;
- m = (pll_freq / freq) - 1;
+ n = awin_chip_id() == AWIN_CHIP_ID_A80 ? 2 : 0;
+ m = ((pll_freq / freq) / (1 << n)) - 1;
} else {
/* UHS speeds not implemented yet */
return 1;
}
clkcr = MMC_READ(sc, AWIN_MMC_CLKCR);
- clkcr &= ~AWIN_MMC_CLKCR_CARDCLKON;
- MMC_WRITE(sc, AWIN_MMC_CLKCR, clkcr);
- if (awin_mmc_update_clock(sc) != 0)
- return 1;
+ if (clkcr & AWIN_MMC_CLKCR_CARDCLKON) {
+ clkcr &= ~AWIN_MMC_CLKCR_CARDCLKON;
+ MMC_WRITE(sc, AWIN_MMC_CLKCR, clkcr);
+ if (awin_mmc_update_clock(sc) != 0)
+ return 1;
+ }
if (freq) {
@@ -707,7 +799,7 @@ awin_mmc_dma_prepare(struct awin_mmc_sof
val |= AWIN_MMC_IDST_TRANSMIT_INT;
MMC_WRITE(sc, AWIN_MMC_IDIE, val);
MMC_WRITE(sc, AWIN_MMC_DLBA, desc_paddr);
- MMC_WRITE(sc, AWIN_MMC_FTRGLEVEL, AWIN_MMC_DMA_FTRGLEVEL);
+ MMC_WRITE(sc, AWIN_MMC_FTRGLEVEL, sc->sc_dma_ftrglevel);
return 0;
}
@@ -765,6 +857,11 @@ awin_mmc_exec_command(sdmmc_chipset_hand
sc->sc_intr_rint = 0;
+ if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+ MMC_WRITE(sc, AWIN_MMC_A12A,
+ (cmdval & AWIN_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff);
+ }
+
MMC_WRITE(sc, AWIN_MMC_ARG, cmd->c_arg);
#ifdef AWIN_MMC_DEBUG
Index: src/sys/arch/arm/allwinner/awin_reg.h
diff -u src/sys/arch/arm/allwinner/awin_reg.h:1.59 src/sys/arch/arm/allwinner/awin_reg.h:1.60
--- src/sys/arch/arm/allwinner/awin_reg.h:1.59 Fri Dec 5 11:53:43 2014
+++ src/sys/arch/arm/allwinner/awin_reg.h Fri Dec 5 14:36:44 2014
@@ -631,6 +631,8 @@
#define AWIN_MMC_CBCR 0x0048
#define AWIN_MMC_BBCR 0x004C
#define AWIN_MMC_DBGC 0x0050
+#define AWIN_MMC_A12A 0x0058 /* A80 */
+#define AWIN_MMC_HWRST 0x0078 /* A80 */
#define AWIN_MMC_DMAC 0x0080
#define AWIN_MMC_DLBA 0x0084
#define AWIN_MMC_IDST 0x0088
@@ -2654,6 +2656,7 @@ struct awin_a31_dma_desc {
*/
#define AWIN_A80_GIC_BASE 0x01c40000
+#define AWIN_A80_SDMMC_COMM_OFFSET 0x00013000
#define AWIN_A80_CCU_OFFSET 0x04400000
#define AWIN_A80_CCU_SCLK_OFFSET 0x04400400
#define AWIN_A80_PIO_OFFSET 0x04400800
@@ -2675,22 +2678,84 @@ struct awin_a31_dma_desc {
#define AWIN_A80_TWI3_OFFSET 0x05403400
#define AWIN_A80_TWI4_OFFSET 0x05403800
-#define AWIN_A80_CCU_PLL_C0CPUX_CTRL_REG 0x0000
-#define AWIN_A80_CCU_PLL_C1CPUX_CTRL_REG 0x0000
+#define AWIN_A80_SDMMC_COMM_SDC_RESET_SW __BIT(18)
+#define AWIN_A80_SDMMC_COMM_SDC_CLOCK_SW __BIT(16)
-#define AWIN_A80_CCU_PLL_ENABLE __BIT(31)
-#define AWIN_A80_CCU_PLL_LOCK_TIME __BITS(26,24)
-#define AWIN_A80_CCU_PLL_OUT_EXT_DIVP __BIT(16)
-#define AWIN_A80_CCU_PLL_FACTOR_N __BITS(15,8)
-#define AWIN_A80_CCU_PLL_POSTDIV_M __BITS(1,0)
+#define AWIN_A80_CCU_PLL_C0CPUX_CTRL_REG 0x0000
+#define AWIN_A80_CCU_PLL_C1CPUX_CTRL_REG 0x0004
+#define AWIN_A80_CCU_PLL_AUDIO_CTRL_REG 0x0008
+#define AWIN_A80_CCU_PLL_PERIPH0_CTRL_REG 0x000c
+#define AWIN_A80_CCU_PLL_VE_CTRL_REG 0x0010
+#define AWIN_A80_CCU_PLL_DDR_CTRL_REG 0x0014
+#define AWIN_A80_CCU_PLL_VIDEO0_CTRL_REG 0x0018
+#define AWIN_A80_CCU_PLL_VIDEO1_CTRL_REG 0x001c
+#define AWIN_A80_CCU_PLL_GPU_CTRL_REG 0x0020
+#define AWIN_A80_CCU_PLL_DE_CTRL_REG 0x0024
+#define AWIN_A80_CCU_PLL_ISP_CTRL_REG 0x0028
+#define AWIN_A80_CCU_PLL_PERIPH1_CTRL_REG 0x002c
+
+#define AWIN_A80_CCU_PLL_CxCPUX_ENABLE __BIT(31)
+#define AWIN_A80_CCU_PLL_CxCPUX_LOCK_TIME __BITS(26,24)
+#define AWIN_A80_CCU_PLL_CxCPUX_OUT_EXT_DIVP __BIT(16)
+#define AWIN_A80_CCU_PLL_CxCPUX_FACTOR_N __BITS(15,8)
+#define AWIN_A80_CCU_PLL_CxCPUX_POSTDIV_M __BITS(1,0)
+
+#define AWIN_A80_CCU_PLL_PERIPH0_ENABLE __BIT(31)
+#define AWIN_A80_CCU_PLL_PERIPH0_SDM_ENABLE __BIT(24)
+#define AWIN_A80_CCU_PLL_PERIPH0_OUTPUT_DIV __BIT(18)
+#define AWIN_A80_CCU_PLL_PERIPH0_INPUT_DIV __BIT(16)
+#define AWIN_A80_CCU_PLL_PERIPH0_FACTOR_N __BITS(15,8)
+
+#define AWIN_A80_CCU_SCLK_SDMMC0_CLK_REG 0x0010
+#define AWIN_A80_CCU_SCLK_SDMMC1_CLK_REG 0x0014
+#define AWIN_A80_CCU_SCLK_SDMMC2_CLK_REG 0x0018
+#define AWIN_A80_CCU_SCLK_SDMMC3_CLK_REG 0x001c
+
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING0_REG 0x0180
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_REG 0x0184
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING2_REG 0x0188
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING3_REG 0x0190
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_REG 0x0194
+
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST0_REG 0x01a0
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_REG 0x01a4
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST2_REG 0x01a8
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST3_REG 0x01b0
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_REG 0x01b4
+
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING0_SD __BIT(8)
+
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST0_SD __BIT(8)
+
+#define AWIN_A80_CCU_SCLK_SDMMC_SCLK_GATING __BIT(31)
+#define AWIN_A80_CCU_SCLK_SDMMC_CLK_SRC_SEL __BITS(27,24)
+#define AWIN_A80_CCU_SCLK_SDMMC_CLK_SRC_SEL_OSC24M 0
+#define AWIN_A80_CCU_SCLK_SDMMC_CLK_SRC_SEL_PERIPH0 1
+#define AWIN_A80_CCU_SCLK_SDMMC_SAMPLE_CLK_PHASE_CTR __BITS(22,20)
+#define AWIN_A80_CCU_SCLK_SDMMC_CLK_DIV_RATIO_N __BITS(17,16)
+#define AWIN_A80_CCU_SCLK_SDMMC_OUTPUT_CLK_PHASE_CTR __BITS(10,8)
+#define AWIN_A80_CCU_SCLK_SDMMC_CLK_DIV_RATIO_M __BITS(3,0)
#define AWIN_A80_PIO_PA_PINS 18
+
#define AWIN_A80_PIO_PB_PINS 20
+
#define AWIN_A80_PIO_PC_PINS 20
+#define AWIN_A80_PIO_PC_SDMMC2_FUNC 3
+#define AWIN_A80_PIO_PC_SDMMC2_PINS 0x0001ffc0 /* PC pins 16-6 */
+
#define AWIN_A80_PIO_PD_PINS 28
+
#define AWIN_A80_PIO_PE_PINS 21
+
#define AWIN_A80_PIO_PF_PINS 6
+#define AWIN_A80_PIO_PF_SDMMC0_FUNC 2
+#define AWIN_A80_PIO_PF_SDMMC0_PINS 0x0000003f /* PF pins 5-0 */
+
#define AWIN_A80_PIO_PG_PINS 16
+#define AWIN_A80_PIO_PG_SDMMC1_FUNC 2
+#define AWIN_A80_PIO_PG_SDMMC1_PINS 0x0000003f /* PG pins 5-0 */
+
#define AWIN_A80_PIO_PH_PINS 22
#endif /* _ARM_ALLWINNER_AWIN_REG_H_ */
Index: src/sys/arch/arm/allwinner/awin_var.h
diff -u src/sys/arch/arm/allwinner/awin_var.h:1.28 src/sys/arch/arm/allwinner/awin_var.h:1.29
--- src/sys/arch/arm/allwinner/awin_var.h:1.28 Fri Dec 5 01:13:11 2014
+++ src/sys/arch/arm/allwinner/awin_var.h Fri Dec 5 14:36:44 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_var.h,v 1.28 2014/12/05 01:13:11 jmcneill Exp $ */
+/* $NetBSD: awin_var.h,v 1.29 2014/12/05 14:36:44 jmcneill Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -103,6 +103,7 @@ void awin_pll7_enable(void);
void awin_pll3_set_rate(uint32_t);
uint32_t awin_pll5x_get_rate(void);
uint32_t awin_pll6_get_rate(void);
+uint32_t awin_periph0_get_rate(void);
void awin_cpu_hatch(struct cpu_info *);
#define AWIN_CHIP_ID_A10 AWIN_SRAM_VER_KEY_A10
Index: src/sys/arch/evbarm/conf/ALLWINNER_A80
diff -u src/sys/arch/evbarm/conf/ALLWINNER_A80:1.1 src/sys/arch/evbarm/conf/ALLWINNER_A80:1.2
--- src/sys/arch/evbarm/conf/ALLWINNER_A80:1.1 Fri Dec 5 01:13:12 2014
+++ src/sys/arch/evbarm/conf/ALLWINNER_A80 Fri Dec 5 14:36:44 2014
@@ -1,4 +1,4 @@
-# $NetBSD: ALLWINNER_A80,v 1.1 2014/12/05 01:13:12 jmcneill Exp $
+# $NetBSD: ALLWINNER_A80,v 1.2 2014/12/05 14:36:44 jmcneill Exp $
#
# ALLWINNER_A80 - Allwinner A80 boards (Cubieboard4, OptimusBoard, etc)
#
@@ -195,9 +195,13 @@ armgtmr0 at armperiph? # ARM Generic
awinio0 at mainbus?
# SD/MMC controllers
-#awinmmc0 at awinio0 port 0
-#sdmmc* at awinmmc?
-#ld* at sdmmc?
+awinmmc0 at awinio0 port 0
+sdmmc0 at awinmmc0
+ld0 at sdmmc0
+
+#awinmmc2 at awinio0 port 2
+#sdmmc2 at awinmmc2
+#ld2 at sdmmc2
# Interrupt Controller
awinicu0 at awinio0
